CN110581069A - 制造高压半导体器件的方法 - Google Patents

制造高压半导体器件的方法 Download PDF

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Publication number
CN110581069A
CN110581069A CN201910167923.9A CN201910167923A CN110581069A CN 110581069 A CN110581069 A CN 110581069A CN 201910167923 A CN201910167923 A CN 201910167923A CN 110581069 A CN110581069 A CN 110581069A
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pattern
region
conductivity type
forming
barrier
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朴淳烈
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SK Hynix System IC Inc
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SK Hynix System IC Inc
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    • H01L21/823493—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
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Abstract

一种制造高压半导体器件的方法包括：在缓冲绝缘层上形成阻挡图案，所述缓冲绝缘层设置在第二导电类型的半导体区域中的第一区域上方；在缓冲绝缘层上方形成具有开口的离子注入掩模图案，以通过离子注入掩模图案的开口暴露出阻挡图案，以及使用离子注入掩模图案，将用于形成第一导电类型的体区的第一导电类型的杂质离子注入到第一区域中。

Description

制造高压半导体器件的方法
相关申请的交叉引用
本申请要求2018年6月11日提交的申请号为10-2018-0066708的韩国专利申请的优先权，其公开内容通过引用整体合并于此。
技术领域
本公开的各种实施例涉及高压半导体器件，以及更具体地，涉及制造用于抑制阱邻近效应的高压半导体器件的方法。
背景技术
能够执行控制器和驱动器两种功能的集成电路可以用在智能功率设备中。而且，智能功率设备的输出电路可以被设计为包括在高电压下工作的横向双扩散MOS(LDMOS)晶体管，如所谓的“高压半导体器件”。因此，LDMOS晶体管的击穿电压(例如，漏结击穿电压和栅介质击穿电压)是可能直接影响LDMOS晶体管的稳定操作的重要因素。另外，LDMOS晶体管的导通电阻(Ron)值也可以是可能影响LDMOS晶体管的电特性(例如，LDMOS晶体管的电流驱动能力)的重要因素。
发明内容
根据一个实施例，提供了一种制造高压半导体器件的方法。该方法包括：在缓冲绝缘层上方形成用于阻挡杂质离子的阻挡图案，所述缓冲绝缘层设置在第二导电类型的半导体区域中的第一区域上方；在所述缓冲绝缘层上方形成具有开口的离子注入掩模图案，以通过离子注入掩模图案的开口暴露出所述阻挡图案，以及使用所述离子注入掩模图案，将用于形成第一导电类型的体区的第一导电类型的杂质离子注入第一区域。
根据另一实施例，提供了一种制造高压半导体器件的方法。该方法包括：在缓冲绝缘层上方形成第一阻挡图案和第二阻挡图案，所述第一阻挡图案与第二阻挡图案被定位成彼此间隔开以阻挡杂质离子，所述缓冲绝缘层设置在第二导电类型的半导体区域中的第一区域上方。在所述缓冲绝缘层上方形成具有开口的离子注入掩模图案，以通过离子注入掩模图案的开口暴露出第一阻挡图案和第二阻挡图案。使用所述离子注入掩模图案，将用于形成第一导电类型的体区的杂质离子注入到第一区域中。在将第一导电类型的杂质离子注入第一区域之后，去除第一阻挡图案和第二阻挡图案。
附图说明
鉴于附图和随附的详细描述，本公开的各种实施例将变得更加明显，其中：
图1至图7是示出根据本公开的实施例的制造高压半导体器件的方法的截面图；以及
图8和图9是示出根据本公开的实施例的制造高压半导体器件的方法的截面图。
具体实施方式
在以下实施方案的描述中，应理解术语“第一”和“第二”旨在标识元件，而不用于仅定义元件本身或表示特定序列。另外，当一个元件被称为位于另一个元件“上”、“上方”、“以上”、“下”或“下方”时，它意味着相对位置关系，但不用于限制该元件直接接触该另一元件或者在它们之间存在至少一个中间元件的某些情况。因此，本文使用的诸如“上”、“上方”、“以上”、“下”、“下方”、“以下”等术语仅用于描述特定实施例的目的，并非旨在限制本公开的范围。此外，当一个元件被称为“连接”或“耦接”到另一个元件时，该元件可以直接电地或机械地连接或耦接到另一个元件，或者可以通过替换其间的另一个元件以形成连接关系或耦接关系。
各种实施例涉及制造高压半导体器件的方法。
用于改善高压半导体器件的导通电阻(Ron)特性的各种方法之一是在高压半导体器件的沟道长度方向上减小高压半导体器件的节距尺寸。在这种情况下，也可以减小高压半导体器件的体区的宽度。就N沟道LDMOS晶体管而言，与栅电极重叠的体区可以用作沟道区。由于沟道区的掺杂浓度可能直接影响N沟道LDMOS晶体管的阈值电压，因此可能需要精确地控制沟道区的掺杂浓度。在体区中沟道区的掺杂浓度可能主要受用于形成体区的离子注入工艺的影响。由于在用于形成体区的离子注入工艺期间发生的阱邻近效应(WPE)，在体区中沟道区的掺杂浓度可能不期望地增大。阱邻近效应(WPE)是指由于当朝向晶片行进的杂质离子被用作离子注入掩模的光刻胶图案的侧表面和栅极的侧表面散射以被注入不需要的区域时在纳米级别上发生的现象引起的效应。本公开的各种实施例将提供制造高压半导体器件的方法，所述高压半导体器件能够抑制由于阱邻近效应(WPE)而导致在体区中的沟道区的掺杂浓度不期望地增大的现象。
图1至图7是示出根据本公开的实施例的制造高压半导体器件的方法的截面图。尽管本实施例结合制造N沟道高压半导体器件的方法进行描述，但是本公开也可以同样适用于利用将每个掺杂区域的导电类型都改变成相反的导电类型来制造P沟道高压半导体器件的方法。参考图1，具有第二导电类型的掩埋层104(例如，N型掩埋层)可以形成在第一导电类型的衬底102(例如，P型衬底)的一部分上。在一个实施例中，衬底102可以是硅衬底。P型外延层106可以形成在衬底102上以覆盖掩埋层104。掩埋层104和外延层106可以使用本领域公知的方法和材料来形成，因此，不需要进一步描述。
参考图2，P型掩埋层108可以形成在P型外延层(图1中的106)的下部。N型半导体区域(即，N型漂移区110)可以形成在P型外延层(图1中的106)的上部。接下来，可以形成穿透N型漂移区110和P型掩埋层108的P型阱区112。在一个实施例中，P型阱区112可以被形成为使得P型阱区112的底表面与衬底102的顶表面接触。P型阱区112可以用作隔离区域，其使根据本实施例制造的高压半导体器件和与高压半导体器件相邻的其他器件电地和物理地隔离。然后可以在P型阱区112中形成器件隔离层114。在一个实施例中，可以使用沟槽隔离工艺来形成器件隔离层114。
参考图3，可以在N型漂移区110的表面、P型阱区112的表面和器件隔离层114的表面上形成绝缘层113。绝缘层113可以在离子注入工艺期间用作缓冲层。另外，绝缘层113也可以用作栅极绝缘层。在一个实施例中，绝缘层113可以由氧化物层形成。场板绝缘图案115和阻挡图案116可以形成在绝缘层113上。阻挡图案116可以被形成为位于第一区域202(在后续工艺中在其中形成体区)上。第一区域202可以位于由器件隔离层114限定的区域的中央。场板绝缘图案115可以被形成为位于第一区域202与器件隔离层114之间的区域上。场板绝缘图案115和阻挡图案116两者可以被形成为具有平面结构。也就是说，场板绝缘图案115的底表面可以与阻挡图案116的底表面共面，并且还可以与绝缘层113的顶表面共面。场板绝缘图案115的顶表面可以与阻挡图案116的顶表面共面。在一个实施例中，场板绝缘图案115和阻挡图案116可以由相同的材料层(例如，氧化物层)来形成。在一个实施例中，场板绝缘图案115和阻挡图案116可以通过相同的沉积工艺和相同的图案化工艺来形成。更具体地，可以在绝缘层113上沉积绝缘材料层，并且可以在绝缘材料层上形成掩模图案。可以通过图案化工艺将绝缘材料层图案化，该图案化工艺包括使用掩模图案作为刻蚀掩模而执行的刻蚀工艺，从而同时形成场板绝缘图案115和阻挡图案116。在另一个实施例中，场板绝缘图案115和阻挡图案116可以单独地形成。在这种情况下，在形成场板绝缘图案115之后，可以使用另一沉积工艺和另一图案化工艺来形成阻挡图案116。
参考图4，栅电极118和光刻胶图案120可以形成在场板绝缘图案115和绝缘层113上。例如，导电层可以形成在绝缘层113上以覆盖场板绝缘图案115和阻挡图案116，以及导电层可以被图案化以形成栅极图案117，该栅极图案117覆盖场板绝缘图案115、阻挡图案116以及在场板绝缘图案115与阻挡图案116之间的绝缘层113。在一个实施例中，当从平面图观察时，场板绝缘图案115可以被形成为具有闭环形状(诸如环形图案)。在这种情况下，阻挡图案116可以被场板绝缘图案115围绕并与场板绝缘图案115间隔开。随后，光刻胶图案120可以形成在绝缘层113上以暴露出栅极图案117的中央区域并且覆盖栅极图案的边缘。然后栅极图案117的中央部分可以使用光刻胶图案120作为刻蚀掩模来刻蚀以形成栅电极118，所述栅电极118提供暴露出阻挡图案116和与阻挡图案116相邻的绝缘层113的一部分的开口119。与栅电极118垂直重叠的绝缘层113和场板绝缘图案115可以用作栅极绝缘层。在一个实施例中，栅电极118可以由掺杂的多晶硅层来形成。光刻胶图案120可以被形成为提供开口119，该开口119暴露出第一区域202(在后续工艺中在其中形成体区)上的绝缘层113的一部分。通过开口119暴露出的光刻胶图案120的侧表面可以具有正倾斜轮廓。由于开口119的侧表面的正倾斜轮廓，开口119的宽度(例如，平面图中的直径)可以朝向衬底102逐渐减小。
光刻胶图案120的限定开口119的侧表面可以与栅电极118的内侧表面对齐。因此，栅电极118的内侧表面和光刻胶图案120的侧表面可以通过开口119来暴露。如上所述，可以通过使用光刻胶图案120作为刻蚀掩模而执行的刻蚀工艺来刻蚀栅极图案117的中央部分(覆盖第一区域202上的绝缘层113和阻挡图案116)以形成栅电极118来提供开口119。在这种情况下，栅电极118的内侧表面也可以具有正倾斜轮廓。虽然未在图中示出，但是薄绝缘层可以设置在栅电极118的由开口119暴露出的内侧表面上。如图4中的箭头所示，可以使用栅电极118和光刻胶图案120作为注入掩模来将P型杂质离子注入到第一区域202中，以形成P型体区。在一个实施例中，P型杂质离子可以在垂直于衬底102的表面的方向上注入。在一个实施例中，P型杂质离子可以是硼(B)离子。作为P型杂质离子的离子注入的结果，可以在N型漂移区110的第一区域202中形成掺杂区域。
如图5中更具体地示出，阻挡图案116可以抑制在用于形成P型体区的离子注入工艺期间由于阱邻近效应(WPE)导致的第二区域152的掺杂浓度增大的现象。第二区域152表示位于P型体区中以与栅电极118垂直重叠的沟道区域。具体地，如图5所示，朝向栅电极118的倾斜内侧表面或光刻胶图案120的倾斜侧表面行进的P型杂质离子302可以在栅电极118的倾斜内侧表面或光刻胶图案120的倾斜侧表面上反射，以朝向第二区域152散射(参见箭头304)。在本实施例中，阻挡图案116可以位于散射的P型杂质离子朝向第二区域152行进的路径304中，从而防止散射的P型杂质离子被注入到第二区域152中。在将P型杂质离子注入到第一区域202中之后，可以去除光刻胶图案120和阻挡图案116。尽管未在附图中示出，但是在注入用于形成P型体区的P型杂质离子之后，可以另外将N型杂质离子注入第二区域152中，以更精确地调节高压半导体器件的阈值电压。
参考图6，注入到第一区域202中的P型杂质离子可以使用扩散工艺扩散以形成P型体区111。在形成P型体区111之后，可以在栅电极118的侧表面上形成栅极侧壁间隔件122。随后，可以利用适当的离子注入掩模来注入N型杂质离子，并且可以利用另一种适当的离子注入掩模来注入P型杂质离子。此后，可以执行扩散工艺以同时在N型漂移区110中形成N型漏极区132以及在P型体区111中形成P型源极接触区136和N型源极区134。另外，在扩散工艺期间，也可以在P型阱区112中形成P型阱接触区138。在另一个实施例中，用于形成N型漏极区132和N型源极区134的N型杂质离子可以通过第一扩散工艺来扩散，并且用于形成P型源极接触区136和P型阱接触区138的P型杂质离子可以通过与第一扩散工艺不同的第二扩散工艺来扩散。
参考图7，层间绝缘层124可以形成在衬底的包括N型漏极区132、N型源极区134、P型源极接触区136和P型阱接触区138的整个表面上。可以将层间绝缘层124图案化以形成暴露N型漏极区132、P型源极接触区136、P型阱接触区138和栅电极118的接触孔。随后，可以用导电层填充接触孔以形成漏极接触126、源极接触127、阱接触128和栅极接触129。虽然图中未示出，但是在形成层间绝缘层124之前，可以在N型漏极区132、P型源极接触区136、P型阱接触区138和栅电极118上形成硅化物层。
图8和图9是示出根据本公开的另一个实施例的制造高压半导体器件的方法的截面图。在图8和图9中，与图1至图7中使用的附图标记相同的附图标记表示相同的元件。因此，以下省略与参考图1至图7阐述的元件相同的元件的详细描述，以避免重复描述。参考图8和图9，根据本实施例，第一阻挡图案416和第二阻挡图案417可以形成在第一区域202(在后续工艺中在其中形成P型体区111)上的绝缘层113上。也就是说，第一阻挡图案416和第二阻挡图案417而不是图3中所示的阻挡图案116，可以形成在第一区域202上的绝缘层113上。因此，在阻挡图案的数量方面，本实施例与图1至图7中所示的先前实施例不同。第一阻挡图案416和第二阻挡图案417可以被形成为在沟道长度方向上(即，在图8和图9中的水平方向上)彼此间隔开。第一阻挡图案416和第二阻挡图案417也可以被形成为与栅电极118间隔开。如图9所示，在注入用于形成P型体区(图6和图7的111)的P型杂质离子时，朝向栅电极118的倾斜内侧表面或者光刻胶图案120的倾斜侧表面行进的P型杂质离子502可以由栅电极118的倾斜内侧表面或光刻胶图案120的倾斜侧表面来散射，以朝向第二区域152行进(参见虚线箭头504)。在本实施例中，第一阻挡图案416和第二阻挡图案417可以位于散射的P型杂质离子朝向第二区域152行进的路径504中，从而防止散射的P型杂质离子被注入到第二区域152中。这样就防止了形成P型杂质浓度增大的区域。
根据上述实施例，在执行用于形成体区的离子注入工艺之前，可以在待通过后续工艺形成的体区上方形成至少一个阻挡图案，从而在执行用于形成体区的离子注入工艺时，防止在体区中的沟道区的掺杂浓度由于阱邻近效应(WPE)而不期望地增大。
以上为了说明的目的公开了本公开的实施例。本领域普通技术人员将理解，在不脱离如所附权利要求中公开的本公开的范围和精神的情况下，可以进行各种修改、添加和替换。

Claims (23)

1.一种制造高压半导体器件的方法，所述方法包括：
在缓冲绝缘层上方形成用于阻挡杂质离子的阻挡图案，所述缓冲绝缘层设置在第二导电类型的半导体区域中的第一区域上方；
在所述缓冲绝缘层上方形成具有开口的离子注入掩模图案，以通过所述离子注入掩模图案的所述开口暴露出所述阻挡图案；以及
使用所述离子注入掩模图案，将用于形成第一导电类型的体区的所述第一导电类型的杂质离子注入到所述第一区域中。
2.根据权利要求1所述的方法，其中，所述离子注入掩模图案包括栅电极和覆盖所述栅电极的光刻胶图案。
3.根据权利要求2所述的方法，其中，由所述开口暴露出的所述栅电极的侧表面和所述光刻胶图案的侧表面具有倾斜轮廓。
4.根据权利要求3所述的方法，还包括：
在所述半导体区域上形成与所述栅电极垂直重叠的场板绝缘图案；以及
在将所述第一导电类型的所述杂质离子注入所述第一区域之后，去除所述阻挡图案。
5.根据权利要求4所述的方法，其中，使用相同的沉积工艺和相同的图案化工艺来形成所述场板绝缘图案和所述阻挡图案。
6.根据权利要求4所述的方法，其中，所述场板绝缘图案和所述阻挡图案由相同的材料层形成。
7.根据权利要求6所述的方法，其中，所述场板绝缘图案和所述阻挡图案由氧化物层形成。
8.根据权利要求4所述的方法，其中，所述场板绝缘图案和所述阻挡图案被形成为具有平面结构。
9.根据权利要求1所述的方法，其中，所述阻挡图案被定位成阻挡杂质离子，所述杂质离子被所述离子注入掩模图案的由所述开口暴露出的侧表面散射而朝向与所述第一区域的边缘相对应的第二区域行进。
10.根据权利要求1所述的方法，其中，所述阻挡图案由氧化物层形成。
11.根据权利要求1所述的方法，其中，所述阻挡图案被形成为具有平面结构。
12.根据权利要求1所述的方法，其中，在形成所述阻挡图案之前：
在所述第一导电类型的衬底上方依次形成所述第二导电类型的掩埋层和所述第一导电类型的外延层；
在所述第一导电类型的所述外延层的上部和下部分别形成所述第二导电类型的所述半导体区域和所述第一导电类型的掩埋层；
形成所述第一导电类型的阱区，所述阱区穿透所述第二导电类型的所述半导体区域和所述第一导电类型的所述掩埋层；以及
在所述第一导电类型的所述阱区与所述第二导电类型的所述半导体区域之间的边界区域处形成器件隔离层。
13.根据权利要求1所述的方法，其中，所述第二导电类型的所述半导体区域用作漂移区。
14.一种制造高压半导体器件的方法，所述方法包括：
在缓冲绝缘层上方形成第一阻挡图案和第二阻挡图案，所述第一阻挡图案和第二阻挡图案被定位成彼此间隔开以阻挡杂质离子，所述缓冲绝缘层设置在第二导电类型的半导体区域中的第一区域上方；
在所述缓冲绝缘层上方形成具有开口的离子注入掩模图案，以通过所述离子注入掩模图案的所述开口暴露出所述第一阻挡图案和第二阻挡图案；
使用所述离子注入掩模图案，将用于形成第一导电类型的体区的所述第一导电类型的杂质离子注入到所述第一区域中；以及
在将所述第一导电类型的所述杂质离子注入所述第一区域之后，去除所述第一阻挡图案和第二阻挡图案。
15.根据权利要求14所述的方法，其中，所述离子注入掩模图案包括栅电极和覆盖所述栅电极的光刻胶图案。
16.根据权利要求15所述的方法，其中，由所述开口暴露出的所述栅电极的侧表面和所述光刻胶图案的侧表面具有倾斜轮廓。
17.根据权利要求16所述的方法，还包括在所述半导体区域上方形成与所述栅电极垂直重叠的场板绝缘图案。
18.根据权利要求17所述的方法，其中，使用相同的沉积工艺和相同的图案化工艺来形成所述场板绝缘图案、所述第一阻挡图案和所述第二阻挡图案。
19.根据权利要求17所述的方法，其中，所述场板绝缘图案、所述第一阻挡图案和所述第二阻挡图案由相同的材料层形成。
20.根据权利要求19所述的方法，其中，所述场板绝缘图案、所述第一阻挡图案和所述第二阻挡图案由氧化物层形成。
21.根据权利要求17所述的方法，其中，所述场板绝缘图案、所述第一阻挡图案和所述第二阻挡图案被形成为具有平面结构。
22.根据权利要求14所述的方法，其中，所述第一阻挡图案和第二阻挡图案被定位成阻挡杂质离子，所述杂质离子被所述离子注入掩模图案的由所述开口暴露出的侧表面散射而朝向与所述第一区域的边缘相对应的第二区域行进。
23.根据权利要求14所述的方法，其中，所述第二导电类型的所述半导体区域用作漂移区。
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