CN108574000B - 半导体装置和半导体装置的制造方法 - Google Patents

半导体装置和半导体装置的制造方法 Download PDF

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CN108574000B
CN108574000B CN201810102265.0A CN201810102265A CN108574000B CN 108574000 B CN108574000 B CN 108574000B CN 201810102265 A CN201810102265 A CN 201810102265A CN 108574000 B CN108574000 B CN 108574000B
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gate
contact hole
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semiconductor device
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CN108574000A (zh
CN108574000B9 (zh
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山口一哉
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Fuji Electric Co Ltd
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Fuji Electric Co Ltd
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Abstract

本发明提供适用于沟槽栅极和沟槽接触孔并且能够实现高耐压/低导通电阻，提高雪崩耐量的半导体装置和半导体装置的制造方法。半导体装置具备：第一导电型的半导体基板(1)；第一导电型的n型漂移层(50)；第二导电型的第一半导体层(7)。另外，半导体装置具有供主电流流通的活性区域(20)，活性区域具有从第一半导体层的表面到达n型漂移层的沟槽(51)、在沟槽的内部隔着栅极绝缘膜(5)设置的栅电极(6)。另外，半导体装置具有包围活性区域的周围的终端区域(30)，终端区域具有与连接于栅电极的栅极金属(17)接触的栅极接触孔(C)。终端区域具有与第一半导体层连接并且延伸到栅极接触孔的底部的第二导电型的第一半导体区域(12)。

Description

半导体装置和半导体装置的制造方法
技术领域
本发明涉及半导体装置和半导体装置的制造方法。
背景技术
通常，在功率MOSFET(Metal Oxide Semiconductor Field Effect Transistor：金属氧化物半导体场效应晶体管)中，导通电阻和耐压之间存在权衡关系。例如，在通常的平面型的n沟道纵向型MOSFET的情况下，高电阻的n－型漂移层的部分作为在MOSFET为导通状态时沿纵向流通漂移电流的区域而发挥作用，在断开状态时进行耗尽化而提高耐压。缩短该高电阻的n－型漂移层的电流路径因为会降低漂移电阻所以获得MOSFET的实质的导通电阻下降的效果，但相反从p型基区和n－型漂移层之间的pn结进行的漏-基间耗尽层的扩散宽度变窄，提早达到硅(Si)的临界电场强度，导致耐压下降。
相反在耐压高的半导体装置中，由于n－型漂移层变厚，所以必然地导通电阻变大，损失增加。这样在导通电阻和耐压之间存在权衡关系。作为针对该问题的解决对策，存在具有超结构造(Super Junction构造：SJ构造)的SJ-MOSFET。漂移层由提高了杂质浓度的n型的区域和p型的区域交替配置而成的并列pn构造(SJ构造)，断开状态时进行耗尽化而负担耐压。
与通常的平面型的n沟道纵向型MOSFET构造上的不同在于，漂移部并非一致且单一的导电型，成为使纵向型层形的n型的漂移区域和纵向型层形的p型的间隔区交替反复接合而并列的并列pn构造(SJ构造)。即使并列pn构造的杂质浓度高，在断开状态下耗尽层也从沿并列pn构造的纵向配向的各pn结向其横向双方扩张，将整个漂移区域耗尽化，因此能够实现高耐压化。
为了利用该SJ-MOSFET实现高耐压/低导通电阻，需要微细化。在实现微细化的基础上，沟槽栅极和沟槽接触孔的使用是有效的(例如，参照专利文献1)。在沟槽栅极在形成于硅的槽中构成栅极的方法中，使沟槽侧壁成为沟道，因此使微细化成为可能。另外，在沟槽接触孔在形成于硅的槽中形成接触区的方法中，通过沟槽侧壁与源极接触，通过沟槽底与p+型层接触，从而能够实现微细化。
图10是表示现有的SJ-MOSFET的构造的截面图。如图10所示，SJ-MO SFET采用在高杂质浓度的n+型漏极层1生长n型漂移层50而成的晶片作为材料。SJ-MOSFET具备活性部20和包围活性部20的周围的终端构造部(边缘部)30。这里，终端构造部30是设有后述的栅极配线15的区域，活性部20是终端构造部30的内侧的区域。在活性部20中，设有从该晶片表面贯穿n型漂移层50而不到达n+型漏极层1的p型柱区3。n型漂移层50中未设有p型柱区3的区域成为n型柱区2。在图10中，p型柱区3不到达n+型漏极层1，但也可以到达n+型漏极层1。
在n型柱区2和p型柱区3的表面设有p型基层7。在p型基层7的表面侧设有沟槽栅极A和沟槽接触孔B。沿沟槽栅极A的侧壁设有栅极绝缘膜5，在栅极绝缘膜5的内侧设有栅电极6。沟槽栅极A的底部与n型柱区2接触。另外，在p型基层7的内部设有n型源区8和p+型接触区10。p+型接触区10设置在沟槽接触孔B的底部。设有在沟槽接触孔B的侧壁与n型源区8接触且在沟槽接触孔B的底部与p+型接触区10接触的源电极11，源电极11和栅电极6通过层间绝缘膜9绝缘。另外，在n+型漏极层1的背面设有漏电极4。
另外，在保持耐压的终端构造部30设有p型降低表面电场(RESURF)区域12(例如，参照专利文献1)。能够利用p型降低表面电场区12，缓解施加在最外周的n型柱区2和p型柱区3上的p型阱区13端部的电场集中，提高终端构造部30的耐压。另外，埋入沟槽栅极A的栅电极6的多晶硅(Poly-Si)从沟槽栅极A终端引出并与栅极配线15连接，通过终端构造部30与栅极金属17在栅极接触孔C接触。栅极金属17、栅极配线15、n型漂移层50通过LOCOS(Local oxidation of silicon：硅的局部氧化)氧化膜16绝缘。
例如，在具有交替周期地形成有第一导电型的第一半导体层和第二导电型的第二半导体层的柱构造的漂移层的半导体装置的终端区域2中，具有以与p+型保护环层21接触，且向相对于元件区域1的相反侧扩展的方式，在表面形成p型降低表面电场层22的构造(例如，参照专利文献2)。
现有技术文献
专利文献
专利文献1：日本特开2007-149736号公报
专利文献2：日本特开2009-44668号公报
发明内容
技术问题
这里，图11、12是表示现有的SJ-MOSFET的制造中途的状态的截面图。如图11所示，使等离子体19照射到在与栅极接触孔C和沟槽接触孔B对应的部分具有开口部的抗蚀剂18。由此，在现有的SJ-MOSFET中，同时形成终端构造部30的栅极接触孔C和活性部20的沟槽接触孔B。
此时，发生以下的问题。在活性部20的硅(p型基层7)被进行蚀刻时，在终端构造部30对栅极配线15的多晶硅进行蚀刻。其中，与硅相比，由于多晶硅的蚀刻速度快，所以在活性部20的沟槽接触孔B形成前，终端构造部30的多晶硅被完全蚀刻，基底的LOCOS氧化膜16受到等离子体19照射。由此，终端构造部30的LOCOS氧化膜16受到等离子体19照射，直到活性部20的沟槽接触孔B到达期望的深度为止。因此，如图12所示，利用等离子体19也削减LOCOS氧化膜16，因此栅极接触孔C的下方的LOCOS氧化膜16变薄。例如，如果通过SEM(Scanning Electron Microscope：扫描型电子显微镜)观察LOCOS氧化膜16，则栅极接触孔C的下方凹进去而变薄。另外，因等离子体19的损伤，LOCOS氧化膜16的膜质(绝缘性)下降。
这样，在活性部20形成沟槽接触孔B时，栅极接触孔C的下方的LOCOS氧化膜16变薄，并且，膜质(绝缘性)下降。在此情况下，如图10所示，在p型降低表面电场区12的端部引起雪崩压降时，雪崩压降产生的电流向栅极接触孔C的下方的低膜质的LOCOS氧化膜16流入，产生元件被破坏的问题。
为了消除上述的现有技术的问题点，本发明的目的在于提供使用沟槽栅极和沟槽接触孔，能够实现高耐压/低导通电阻，并且提高雪崩耐量的半导体装置和半导体装置的制造方法。
技术方案
为了解决上述课题，实现上述目的，本发明的半导体装置具有如下特征。在第一导电型的半导体基板的第一主面上设有第一导电型的漂移层。在上述漂移层的表面层设有第二导电型的第一半导体层。设有供主电流流通的活性区域，该活性区域具有从上述第一半导体层的表面到达上述漂移层的沟槽和在上述沟槽的内部隔着栅极绝缘膜设置的栅电极。设有终端区域，所述终端区域具有与连接于上述栅电极的栅极金属接触的栅极接触孔并且包围上述活性区域的周围。上述终端区域具有第二导电型的第一半导体区域，所述第二导电型的第一半导体区域与上述第一半导体层连接，并且延伸到上述栅极接触孔的底部。
另外，本发明的半导体装置在上述发明的基础上，其特征在于，在上述终端区域，在上述第一半导体区域和上述栅极金属之间设有绝缘膜，上述栅极接触孔的上述底部的下部的上述绝缘膜的膜厚比未设有上述栅极接触孔的区域的上述绝缘膜的膜厚薄。
另外，本发明的半导体装置在上述发明的基础上，其特征在于，上述栅极接触孔的上述底部的下部的上述绝缘膜的膜厚比未设有上述栅极接触孔的区域的上述绝缘膜的膜厚薄3％～15％。
另外，本发明的半导体装置在上述发明的基础上，其特征在于，上述栅极接触孔的上述底部的下部的上述第一半导体区域的膜厚为1.4μm以上2.0μm以下。
另外，本发明的半导体装置在上述发明的基础上，其特征在于，设有上述栅极接触孔的区域的上述第一半导体区域的杂质浓度在5×1016/cm3以上1×1017/cm3以下。
另外，本发明的半导体装置在上述发明的基础上，其特征在于，上述栅极接触孔的上述终端构造部侧的侧表面和上述第一半导体区域的上述终端构造部侧的端部之间的距离为3.5μm以上。
另外，本发明的半导体装置在上述发明的基础上，其特征在于，在上述漂移层，第一导电型的第一柱体和第二导电型的第二柱体在上述第一主面上沿与所述第一主面平行的方向反复交替地配置。
为了解决上述课题，实现本发明的目的，本发明的半导体装置的制造方法具有如下特征。上述半导体装置具备：第一导电型的半导体基板；配置在上述半导体基板的第一主面上的第一导电型的漂移层；设置在上述漂移层的表面的供主电流流通的活性区域；以及，包围上述活性区域的周围的终端区域。首先，进行在上述终端区域的上述漂移层的表面层形成第二导电型的第一半导体区域的离子注入的第一工序。接着，在上述第一工序后，进行在上述终端区域的第一半导体区域和上述终端区域的上述漂移层的表面形成LOCOS氧化膜的第二工序。接着，进行从上述活性区域的上述漂移层的表面沿与上述第一主面垂直的方向形成沟槽的第三工序。接着，在上述第三工序后，进行在上述漂移层的整个上表面形成栅极绝缘膜的第四工序。接着，在上述第四工序后，进行在栅极绝缘膜的整个上表面堆积多晶硅的第五工序。接着，在上述第五工序后，进行形成上述沟槽内的栅电极和上述终端区域的栅极配线的第六工序。接着，在上述第六工序后，进行在上述活性区域的上述漂移层的表面层形成第二导电型的阱区的第七工序。接着，进行在上述第一半导体层的表面层形成第一导电型的源区的第八工序。接着，在上述第八工序后，进行在上述漂移层的整个上表面形成层间绝缘膜的第九工序。接着，除去上述层间绝缘膜的一部而形成使连接于上述栅电极的上述栅极配线与栅极金属接触的栅极接触孔的第十工序。在上述第一工序中，将上述第一半导体区域延伸到设有上述栅极接触孔的区域。
另外，本发明的半导体装置的制造方法在上述发明的基础上，其特征在于，在上述第十工序中，将设置在上述活性区域的沟槽接触孔与上述栅极接触孔同时形成。
根据上述发明，p型降低表面电场区(第二导电型的第二半导体区域)延伸设置到设有栅极接触孔的区域，覆盖栅极接触孔的下方。由此，能够将因雪崩压降产生的电流从p型降低表面电场区经由p型阱区直接排出到源电极。因此，在具有沟槽栅极和沟槽接触孔的半导体装置中，能够得到高的雪崩耐量。
发明效果
根据本发明的半导体装置和半导体装置的制造方法，能够起到使用沟槽栅极和沟槽接触孔，实现高耐压/低导通电阻并且提高雪崩耐量的效果。
附图说明
图1是表示实施方式的SJ-MOSFET的构造的截面图。
图2是表示实施方式的SJ-MOSFET的制造中途的状态的截面图(其一)。
图3是表示实施方式的SJ-MOSFET的制造中途的状态的截面图(其二)。
图4是表示实施方式的SJ-MOSFET的制造中途的状态的截面图(其三)。
图5是表示实施方式的SJ-MOSFET的制造中途的状态的截面图(其四)。
图6是表示实施方式的SJ-MOSFET的制造中途的状态的截面图(其五)。
图7是表示实施方式的SJ-MOSFET的制造中途的状态的截面图(其六)。
图8是表示实施方式的MOSFET的构造的截面图。
图9是表示实施方式的IGBT的构造的截面图。
图10是表示现有的SJ-MOSFET的构造的截面图。
图11是表示现有的SJ-MOSFET的制造中途的状态的截面图(其一)。
图12是表示现有的SJ-MOSFET的制造中途的状态的截面图(其二)。
标记说明
1：n+型漏极层
2：n型柱区
3：p型柱区
4：漏电极
5：栅极绝缘膜
6：栅电极
7：p型基层
8：n型源区
9：层间绝缘膜
10：p+型接触区
11：源电极
12：p型降低表面电场区
13：p型阱区
14：绝缘膜
15：栅极配线
16：LOCOS氧化膜
17：栅极金属
18：抗蚀剂
19：等离子体
20：活性部
21：n+型半导体基板
22：n－型漂移层
23：p型集电层
24：n型发射区
25：发射极
26：集电极
30：终端构造部
40：箭头
50：n型漂移层
51、52、53：沟槽
A：沟槽栅极
B：沟槽接触孔
C：栅极接触孔
具体实施方式
以下，参照附图对本发明的半导体装置及半导体装置的制造方法的优选实施方式进行详细说明。在本说明书及附图中，在标注有n或p的层和区域中，分别意味着电子或空穴为多数载流子。另外，标记于n或p的+及－分别意味着杂质浓度比未标记+及－的层或区域的杂质浓度高及低。含有+和－的n或p的标记相同的情况表示接近的浓度，浓度未必相同。应予说明，在以下的实施方式的说明和附图中，对同样的构成标注相同的符号并省略重复说明。
(实施方式)
以SJ-MOSFET为例说明本发明的半导体装置。图1是表示实施方式的SJ-MOSFET的构造的截面图。图1中，仅表示了2个单位单元(元件的功能单位)，省略与它们邻接的其它单位单元的图示。图1所示的SJ-MOSFET为在由硅构成的半导体基体(硅基体：半导体芯片)的表面(p型基层7侧的面)一侧具备MOS(Metal Oxide Semiconductor：金属氧化物半导体)栅极的SJ-MOSFET。该SJ-MOSFET具备活性部20和包围活性部20的周围的终端构造部30。活性部20为导通状态时流通电流的区域。终端构造部30是缓解漂移区域的基体表面侧的电场并保持耐压的区域。
硅基体在成为n+型漏极层(第一导电型的半导体基板)1的n+型半导体基板的表面上使n型漂移层50生长，在n型漂移层50内交替设置具有超结构造(SJ构造)的n型柱区2和p型柱区3。MOS栅极由p型基层(第二导电型的第一半导体层)7、n型源区8、p+型接触区10、沟槽栅极A、沟槽接触孔B、栅极绝缘膜5和栅电极6构成。另外，在n+型漏极层1的背面设有漏电极4。
在活性部20设有SJ构造。SJ构造是由n型柱区2和p型柱区3交替反复地接合而成的。p型柱区3以从n型漂移层50的表面没有到达n+型漏极层1的表面的方式设置。n型柱区2和p型柱区3的平面形状为例如条纹形、六面格子形或者正方形。应予说明，p型柱区3也可以到达n+型漏极层1的表面。
另外，在活性部20设有到达n型柱区2的沟槽51，隔着栅极绝缘膜5使由多晶硅构成的栅电极6埋入沟槽51。由此，设置沟槽栅极A。另外，在p型柱区3的上方(源电极11侧)设有p型基层7，在p型基层7的表面设有n型源区8。在栅电极6上设有用于与源电极11绝缘的层间绝缘膜9。贯穿层间绝缘膜9，在p型基层7的表面设有沟槽52，在沟槽52的底部，p+型接触区10与源电极11连接，在沟槽52的侧壁，n型源区8和源电极11连接。由此，设置沟槽接触孔B。
另外，在外周的终端构造部30设有与p型柱区3连接的p型阱区13，在其外侧设有与p型阱区13连接的p型降低表面电场区(第二导电型的第一半导体区域)12。p型降低表面电场区12的杂质浓度比p型柱区3的杂质浓度高。在p型降低表面电场区12和p型阱区13上设有绝缘膜14，隔着绝缘膜14设有栅极配线15。该栅极配线15与埋入设置在活性部20的沟槽51的栅电极6连接。在栅极配线15上设置有层间绝缘膜9。
另外，在绝缘膜14的外侧设有LOCOS氧化膜16，栅极配线15延伸设置到LOCOS氧化膜16的上方为止。在外周的终端构造部30设有贯通层间绝缘膜9和栅极配线15的沟槽53，在沟槽53的内部埋入有栅极金属17。由此，设有使栅极配线15与栅极金属17连接的栅极接触孔C。栅极配线15隔着栅极金属17与栅极焊盘(未图示)连接。栅极金属优选为铝或者含有铝的金属。
另外，LOCOS氧化膜16如后所述利用等离子体蚀刻使沟槽53的底部的部分(由图1的X所示的部分)变薄。也就是说，栅极接触孔C的底部(沟槽53的底部)的下方的部分比未设有栅极接触孔C的部分膜厚薄。例如，栅极接触孔C的底部(沟槽53的底部)的下方的部分的膜厚比未设有栅极接触孔C的部分的膜厚(LOCOS氧化膜16的膜厚)薄3％～15％。另外，例如，LOCOS氧化膜16的膜厚为0.35μm，栅极接触孔C的底部(沟槽53的底部)的下方的部分的膜厚为0.3μm以上且0.34μm以下。
进而，LOCOS氧化膜16因等离子体蚀刻而受到损伤，因此膜质(绝缘性)下降而电阻变低。这是由于因等离子体蚀刻使电子、离子等进入LOCOS氧化膜16，在不同于本来的能级的地方产生能级，经由此使电流流通。
另外，p型降低表面电场区12与p型阱区13连接，一直延伸设置到设有栅极接触孔C的区域，并覆盖栅极接触孔C的底部。p型降低表面电场区12的终端构造部30侧的端部和栅极接触孔C的终端构造部30侧的侧表面(沟槽53的终端构造部30侧的侧表面)之间的距离Y(由图1的Y表示部分)可以距离至少3.5μm以上。这里，p型降低表面电场区12可以是越靠近p型降低表面电场区12的表面杂质浓度就越高。这是由于越靠近表面电阻越低，因雪崩压降产生的电流容易流动。另外，p型降低表面电场区12的杂质浓度、膜厚根据SJ-MOSFET的耐压而变化。例如，只要SJ-MOSFET的耐压为100V～150V，则优先为杂质浓度为5×1016/cm3以上1×1017/cm3以下，膜厚为1.4μm以上且2.0μm以下。应予说明，沟槽接触孔B和栅极接触孔C的平面形状可以是条纹形、也可以是点形。
这样，由于使p型降低表面电场区12覆盖栅极接触孔C的底部，因此雪崩耐量的产生的点从栅极接触孔C的底部离开到外侧的位置(由图1的Z表示的部分)。进而，虽然因损伤使LOCOS氧化膜16的电阻变低，但由于p型区域电阻更低，所以因雪崩压降产生的电流从作为p型区域的p型降低表面电场区12经由p型阱区13直接排出到源电极11(参照图1的箭头40)。这样，因雪崩压降产生的电流不会流入到栅极接触孔C的下方的膜厚变薄的LOCOS氧化膜16，因此能够防止破坏元件。因此，本实施方式的SJ-MOSFET能够获得高的雪崩耐量。
(实施方式的半导体装置的制造方法)
接着，说明实施方式的半导体装置的制造方法。图2～图7是表示实施方式的SJ-MOSFET的制造中途的状态的截面图。首先，准备由硅构成且成为n+型漏极层1的n+型半导体基板。接着，在n+型漏极层1的表面上反复进行外延生长和离子注入，形成由n型柱区2和p型柱区3构成的SJ构造。至此的状态记载于图2。应予说明，未设有n型柱区2和p型柱区3的区域成为n型漂移层50。另外，SJ构造可以在n+型漏极层1的表面上以外延生长形成n型漂移层50，将在从n型漂移层50的上表面形成p型柱区3的位置形成沟槽从而形成p型柱区3的半导体层埋入到沟槽的内部。
接着，利用光刻和蚀刻形成掩模而进行p型杂质的离子注入，在n型漂移层50的终端构造部30侧的表面层形成p型降低表面电场区12。p型降低表面电场区12从活性部20的最外周的p型柱区3形成到栅极接触孔C所形成的区域，以未达到p型柱区3的深度而形成。至此的状态记载于图3。
接着，在潮湿O2(氧气)氧化、氢气氧化等包含水蒸气的环境中，进行高温长时间的热处理，进行热氧化而在终端构造部30形成LOCOS氧化膜16。利用此时的热处理，p型降低表面电场区12变宽，与p型柱区3连接。LOCOS氧化膜16设置在终端构造部30的p型降低表面电场区12和n型漂移层50的表面。至此的状态记载于图4。
接着，在活性部20形成沟槽栅极A。形成从n型漂移层50的表面上到达n型柱区2的沟槽51。沟槽形成时的掩模使用氧化膜。接着，沿n型漂移层50的表面和沟槽51的内壁形成栅极绝缘膜5。接着，以埋入沟槽51的方式堆积例如多晶硅，通过对活性部20的部分进行蚀刻，在沟槽51的内部残留成为栅电极6的多晶硅而设置沟槽栅极A，在终端构造部30残留成为栅极配线15的多晶硅。此时，埋入到沟槽51的多晶硅可以进行蚀刻而以相对于n型漂移层的表面在内侧残留的方式进行蚀刻，通过实施图案形成和蚀刻而与n型漂移层的表面相比向外侧突出。至此的状态如图5所示。
接着，在n型漂移层50的表面上通过光刻法技术由例如氧化膜形成具有期望的开口部的未图示的离子注入用掩模。将该离子注入用掩模作为掩模，进行p型杂质的离子注入，在n型漂移层50的表面层形成p型基层7。接着，除去离子注入用掩模。
接着，在p型基层7的表面上通过光刻法技术由例如氧化膜形成具有期望的开口部的未图示的离子注入用掩模。将该离子注入用掩模作为掩模，进行n型杂质的离子注入，在p型基层7的表面层形成n型源区8。接着，除去离子注入用掩模。至此的状态如图6所示。
接着，在n型漂移层50的表面上的整个面形成层间绝缘膜9。层间绝缘膜9由例如BPSG(Boro Phospho Silicate glass：硼磷硅玻璃)形成。接着，为了进行层间绝缘膜9的平担化而进行回流焊处理。层间绝缘膜9可以由NSG(None-doped Silicate Glass：无掺杂硅酸盐玻璃)、PSG(Phospho Silicate Glass：磷酸盐玻璃)、HTO(High Temperature Oxide：高温氧化)或者以上的组合形成。
接着，同时形成到达活性部20中的p型基层7的沟槽接触孔B和到达终端构造部30中的LOCOS氧化膜16的栅极接触孔C。通过同时形成沟槽接触孔B的沟槽52和形成栅极接触孔C的沟槽53，可以减少工序。在沟槽形成时的掩模使用氧化膜。例如，通过对在与栅极接触孔C和沟槽接触孔B对应的部分具有开口部的掩模(未图示)照射等离子体，由此同时在形成栅极接触孔C的位置形成沟槽52和在形成沟槽接触孔B的位置形成沟槽53。此时，沟槽53的底部(栅极接触孔C的底部的下方)的LOCOS氧化膜16因等离子体蚀刻而受到损伤，因此膜质(绝缘性)下降而变薄。应予说明，蚀刻只要是各向异性即可，也可以通过等离子体蚀刻以外的干蚀刻进行。
接着，在沟槽52的底部进行p型杂质的离子注入，在p型基层7的内部形成杂质浓度比p型基层7高的p+型接触区10。接着，对进行了离子注入的区域实施活性化退火。例如，活性化退火在950℃下进行。由此，使对n型源区8、p+型接触区10、p型降低表面电场区12和p型阱区13进行离子注入的杂质活性化。至此的状态如图7所示。
接着，以覆盖层间绝缘膜9的方式，形成由钛(Ti)或者氮化钛(TiN)构成的势垒金属(未图示)并进行图案形成，露出n型源区8、p+型接触区10和栅极配线15。接着，以与n型源区8和p+型接触区10接触的方式形成源电极11。源电极11也可以以覆盖势垒金属的方式形成，也可以只残留在沟槽52内。应予说明，为了防止源电极11的铝铜合金的覆盖率变差，可以使用钨(W)插塞。接着，以与栅极配线15接触的方式形成栅极金属17。应予说明，在沟槽53内也可以使用势垒金属、钨(W)插塞。
接着，以埋入沟槽52的方式形成源极焊盘(未图示)。可以将为了形成源极焊盘而堆积的金属层的一部分作为栅极焊盘。在n+型漏极层1的背面，可以使用溅射蒸镀等在漏电极4的接触部形成镍(Ni)膜、钛(Ti)膜等金属膜。该金属膜可以将多个Ni膜、Ti膜进行组合而层积。之后，以使金属膜硅化而形成欧姆接触的方式进行高速热处理(RTA：RapidThermal Annealing)等退火。之后，通过电子束(EB：Electron beam)蒸镀等形成按顺序层积例如Ti膜、Ni膜、金(Au)而成的层积膜等厚的膜，并且形成漏电极4。
在上述外延生长和离子注入中，作为n型杂质(n型掺杂剂)，可以使用例如相对于碳化硅成为n型的氮(N)或磷(P)、砷(As)、锑(Sb)等。作为p型杂质(p型掺杂剂)，可以使用例如相对于碳化硅成为p型的硼(B)或铝(Al)、钙(Ga)、铟(In)、铊(Tl)等。这样，完成图1所示的SJ-MOSFET。
另外，在以上说明中，以SJ-MOSFET为例进行了说明，但具有沟槽接触孔和栅极接触孔的MOSFET、IGBT(Insulated Gate Bipolar Transistor：绝缘栅双极型晶体管)也可以应用本发明。图8是表示实施方式的MOSFET的构造的截面图。在图8中，符号21、22分别为n+型半导体基板、n－型漂移层。其它构造与图1的SJ-MOSFET相同因此省略。图9是表示实施方式的IGBT的构造的截面图。在图9中，符号23～26分别为p型集电层、n型发射区、发射极、集电极。其它构造与图1的SJ-MOSFET相同因此省略。
以上，如上所述，根据实施方式，p型降低表面电场区延伸设置到设有栅极接触孔的区域，覆盖栅极接触孔的下方。由此，能够将由雪崩压降产生的电流从p型降低表面电场区经由p型阱区直接排出到源电极。因此，在具有沟槽栅极和沟槽接触孔的半导体装置中，能够得到高的雪崩耐量。
以上在本发明中，以在硅基板的第一主面上构成MOS栅极构造的例子进行说明，但不限于此，能够对半导体的种类(例如碳化硅(SiC)等)、基板主面的面方位等进行各种变更。另外，在本发明中，在各实施方式中第一导电型采用p型，第二导电型采用n型，但本发明的第一导电型采用n型，第二导电型采用p型也是同样成立的。
工业上的可利用性
如上所述，本发明的半导体装置和半导体装置的制造方法可以用于在电力转换装置、各种工业用机械等电源装置等中使用的高耐压半导体装置，特别适于具有沟槽构造的高耐压半导体装置。

Claims (9)

1.一种半导体装置，其特征在于，具备：
第一导电型的半导体基板；
设置在所述半导体基板的第一主面上的第一导电型的漂移层；
设置在所述漂移层的表面层的第二导电型的第一半导体层，
活性区域，其供主电流流通，具有从所述第一半导体层的表面到达所述漂移层的沟槽以及在所述沟槽的内部隔着栅极绝缘膜设置的栅电极；
终端区域，其具有与连接于所述栅电极的栅极金属接触的栅极接触孔，包围所述活性区域的周围；
第二导电型的第一半导体区域，其在所述终端区域，与所述第一半导体层连接并且延伸到所述栅极接触孔的底部；
绝缘膜，其在所述终端区域，设置于所述第一半导体区域上；
栅极配线，其与设置于所述活性区域的所述栅电极连接，并且设置在所述绝缘膜上；以及
层间绝缘膜，其设置于所述栅极配线上，
所述栅极接触孔贯通所述层间绝缘膜和所述栅极配线直到所述绝缘膜。
2.根据权利要求1记载的半导体装置，其特征在于，所述栅极接触孔的所述底部的下部的所述绝缘膜的膜厚比未设有所述栅极接触孔的区域的所述绝缘膜的膜厚薄。
3.根据权利要求2记载的半导体装置，其特征在于，所述栅极接触孔的所述底部的下部的所述绝缘膜的膜厚比未设有所述栅极接触孔的区域的所述绝缘膜的膜厚薄3％～15％。
4.根据权利要求1～3中任意一项记载的半导体装置，其特征在于，所述栅极接触孔的所述底部的下部的所述第一半导体区域的膜厚为1.4μm以上2.0μm以下。
5.根据权利要求1～4中任意一项记载的半导体装置，其特征在于，设有所述栅极接触孔的区域的所述第一半导体区域的杂质浓度为5×1016/cm3以上且1×1017/cm3以下。
6.根据权利要求1～5中任意一项记载的半导体装置，其特征在于，所述栅极接触孔的所述终端构造部侧的侧表面和所述第一半导体区域的所述终端构造部侧的端部之间的距离为3.5μm以上。
7.根据权利要求1记载的半导体装置，其特征在于，在所述漂移层，第一导电型的第一柱体和第二导电型的第二柱体在所述第一主面上沿与所述第一主面平行的方向反复交替地配置。
8.一种半导体装置的制造方法，其特征在于，所述半导体装置具备：第一导电型的半导体基板；在所述半导体基板的第一主面上配置的第一导电型的漂移层；设置在所述漂移层的表面的供主电流流通的活性区域；包围所述活性区域的周围的终端区域，
所述半导体装置的制造方法具有：
第一工序，进行在所述终端区域的所述漂移层的表面层形成第二导电型的第一半导体区域的离子注入；
第二工序，在所述第一工序后，在所述终端区域的第一半导体区域和所述终端区域的所述漂移层的表面形成LOCOS氧化膜；
第三工序，从所述活性区域的所述漂移层的表面沿与所述第一主面垂直的方向形成沟槽；
第四工序，在所述第三工序后，在所述漂移层的整个上表面形成栅极绝缘膜；
第五工序，在所述第四工序后，在栅极绝缘膜的整个上表面堆积多晶硅；
第六工序，在所述第五工序后，形成所述沟槽内的栅电极和所述终端区域的栅极配线；
第七工序，在所述第六工序后，在所述活性区域的所述漂移层的表面层形成第二导电型的阱区；
第八工序，在所述第一半导体层的表面层形成第一导电型的源区；
第九工序，在所述第八工序后，在所述漂移层的整个上表面形成层间绝缘膜；以及
第十工序，除去所述层间绝缘膜的一部分而形成使连接于所述栅电极的所述栅极配线与栅极金属接触的栅极接触孔，
在所述第一工序中，将所述第一半导体区域延伸到设有所述栅极接触孔的区域。
9.根据权利要求8记载的半导体装置的制造方法，其特征在于，在所述第十工序中，将设置在所述活性区域的沟槽接触孔与所述栅极接触孔同时形成。
CN201810102265.0A 2017-03-14 2018-02-01 半导体装置和半导体装置的制造方法 Active CN108574000B9 (zh)

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DE102019122453A1 (de) * 2019-08-21 2021-02-25 Infineon Technologies Austria Ag Graben-Elektrodenstrukturen enthaltende Halbleitervorrichtung
US11961903B2 (en) * 2020-05-26 2024-04-16 Hyundai Mobis Co., Ltd. Power semiconductor device and method of fabricating the same
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009021519A (ja) * 2007-07-13 2009-01-29 Denso Corp 半導体装置
JP2009200098A (ja) * 2008-02-19 2009-09-03 Toyota Motor Corp Ｉｇｂｔとその製造方法
JP2013201451A (ja) * 2013-06-03 2013-10-03 Renesas Electronics Corp 半導体装置

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69525003T2 (de) * 1994-08-15 2003-10-09 Siliconix Inc Verfahren zum Herstellen eines DMOS-Transistors mit Grabenstruktur unter Verwendung von sieben Masken
US5597765A (en) * 1995-01-10 1997-01-28 Siliconix Incorporated Method for making termination structure for power MOSFET
JP3525637B2 (ja) * 1996-08-09 2004-05-10 株式会社デンソー 半導体装置
JP4059566B2 (ja) 1998-06-24 2008-03-12 Ｎｅｃエレクトロニクス株式会社 絶縁ゲート型半導体装置及びその製造方法
JP2006073710A (ja) 2004-09-01 2006-03-16 Sanken Electric Co Ltd 半導体装置及び半導体装置の製造方法
JP5002148B2 (ja) 2005-11-24 2012-08-15 株式会社東芝 半導体装置
JP4927650B2 (ja) 2007-06-25 2012-05-09 古河電気工業株式会社 面上発熱源の放熱構造体
JP2009004668A (ja) 2007-06-25 2009-01-08 Toshiba Corp 半導体装置
US7652329B2 (en) * 2007-07-13 2010-01-26 Semiconductor Components Industries, Llc Vertical MOS transistor and method therefor
JP2009289791A (ja) 2008-05-27 2009-12-10 Nec Electronics Corp 半導体装置
JP5371453B2 (ja) * 2009-01-09 2013-12-18 ミツミ電機株式会社 電界効果トランジスタおよびその製造方法
JP2011210916A (ja) * 2010-03-30 2011-10-20 Mitsumi Electric Co Ltd 半導体装置の製造方法
JP5586546B2 (ja) * 2011-03-23 2014-09-10 株式会社東芝 半導体装置
JP5510404B2 (ja) 2011-07-11 2014-06-04 トヨタ自動車株式会社 半導体装置、及び、半導体装置の製造方法
EP2725623B1 (en) * 2011-09-08 2019-10-30 Fuji Electric Co., Ltd. Semiconductor device
JP2017045839A (ja) * 2015-08-26 2017-03-02 ルネサスエレクトロニクス株式会社 半導体装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009021519A (ja) * 2007-07-13 2009-01-29 Denso Corp 半導体装置
JP2009200098A (ja) * 2008-02-19 2009-09-03 Toyota Motor Corp Ｉｇｂｔとその製造方法
JP2013201451A (ja) * 2013-06-03 2013-10-03 Renesas Electronics Corp 半導体装置

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