JP5510404B2 - 半導体装置、及び、半導体装置の製造方法 - Google Patents
半導体装置、及び、半導体装置の製造方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims description 278
- 238000004519 manufacturing process Methods 0.000 title claims description 19
- 238000000034 method Methods 0.000 title claims description 10
- 230000002093 peripheral effect Effects 0.000 claims description 115
- 239000012535 impurity Substances 0.000 claims description 105
- 239000000758 substrate Substances 0.000 claims description 54
- 239000010410 layer Substances 0.000 description 68
- 210000000746 body region Anatomy 0.000 description 52
- 230000005684 electric field Effects 0.000 description 41
- 238000009826 distribution Methods 0.000 description 15
- 230000015556 catabolic process Effects 0.000 description 7
- 238000005468 ion implantation Methods 0.000 description 6
- 239000013078 crystal Substances 0.000 description 5
- 230000007423 decrease Effects 0.000 description 5
- 230000007547 defect Effects 0.000 description 5
- 230000004888 barrier function Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 2
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Description
以下に、この半導体装置をオンさせる方法を説明する。コレクタ領域とエミッタ領域の間に、コレクタ領域がプラスとなる電圧が印加されている状態で、ゲート電極に閾値(チャネルを形成するのに必要な最小限の電位)以上の電位を印加する。すると、ゲート電極への電位の印加によって、絶縁膜と接する範囲の第1半導体領域がn型に反転し、その範囲にチャネルが形成される。すると、エミッタ領域、第1半導体領域のチャネル、第6半導体領域、ドリフト領域、コレクタ領域を順に通過して電子が流れる。また、コレクタ領域から、ドリフト領域内にホールが流入する。ドリフト領域に流入したホールは、第6半導体領域、第1半導体領域、を順に通過して流れる。ドリフト領域内にホールが流入すると、ドリフト領域内で伝導度変調現象が起こり、ドリフト領域の電気抵抗が低下する。したがって、電子はドリフト領域内を低損失で流れることができる。これによって、コレクタ領域からエミッタ領域に向けて電流が流れる。すなわち、本明細書が開示する半導体装置がオンする。
本明細書が開示する半導体装置では、第6半導体領域と第1半導体領域の間のpn接合がホールの流れの障壁となるので、ホールが第6半導体領域から第1半導体領域に流れ難い。このため、多くのホールがドリフト領域内に蓄積され、ドリフト領域の電気抵抗がより低くなる。したがって、この半導体装置はオン抵抗を低減することができる。
本明細書が開示する一の形態の半導体装置は、半導体基板を有している。半導体基板は、縦型の半導体素子が形成されている素子領域と、その素子領域の周囲に配置されている周辺領域を有している。素子領域内には、第1導電型を有しており、半導体基板の上面に露出している第1半導体領域が形成されている。周辺領域内には、第2半導体領域、第3半導体領域、及び、第4半導体領域が形成されている。第2半導体領域は、第1導電型を有しており、第1半導体領域よりも第1導電型不純物濃度が低く、半導体基板の上面に露出しており、直接または第1導電型を有する他の半導体領域を介して第1半導体領域と繋がっている。第3半導体領域は、第2導電型を有しており、第2半導体領域に対して下方から接している。第4半導体領域は、第2導電型を有しており、第3半導体領域よりも第2導電型不純物濃度が低く、第3半導体領域に対して下方から接している。第3半導体領域は、エピタキシャル層である。
本明細書または図面に説明した技術要素は、単独であるいは各種の組み合わせによって技術的有用性を発揮するものであり、出願時請求項記載の組み合わせに限定されるものではない。また、本明細書または図面に例示した技術は複数目的を同時に達成するものであり、そのうちの一つの目的を達成すること自体で技術的有用性を持つものである。
12:半導体基板
14:端面
16:上面
18:下面
40:絶縁層
50:エミッタ電極
60:外周電極
70:コレクタ電極
80:ゲート電極
82:ゲート絶縁膜
84:層間絶縁膜
100:素子領域
102:エミッタ領域
104:ボディコンタクト領域
106:上部ボディ領域
108:ストッパ領域
110:下部ボディ領域
112:ドリフト領域
114:コレクタ領域
120:n型領域
200:周辺領域
202:終端領域
204:リサーフ領域
206:周辺n型領域
208:外周コンタクト領域
210:pn接合
Claims (4)
- 半導体装置であって、
半導体基板を有しており、
半導体基板が、縦型のIGBTが形成されている素子領域と、その素子領域の周囲に配置されている周辺領域を有しており、
素子領域内に、
n型を有しており、半導体基板の上面に露出しているエミッタ領域と、
p型を有しており、半導体基板の上面に一部が露出しており、エミッタ領域に下方から接している第1半導体領域と、
エピタキシャル層であり、n型を有しており、第1半導体領域に下方から接しており、第1半導体領域によってエミッタ領域と分離されている第6半導体領域と、
n型を有しており、第6半導体領域の下方に配置されており、第6半導体領域よりもn型不純物濃度が低いドリフト領域と、
p型を有しており、ドリフト領域に下方から接しているコレクタ領域と、
エミッタ領域と第6半導体領域とを分離している範囲の第1半導体領域に対して絶縁膜を介して接しているゲート電極、
が形成されており、
周辺領域内に、
p型を有しており、第1半導体領域よりもp型不純物濃度が低く、半導体基板の上面に露出しており、直接またはp型を有する他の半導体領域を介して第1半導体領域と繋がっている第2半導体領域と、
エピタキシャル層であり、n型を有しており、第6半導体領域と同一のn型不純物濃度を有しており、第2半導体領域に対して下方から接している第3半導体領域と、
n型を有しており、第3半導体領域よりもn型不純物濃度が低く、第3半導体領域に対して下方から接している第4半導体領域、
が形成されている、
ことを特徴とする半導体装置。
- 周辺領域内に、n型を有しており、第3半導体領域よりもn型不純物濃度が低く、半導体基板の上面に露出しており、第2半導体領域と半導体基板の端面の間に配置されており、第2半導体領域に対して側方から接している第5半導体領域が形成されていることを特徴とする請求項1に記載の半導体装置。
- 第2半導体領域の中におけるp型不純物の最大濃度が、第3半導体領域の中におけるn型不純物の最大濃度よりも高いことを特徴とする請求項1または2に記載の半導体装置。
- 請求項1に記載の半導体装置を製造する方法であって、
n型を有するベース半導体層上に、n型を有し、ベース半導体層よりもn型不純物濃度が高いエピタキシャル層を成長させる工程と、
周辺領域内のエピタキシャル層にp型不純物を注入することによって、p型を有しており、エピタキシャル層の上面に露出しており、下端がベース半導体層に達しない第2半導体領域を周辺領域内に形成する工程と、
素子領域内のエピタキシャル層にp型不純物を注入することによって、p型を有しており、エピタキシャル層の上面に露出しており、下端がベース半導体層に達しない第1半導体領域を素子領域内に形成する工程、
を有しており、
第1半導体領域と第2半導体領域は、第1半導体領域のp型不純物濃度よりも第2半導体領域のp型不純物濃度が低くなるように形成される、
ことを特徴とする半導体装置の製造方法。
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US13/480,074 US9000478B2 (en) | 2011-07-11 | 2012-05-24 | Vertical IGBT adjacent a RESURF region |
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US10186573B2 (en) * | 2015-09-14 | 2019-01-22 | Maxpower Semiconductor, Inc. | Lateral power MOSFET with non-horizontal RESURF structure |
US9768247B1 (en) | 2016-05-06 | 2017-09-19 | Semiconductor Components Industries, Llc | Semiconductor device having improved superjunction trench structure and method of manufacture |
JP7316746B2 (ja) * | 2017-03-14 | 2023-07-28 | 富士電機株式会社 | 半導体装置および半導体装置の製造方法 |
JP6847007B2 (ja) * | 2017-09-13 | 2021-03-24 | 株式会社日立製作所 | 半導体装置およびその製造方法 |
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