JP6847007B2 - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
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- JP6847007B2 JP6847007B2 JP2017175603A JP2017175603A JP6847007B2 JP 6847007 B2 JP6847007 B2 JP 6847007B2 JP 2017175603 A JP2017175603 A JP 2017175603A JP 2017175603 A JP2017175603 A JP 2017175603A JP 6847007 B2 JP6847007 B2 JP 6847007B2
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Description
実施例1の半導体装置100は、トレンチゲート型パワーMOSFETであり、半導体基板SBには、トレンチゲート型パワーMOSFET(なお、単に「トランジスタ」と呼ぶ場合もある)が形成されている。実施例1では、nチャネルのトレンチゲート型パワーMOSFETを例に説明するが、pチャネル型のトレンチゲート型パワーMOSFETとすることも出来る。
図5は、実施例1の半導体装置100(トランジスタ)の等価回路図である。図6は、半導体装置(トランジスタ)100の動作電圧の一例を示す表である。図7は、実施例1の半導体装置(トランジスタ)100のオフ動作時の空乏層を示す模式図である。図8は、実施例1の半導体装置(トランジスタ)100のオン動作時の空乏層を示す模式図である。
<半導体装置の製造方法>
次に、実施例1の半導体装置の製造方法を図9〜図15を用いて説明する。図9〜図15は、実施例1の半導体装置の製造工程中の断面図である。図9〜図15は、図3の断面図に対応している。
2 ドレイン領域(n型半導体領域)
3 ドリフト領域(n型半導体領域)
4 ボディ領域(p型半導体領域)
5 ソース領域(n型半導体領域)
6 ボディ接続領域(p型半導体領域)
7 ゲート絶縁膜
8 ゲート電極
9 ソース電極
10 層間絶縁膜(絶縁膜)
10a 開口
11 溝
12 電界緩和層(p型半導体領域)
13 n型半導体領域
14 p型半導体領域
15 n型半導体領域
21 コレクタ電極
22 コレクタ領域(p形半導体領域)
23 バッファ領域(n型半導体領域)
25 エミッタ領域(n型半導体領域)
29 エミッタ電極
100 半導体装置(半導体チップ)
101 ターミネーション領域
102 アクティブ領域(活性領域)
103 単位アクティブセル
104 ソースパッド
105 ゲートパッド
BK バルク基板
C コレクタ
D ドレイン
DEP 空乏層
E エミッタ
EP エピタキシャル層
ED1、ED2、ED3、ED4 辺
ED1S、ED2S、ED3S、ED4S 側壁(側面)
G ゲート
GR ガードリング(p形半導体領域)
MSK1、MSK2、MSK3、MSK4、MSK5 マスク層
OP1、OP2、OP3、OP4、OP5 開口
S ソース
SB 半導体基板
SBa 主面
SBb 裏面
Claims (12)
- 主面と裏面とを有する半導体基板と、
前記主面に接するように、前記半導体基板内に設けられた第1導電型を有するドリフト領域と、
前記ドリフト領域内に選択的に設けられ、前記第1導電型と異なる第2導電型を有するボディ領域と、
前記ボディ領域を貫通し、平面視にて、第1方向に延在し、前記第1方向と直交する第2方向において、互いに離間して配置された第1溝および第2溝と、
前記ボディ領域内に形成され、前記第1溝と前記第2溝との間に配置された前記第2導電型を有する第1半導体領域と、
前記ボディ領域内に形成され、前記第1溝と前記第1半導体領域との間に配置された前記第1導電型を有する第2半導体領域と、
前記ボディ領域内に形成され、前記第2溝と前記第1半導体領域との間に配置された前記第1導電型を有する第3半導体領域と、
前記ドリフト領域内に形成され、前記第1溝および前記第2溝の下に配置された前記第2導電型を有する第4半導体領域と、
前記第1溝内に、第1ゲート絶縁膜を介して形成された第1ゲート電極と、
前記第2溝内に、第2ゲート絶縁膜を介して形成された第2ゲート電極と、
前記半導体基板の前記主面上に形成され、前記第1半導体領域、前記第2半導体領域および前記第3半導体領域に電気的に接続された第1電極と、
前記半導体基板の前記裏面上に形成された、第2電極と、
前記ボディ領域と前記第4半導体領域との間に位置し、前記第1導電型を有する第5半導体領域と、
前記ドリフト領域内において、前記第4半導体領域の下に配置され、前記第1導電型を有する第6半導体領域と、
を有し、
前記第4半導体領域は、前記第1方向において、前記第1溝の下および前記第2溝の下にそれぞれ連続的に延在しており、
前記第4半導体領域は、前記第2方向において、前記第1溝、前記第2半導体領域、前記第1半導体領域、前記第3半導体領域および前記第2溝の下に連続的に延在しており、
前記第6半導体領域の不純物濃度は、前記ドリフト領域の不純物濃度よりも高い、半導体装置。 - 請求項1に記載の半導体装置において、
平面視において、前記第4半導体領域は、前記ボディ領域の全域に連続的に延在している、半導体装置。 - 請求項1に記載の半導体装置において、
前記半導体基板は、シリコンよりもバンドギャップの広い半導体材料からなる、半導体装置。 - 請求項1に記載の半導体装置において、
前記第4半導体領域の不純物濃度は、前記ボディ領域の不純物濃度よりも低い、半導体装置。 - 請求項1に記載の半導体装置において、
前記半導体装置は、前記第1電極と前記第2電極との間に形成されたトランジスタを有し、前記トランジスタのオン動作時において、前記第4半導体領域は、その厚さ方向で完全に空乏化している、半導体装置。 - 請求項1に記載の半導体装置において、
前記第4半導体領域は、前記ボディ領域の下に位置し、前記ボディ領域に接している、半導体装置。 - 請求項1に記載の半導体装置において、
さらに、
前記第2方向において、前記第5半導体領域を分断するように配置され、前記ボディ領域と前記第4半導体領域とを連結し、前記第2導電型を有する第7半導体領域を有する、半導体装置。 - (a)主面と裏面とを有し、平面視にて、前記主面には活性領域と、前記活性領域を取り囲むターミネーション領域とを有し、断面視にて、前記主面に接するように第1導電型のドリフト領域を有する半導体基板を準備する工程、
(b)前記活性領域に対応する第1開口を有し、前記主面上に形成された第1マスク層を用い、前記第1マスク層から露出した前記半導体基板に、前記第1導電型とは異なる第2導電型のボディ領域と、前記ボディ領域の下部に位置する前記第2導電型の第1半導体領域とを形成する工程、
(c)前記主面上に形成され、複数の第2開口を有する第2マスク層を用いて、前記ボディ領域内に前記第2導電型の複数の第2半導体領域を形成する工程、
(d)前記ボディ領域内であって、前記複数の第2半導体領域間に、前記第1導電型の第3半導体領域を形成する工程、
(e)前記主面から前記裏面に向かって延び、前記第3半導体領域および前記ボディ領域を貫通し、前記第1半導体領域は貫通しない溝を形成する工程、
(f)前記溝内にゲート絶縁膜を介してゲート電極を形成する工程、
を有し、
前記(b)工程は、さらに、
(b1)前記第1マスク層を用いて、前記ボディ領域と前記第1半導体領域との間に、前記第1導電型の第5半導体領域を形成する工程、
を有する、半導体装置の製造方法。 - 請求項8に記載の半導体装置の製造方法において、
前記(e)工程において、前記溝は、前記第1半導体領域に達する、半導体装置の製造方法。 - 請求項8に記載の半導体装置の製造方法において、
さらに、
(g)平面視において、前記ボディ領域の周囲を連続的に取り囲む前記第2導電型の第4半導体領域を、前記ターミネーション領域に形成する工程、
を有する、半導体装置の製造方法。 - 請求項8に記載の半導体装置の製造方法において、
前記(c)工程は、さらに、
(c1)前記第2マスク層を用いて、前記ボディ領域と前記第1半導体領域とを連結する前記第2導電型の複数の第7半導体領域を形成する工程、
を有する、半導体装置の製造方法。 - 請求項8に記載の半導体装置の製造方法において、
前記(b)工程は、さらに、
(b2)前記第1マスク層を用いて、前記第1半導体領域の下に、前記第1導電型の第6半導体領域を形成する工程、
を有する、半導体装置の製造方法。
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