TW201901959A - 半導體裝置及半導體裝置之製造方法 - Google Patents

半導體裝置及半導體裝置之製造方法 Download PDF

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TW201901959A
TW201901959A TW107103198A TW107103198A TW201901959A TW 201901959 A TW201901959 A TW 201901959A TW 107103198 A TW107103198 A TW 107103198A TW 107103198 A TW107103198 A TW 107103198A TW 201901959 A TW201901959 A TW 201901959A
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TWI702722B (zh
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山口一哉
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日商富士電機股份有限公司
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  • Electrodes Of Semiconductors (AREA)

Abstract

提供適用於溝槽閘極與溝槽觸部，可以實現高耐壓/低導通電阻，而且可以提高雪崩耐受能力的半導體裝置及半導體裝置之製造方法。 　　半導體裝置具備：第1導電型的半導體基板(1)；第1導電型的n型漂移層(50)；及第2導電型的第1半導體層(7)。又，半導體裝置具有供主電流流動的活化區域(20)，該活化區域(20)具有：從第1半導體層(7)之表面到達n型漂移層(50)的溝槽(51)；及在溝槽(51)之內部隔著閘極絕緣膜(5)而設置的閘極電極(6)。又，半導體裝置具備包圍活化區域(20)之周圍的終端區域(30)，該終端區域(30)具有與閘極金屬(17)接觸的閘極觸部(C)，該閘極金屬(17)連接於閘極電極(6)。終端區域(30)具有：與第1半導體層(7)連接，且延伸至閘極觸部(C)之底部的第2導電型之第1半導體區域(12)。

Description

半導體裝置及半導體裝置之製造方法
[0001] 本發明關於半導體裝置及半導體裝置之製造方法。
[0002] 通常，電力MOSFET(Metal Oxide Semiconductor Field Effect Transistor：絕緣閘型場效電晶體)在導通電阻與耐壓之間存在取捨之關係。例如通常之平面型之n通道縱型MOSFET之情況下，高電阻的n- 型漂移層之部分，在MOSFET成為導通狀態時係發揮向縱向流通漂移電流的區域之機能，而在非導通狀態時成為空乏化提高耐壓。縮短該高電阻的n- 型漂移層之電流路徑意味著漂移電阻變低而與降低MOSFET之實質的導通電阻之效果有關連，但反面是從p型基極區域與n- 型漂移層之間之pn接合進行的汲極-基極間空乏層之擴展寬度變窄，迅速到達矽(Si)之臨界電場強度，因此降低耐壓。 　　[0003] 反之，高耐壓的半導體裝置中，n- 型漂移層較厚，因此當然地導通電阻變大，損失增大。如此般，導通電阻與耐壓之間存在取捨關係。作為該問題的解決對策，有具有超接合面構造(Super Junction構造：SJ構造)的SJ-MOSFET。以提高雜質濃度的n型區域與p型區域交互配置而成的並聯pn構造(SJ構造)來構成漂移層，使非導通狀態時成為空乏化來負擔耐壓。 　　[0004] 與通常之平面型之n通道縱型MOSFET之構造上之差異在於，漂移部並非一樣･單一之導電型，而是成為將縱型層狀之n型漂移區域與縱型層狀之p型間隔區域交替且反復地接合而成的並聯pn構造(SJ構造)。即使並聯pn構造之雜質濃度較高，但在非導通狀態，空乏層從並聯pn構造之沿縱向配向的各pn接合朝其之橫向雙方擴張，而使漂移區域全體空乏化，因此可以達成高耐壓化。 　　[0005] 該SJ-MOSFET中欲實現高耐壓/低導通電阻需要微細化。為了達成微細化，溝槽閘極(trench gate)與溝槽觸部(trench contact)之適用為有效(例如參照專利文獻1)。溝槽閘極係在形成於矽的溝之中構成閘極的方法中，將溝槽側壁設為通道，因此可以達成微細化。又，溝槽觸部係在形成於矽的溝之中形成接觸區域的方法中，藉由溝槽側壁接觸源極，藉由溝槽底接觸p+ 型層而使微細化成為可能。 　　[0006] 圖10表示習知SJ-MOSFET之構造的斷面圖。如圖10所示，SJ-MOSFET係以在高雜質濃度之n+ 型汲極層1成長有n型漂移層50的晶圓為材料。SJ-MOSFET具備：活化部20；及包圍活化部20之周圍的終端構造部(邊緣部)30。其中，終端構造部30係設有後述的閘極配線15的區域，活化部20係終端構造部30之內側之區域。活化部20中設有由該晶圓表面貫穿n型漂移層50未到達n+ 型汲極層1的p型柱區域3。n型漂移層50之中未設有p型柱區域3的區域係成為n型柱區域2。圖10中，p型柱區域3未到達n+ 型汲極層1，但亦可以到達n+ 型汲極層1。 　　[0007] 在n型柱區域2及p型柱區域3之表面設置p型基極層7。在p型基極層7之表面側設置溝槽閘極A及溝槽觸部B。沿著溝槽閘極A之側壁設置閘極絕緣膜5，在閘極絕緣膜5之內側設置閘極電極6。溝槽閘極A之底與n型柱區域2相接。又，在p型基極層7之內部設置n型源極區域8及p+ 型接觸區域10。p+ 型接觸區域10設於溝槽觸部B之底。設置藉由溝槽觸部B之側壁與n型源極區域8相接，藉由溝槽觸部B之底與p+ 型接觸區域10相接的源極電極11，源極電極11與閘極電極6透過層間絕緣膜9進行絕緣。又，在n+ 型汲極層1之背面設置汲極電極4。 　　[0008] 又，在保持耐壓的終端構造部30設有p型RESURF(REduced SURface Field，降低表面電場)區域12(例如專利文獻1)。藉由p型RESURF區域12來緩和施加在p型阱區域13端部的電場集中，該p型阱區域13設於最外周之n型柱區域2與p型柱區域3上，據此可以提升終端構造部30之耐壓。又，填埋於溝槽閘極A的閘極電極6之多晶矽(Poly-Si)，係由溝槽閘極A終端被引出而連接於閘極配線15，於終端構造部30中與閘極金屬17在閘極觸部(gate contact)C中相接。閘極金屬17及閘極配線15與n型漂移層50係透過LOCOS(Local Oxidation of Silicon)氧化膜16進行絕緣。 　　[0009] 例如第1導電型之第1半導體層與第2導電型之第2半導體層，在具有交互週期性被形成的柱部構造之漂移層的半導體裝置之終端區域2，與P+型保護環層21相接，以朝元件區域1之相反側擴展的方式，在表面形成有P型RESURF層22的構造存在(例如參照專利文獻2)。 ［先前技術文獻］ ［專利文獻］ 　　[0010] 　　[專利文獻1]特開2007-149736號公報 　　[專利文獻2]特開2009-4688號公報
［發明所欲解決之課題］ 　　[0011] 於此，圖11、12表示習知SJ-MOSFET之製造中途之狀態的斷面圖。如圖11所示，在與閘極觸部C及溝槽觸部B對應的部分對具有開口部的阻劑18照射電漿19。據此，習知SJ-MOSFET中，同時形成終端構造部30之閘極觸部C及活化部20之溝槽觸部B。 　　[0012] 此時，發生以下之問題。活化部20之矽(p型基極層7)被蝕刻時，終端構造部30中閘極配線15之多晶矽被蝕刻。但是，和矽比較，多晶矽之蝕刻速率較快，因此在活化部20之溝槽觸部B形成之前，終端構造部30之多晶矽完全被蝕刻，底層之LOCOS氧化膜16暴露於電漿19。如此則，直至活化部20之溝槽觸部B到達所要之深度為止，終端構造部30之LOCOS氧化膜16暴露於電漿19。因此如圖12所示，LOCOS氧化膜16亦被電漿19削去，因此閘極觸部C之下之LOCOS氧化膜16變薄。例如以SEM(Scanning Electron Microscope：掃描型電子顯微鏡)觀察LOCOS氧化膜16時閘極觸部C之下凹陷而變薄。又，電漿19之損傷亦降低LOCOS氧化膜16之膜質(絕緣性)。 　　[0013] 如上述說明，在活化部20形成溝槽觸部B時，閘極觸部C之下之LOCOS氧化膜16變薄，而且，膜質(絕緣性)降低。該情況下，如圖10所示，在p型RESURF區域12之端部引起雪崩擊穿時，雪崩擊穿產生的電流流入閘極觸部C之下之低膜質之LOCOS氧化膜16，導致元件被破壞之問題。 　　[0014] 本發明為解消上述習知技術之問題點，目的在於提供適用於溝槽閘極與溝槽觸部，可以實現高耐壓/低導通電阻，而且可以提高雪崩耐受能力(avalanche resistance)的半導體裝置及半導體裝置之製造方法。 ［用以解決課題的手段］ 　　[0015] 為解決上述課題，達成本發明之目的，本發明的半導體裝置具有以下之特徵。在第1導電型的半導體基板之第1主面上設有第1導電型的漂移層。在上述漂移層之表面層設有第2導電型的第1半導體層。設置有供主電流流動的活化區域，該活化區域具有：從上述第1半導體層之表面到達上述漂移層的溝槽；及在上述溝槽之內部隔著閘極絕緣膜而設置的閘極電極。設置具有閘極觸部、且包圍上述活化區域之周圍的終端區域，該閘極觸部係與連接於上述閘極電極的閘極金屬接觸。上述終端區域具有：連接於上述第1半導體層，且延伸至上述閘極觸部之底部的第2導電型之第1半導體區域。 　　[0016] 又，本發明的半導體裝置之特徵為，係於上述發明中，於上述終端區域中，在上述第1半導體區域與上述閘極金屬之間設有絕緣膜，上述閘極觸部的上述底部的下部之上述絕緣膜之膜厚，係較未設置有上述閘極觸部的區域中的上述絕緣膜之膜厚薄。 　　[0017] 又，本發明的半導體裝置之特徵為，係於上述發明中，上述閘極觸部的上述底部的下部之上述絕緣膜之膜厚，係較未設置有上述閘極觸部的區域中的上述絕緣膜之膜厚薄3~15%。 　　[0018] 又，本發明的半導體裝置之特徵為，係於上述發明中，上述閘極觸部的上述底部的下部之上述第1半導體區域之膜厚在1.4μm以上2.0μm以下。 　　[0019] 又，本發明的半導體裝置之特徵為，係於上述發明中，設置有上述閘極觸部的區域中的上述第1半導體區域之雜質濃度在5×1016 /cm3 以上1×1017 /cm3 以下。 　　[0020] 又，本發明的半導體裝置之特徵為，係於上述發明中，上述閘極觸部的上述終端構造部側之側面與上述第1半導體區域的上述終端構造部側之端部之間之距離在3.5μm以上。 　　[0021] 又，本發明的半導體裝置之特徵為，係於上述發明中，在上述漂移層中，第1導電型的第1柱與第2導電型的第2柱在上述第1主面上沿著與上述第1主面平行的方向交替且反複地配置。 　　[0022] 為解決上述課題，達成本發明之目的，本發明的半導體裝置之製造方法具有以下之特徵。一種半導體裝置之製造方法，該半導體裝置具備：第1導電型的半導體基板；第1導電型的漂移層，配置於上述半導體基板之第1主面上；活化區域，設於上述漂移層之表面，供主電流流動；及終端區域，包圍上述活化區域之周圍；首先，進行第1工程，其係進行離子植入而在上述終端區域之上述漂移層之表面層形成第2導電型之第1半導體區域。接著，進行第2工程，係在上述第1工程後在上述終端區域之第1半導體區域與上述終端區域之上述漂移層之表面形成LOCOS氧化膜。接著，進行第3工程，係由上述活化區域之上述漂移層之表面沿著與上述第1主面垂直的方向形成溝槽。接著，進行第4工程，係在上述第3工程後在上述漂移層之整個上表面形成閘極絕緣膜。接著，進行第5工程，係在上述第4工程後在閘極絕緣膜之整個上表面沈積多晶矽。接著，進行第6工程，係在上述第5工程後形成上述溝槽內之閘極電極與上述終端區域之閘極配線。接著，進行第7工程，係在上述第6工程後在上述活化區域之上述漂移層之表面層形成第2導電型的阱區域。接著，進行第8工程，係在上述第1半導體層之表面層形成第1導電型的源極區域。接著，進行第9工程，係在上述第8工程後在上述漂移層之整個上表面形成層間絕緣膜。接著，進行第10工程，係將上述層間絕緣膜之一部分除去而由連接於上述閘極電極的上述閘極配線來形成與閘極金屬接觸的閘極觸部。上述第1工程中，係使上述第1半導體區域延伸至設置有上述閘極觸部的區域。 　　[0023] 又，本發明的半導體裝置之製造方法之特徵為，係於上述發明中，上述第10工程中，係同時形成上述活化區域的溝槽觸部及上述閘極觸部。 　　[0024] 依據上述發明，p型RESURF區域(第2導電型的第2半導體區域)係被延伸至設置有閘極觸部的區域，覆蓋閘極觸部之下。據此，雪崩擊穿產生的電流可由p型RESURF區域經由p型阱區域直接排出至源極電極。因此在具有溝槽閘極與溝槽觸部的半導體裝置中，可以獲得高的雪崩耐受能力。 ［發明之效果］ 　　[0025] 依據本發明的半導體裝置及半導體裝置之製造方法，可以達成以下效果：適用於溝槽閘極與溝槽觸部，能實現高耐壓/低導通電阻，而且可以提高雪崩耐受能力。
[0027] 以下參照添附圖面詳細說明本發明的半導體裝置及半導體裝置之製造方法之較佳實施形態。本說明書及添附圖面中，標記有n或p之層或區域分別意味著電子或電洞為多數載子。又，附加於n或p的+及-分別意味著比起未附加該符號的層或區域為高雜質濃度及低雜質濃度。包含+及-的n或p之標記為同一之情況表示接近的濃度，不限定於濃度相等。又，以下之實施形態之說明及添附圖面中，同樣之構成附加同一之符號，並省略重複說明。 　　[0028] (實施形態) 　　針對本發明的半導體裝置以SJ-MOSFET為例進行說明。圖1表示實施形態的SJ-MOSFET之構造的斷面圖。圖1中僅表示2個單位格(元件之機能單位)，省略與彼等鄰接的其他單位格之圖示。圖1所示SJ-MOSFET，係在由矽形成的半導體基體(矽基體：半導體晶片)之表面(p型基極層7側之面)側具備MOS(Metal Oxide Semiconductor)閘極的SJ-MOSFET。該SJ-MOSFET具備：活化部20；及包圍活化部20之周圍的終端構造部30。活化部20係在導通狀態時流通電流的區域。終端構造部30係緩和漂移區域之基體表面側之電場並保持耐壓的區域。 　　[0029] 矽基體係在成為n+ 型汲極層(第1導電型的半導體基板)1之n+ 型半導體基板之表面上成長n型漂移層50，於n型漂移層50內交替設置具有超接合面構造(SJ構造)的n型柱區域2與p型柱區域3。MOS閘極係由p型基極層(第2導電型的第1半導體層)7、n型源極區域8、p+ 型接觸區域10、溝槽閘極A、溝槽觸部B、閘極絕緣膜5及閘極電極6構成。又，在n+ 型汲極層1之背面設有汲極電極4。 　　[0030] 於活化部20設有SJ構造。SJ構造係將n型柱區域2與p型柱區域3交替且反複地接合而成。p型柱區域3以從n型漂移層50之表面未到達n+ 型汲極層1之表面的方式設置。n型柱區域2與p型柱區域3之平面形狀例如為條紋狀、六方格子狀或正方狀。又，p型柱區域3到達n+ 型汲極層1之表面亦可。 　　[0031] 又，於活化部20設有到達n型柱區域2的溝槽51，由多晶矽形成的閘極電極6隔著閘極絕緣膜5被填埋於溝槽51。據此而設置溝槽閘極A。又，在p型柱區域3之上(源極電極11側)設置p型基極層7，在p型基極層7之表面設置n型源極區域8。在閘極電極6上設置供作為與源極電極11絕緣用的層間絕緣膜9。貫穿層間絕緣膜9而在p型基極層7之表面設置溝槽52，p+ 型接觸區域10與源極電極11在溝槽52之底被連接，n型源極區域8與源極電極11在溝槽52之側壁被連接。據此而設置溝槽觸部B。 　　[0032] 又，在外周之終端構造部30設置與p型柱區域3連接的p型阱區域13，於其外側設置與p型阱區域13連接的p型RESURF區域(第2導電型之第1半導體區域)12。p型RESURF區域12之雜質濃度高於p型柱區域3。在p型RESURF區域12與p型阱區域13之上設置絕緣膜14，隔著絕緣膜14設置閘極配線15。該閘極配線15係與被填埋於設置在活化部20的溝槽51之閘極電極6連接。於閘極配線15之上設置層間絕緣膜9。 　　[0033] 又，於絕緣膜14之外側設置LOCOS氧化膜16，閘極配線15延伸至LOCOS氧化膜16之上。於外周之終端構造部30設置貫穿層間絕緣膜9及閘極配線15的溝槽53，於溝槽53之內部填埋有閘極金屬17。據此而設置閘極配線15與閘極金屬17連接的閘極觸部C。閘極配線15通過閘極金屬17連接於閘極焊墊(未圖示)。閘極金屬較佳為鋁或含鋁的金屬。 　　[0034] 又，如後述說明，基於電漿蝕刻造成LOCOS氧化膜16在溝槽53之底部之部分(圖1之X所示部分)變薄。亦即，閘極觸部C之底部(溝槽53之底部)之下之部分的膜厚，較未設置閘極觸部C的部分之膜厚為薄。例如閘極觸部C之底部(溝槽53之底部)之下之部分之膜厚較未設置閘極觸部C的部分之膜厚(LOCOS氧化膜16之膜厚)薄3~15%。又，例如LOCOS氧化膜16之膜厚為0.35μm，閘極觸部C之底部(溝槽53之底部)之下之部分之膜厚為0.3μm以上0.34μm以下。 　　[0035] 另外，LOCOS氧化膜16基於電漿蝕刻而受到損傷，因此膜質(絕緣性)降低，電阻變低。此乃因為電漿蝕刻造成電子、離子等進入LOCOS氧化膜16，在其他部位出現與本來之準位不同的準位，電流經由此而流動。 　　[0036] 又，p型RESURF區域12連接於p型阱區域13，延伸至設有閘極觸部C的區域，並覆蓋閘極觸部C之底部。p型RESURF區域12之終端構造部30側的端部與閘極觸部C之終端構造部30側之側面(溝槽53之終端構造部30側之側面)之間之距離Y(圖1之Y所示部分)至少分離3.5μm以上即可。於此，p型RESURF區域12構成為越接近p型RESURF區域12之表面雜質濃度越高亦可。因為越接近表面越減低電阻，可以使雪崩擊穿產生的電流容易流動。又，p型RESURF區域12之雜質濃度、膜厚按SJ-MOSFET之耐壓而變。例如SJ-MOSFET之耐壓為100~150V時，雜質濃度、膜厚分別為5×1016 /cm3 以上1×1017 /cm3 以下、1.4μm以上2.0μm以下為較好。又，溝槽觸部B及閘極觸部C之平面形狀可以是條紋狀，亦可以是點狀。 　　[0037] 如上述說明，以p型RESURF區域12覆蓋閘極觸部C之底部，因此雪崩耐受能力之發生點由閘極觸部C之底部朝外側移動而位於分離的位置(圖1之Z所示部分)。另外，損傷雖減低LOCOS氧化膜16之電阻，但p型區域之電阻更低，因此雪崩擊穿產生的電流從p型區域亦即p型RESURF區域12經由p型阱區域13直接排出至源極電極11(參照圖1之箭頭40)。如上述說明，雪崩擊穿產生的電流不流入閘極觸部C之下之膜厚變薄的LOCOS氧化膜16，因此可以防止元件被破壞。因此本實施形態之SJ-MOSFET可以獲得高的雪崩耐受能力。 　　[0038] (實施形態的半導體裝置之製造方法) 　　接著，說明實施形態的半導體裝置之製造方法。圖2~7表示實施形態的SJ-MOSFET之製造中途之狀態的斷面圖。首先，準備由矽形成而成為n+ 型汲極層1的n+ 型半導體基板。接著，於n+ 型汲極層1之表面上重複進行磊晶成長與離子植入，形成由n型柱區域2與p型柱區域3形成的SJ構造。至此之狀態如圖2之記載。又，未設置有n型柱區域2及p型柱區域3的區域係成為n型漂移層50。又，SJ構造，可以在n+ 型汲極層1之表面上藉由磊晶成長形成n型漂移層50，從n型漂移層50之上面在形成p型柱區域3之位置形成溝槽並將形成p型柱區域3的半導體層填埋於溝槽之內部。 　　[0039] 接著，藉由光微影成像及蝕刻形成遮罩成為p型雜質之離子植入，在n型漂移層50之終端構造部30側之表面層形成p型RESURF區域12。p型RESURF區域12係在由活化部20之最外周之p型柱區域3至形成閘極觸部C的區域之間被形成，以未到達p型柱區域3之深度被形成。至此之狀態係如圖3之記載。 　　[0040] 接著，在包含濕式O2 (氧)氧化或熱解氧化(Pyrogenic oxidation)等之水蒸氣的氛圍下，進行高溫･長時間之熱處理，進行熱氧化而在終端構造部30形成LOCOS氧化膜16。藉由此時之熱處理，p型RESURF區域12擴展而與p型柱區域3連接。LOCOS氧化膜16設於終端構造部30之p型RESURF區域12與n型漂移層50之表面。至此之狀態係如圖4之記載。 　　[0041] 接著，於活化部20形成溝槽閘極A。形成從n型漂移層50之表面上到達n型柱區域2的溝槽51。溝槽形成時之遮罩係使用氧化膜。接著，沿著n型漂移層50之表面及溝槽51之內壁形成閘極絕緣膜5。接著，以填埋於溝槽51的方式沈積例如多晶矽，藉由對活化部20之部分進行蝕刻，使成為閘極電極6的多晶矽殘留於溝槽51之內部而設置溝槽閘極A，使成為閘極配線15的多晶矽殘留於終端構造部30。此時，填埋於溝槽51的多晶矽，藉由進行回蝕刻(etch back)以使殘留於比起n型漂移層之表面更內側的方式進行蝕刻亦可，或藉由實施圖案化與蝕刻使進行比起n型漂移層之表面更朝外側突出亦可。至此之狀態係如圖5所示。 　　[0042] 接著，在n型漂移層50之表面上，藉由光微影成像技術例如以氧化膜形成具有所要之開口部的未圖示的離子植入用遮罩。以該離子植入用遮罩作為遮罩進行p型雜質之離子植入，在n型漂移層50之表面層形成p型基極層7。接著，除去離子植入用遮罩。 　　[0043] 接著，在p型基極層7之表面上，藉由光微影成像技術例如以氧化膜形成具有所要之開口部的未圖示的離子植入用遮罩。以該離子植入用遮罩作為遮罩進行n型雜質之離子植入，於p型基極層7之表面層形成n型源極區域8。接著，除去離子植入用遮罩。至此之狀態係如圖6所示。 　　[0044] 接著，在n型漂移層50之表面上之全面形成層間絕緣膜9。層間絕緣膜9例如由BPSG(Boro Phospho Silicate Glass)形成。接著，為了進行層間絕緣膜9之平担化而進行回焊處理。層間絕緣膜9亦可以由NSG(None-doped Silicate Glass：非摻雜矽酸鹽玻璃)、PSG(Phospho Silicate Glass)、HTO(High Temperature Oxide)或彼等之組合形成。 　　[0045] 接著， 同時形成到達活化部20中之p型基極層7的溝槽觸部B及到達終端構造部30中之LOCOS氧化膜16的閘極觸部C。藉由將進行溝槽觸部B之形成的溝槽52與進行閘極觸部C之形成的溝槽53予以同時形成，可以削減工時。溝槽形成時之遮罩係使用氧化膜。例如藉由對與閘極觸部C及溝槽觸部B對應的部分具有開口部的遮罩(未圖示)照射電漿，而可以在形成閘極觸部C之位置及在形成溝槽觸部B之位置同時形成溝槽52及溝槽53。此時，溝槽53之底部(閘極觸部C之底部之下)之LOCOS氧化膜16基於電漿蝕刻而受到損傷，膜質(絕緣性)降低並變薄。又，蝕刻只要是異方性即可，亦可以藉由電漿蝕刻以外之乾蝕刻進行。 　　[0046] 接著，於溝槽52之底進行p型雜質之離子植入，在p型基極層7之內部形成雜質濃度高於p型基極層7的p+ 型接觸區域10。接著，對已實施離子植入的區域進行活化退火。例如活化退火在950℃進行。據此而使被離子植入n型源極區域8、p+ 型接觸區域10、p型RESURF區域12及p型阱區域13的雜質活化。至此之狀態係如圖7所示。 　　[0047] 接著，以覆蓋層間絕緣膜9的方式形成由鈦(Ti)或氮化鈦(TiN)形成的阻障層金屬(未圖示)並進行圖案化，使n型源極區域8、p+ 型接觸區域10及閘極配線15露出。接著，以與n型源極區域8及p+ 型接觸區域10接觸的方式形成源極電極11。源極電極11以覆蓋阻障層金屬的方式形成亦可，僅殘留於溝槽52內亦可。又，為防止源極電極11之鋁銅合金之覆蓋率惡化，可以使用鎢(W)栓塞。接著，以與閘極配線15接觸的方式形成閘極金屬17。又，溝槽53內亦可以使用阻障層金屬或鎢(W)栓塞。 　　[0048] 接著，以填埋溝槽52的方式形成源極焊墊(未圖示)。以為了形成源極焊墊而沈積的金屬層之一部分作為閘極焊墊亦可。於n+ 型汲極層1之背面，在汲極電極4之接觸部使用濺鍍蒸鍍等形成鎳(Ni)膜、鈦(Ti)膜等之金屬膜。該金屬膜亦可以將複數層Ni膜、Ti膜組合進行積層。之後，實施高速熱處理(RTA：Rapid Thermal Annealing)等之退火使金屬膜矽化物化而形成歐姆接觸。之後，例如藉由電子束(EB：Electron Beam)蒸鍍等形成依序積層有Ti膜、Ni膜、金(Au)之積層膜等之厚膜，形成汲極電極4。 　　[0049] 在上述磊晶成長及離子植入中，作為n型雜質(n型摻雜物)例如可以使用相對於碳化矽成為n型的氮(N)或磷(P)、砷(As)、銻(Sb)等。作為p型雜質(p型摻雜物)例如可以使用相對於碳化矽成為p型的硼(B)或鋁(Al)、鎵(Ga)、銦(In)、鉈(Tl)等。如此而完成圖1所示SJ-MOSFET。 　　[0050] 又，以上之說明中說明SJ-MOSFET之例，但本發明亦適用具有溝槽觸部及閘極觸部的MOSFET、IGBT(Insulated Gate Bipolar Transistor：絕緣閘型雙極電晶體)。圖8表示實施形態的MOSFET之構造的斷面圖。圖8中，符號21、22分別表示n+ 型半導體基板、n- 型漂移層。其他構造和圖1之SJ-MOSFET同樣，因此省略。圖9表示實施形態的IGBT之構造的斷面圖。圖9中，符號23~26分別表示p型集極層、n型射極區域、射極電極、集極電極。其他構造和圖1之SJ-MOSFET同樣，因此省略。 　　[0051] 如以上說明，依據實施形態，p型RESURF區域延伸至設置有閘極觸部的區域，覆蓋閘極觸部之下。據此，雪崩擊穿產生的電流可以由p型RESURF區域經由p型阱區域直接排出至源極電極。因此在具有溝槽閘極及溝槽觸部的半導體裝置中，可以獲得高的雪崩耐受能力。 　　[0052] 以上說明的本發明中，係以在矽基板之第1主面上構成MOS閘極構造之情況為例進行說明，但不限定於此，半導體之種類(例如碳化矽(SiC)等)、基板主面之面方位等可以作各種變更。又，本發明之各實施形態中將第1導電型設為p型，將第2導電型設為n型，但本發明將第1導電型設為n型，將第2導電型設為p型亦同樣成立。 ［產業上之可利用性］ 　　[0053] 如以上之說明，本發明的半導體裝置及半導體裝置之製造方法，適合應用於電力變換裝置或各種產業用機械等之電源裝置等所使用的高耐壓半導體裝置，特別是適用於具有溝槽構造的高耐壓半導體裝置。
[0054]
1‧‧‧n+型汲極層
2‧‧‧n型柱區域
3‧‧‧p型柱區域
4‧‧‧汲極電極
5‧‧‧閘極絕緣膜
6‧‧‧閘極電極
7‧‧‧p型基極層
8‧‧‧n型源極區域
9‧‧‧層間絕緣膜
10‧‧‧p+型接觸區域
11‧‧‧源極電極
12‧‧‧p型RESURF區域
13‧‧‧p型阱區域
14‧‧‧絕緣膜
15‧‧‧閘極配線
16‧‧‧LOCOS氧化膜
17‧‧‧閘極金屬
18‧‧‧阻劑
19‧‧‧電漿
20‧‧‧活化部
21‧‧‧n+型半導體基板
22‧‧‧n-型漂移層
23‧‧‧p型集極層
24‧‧‧n型射極區域
25‧‧‧射極電極
26‧‧‧集極電極
30‧‧‧終端構造部
40‧‧‧箭頭
50‧‧‧n型漂移層
51、52、53‧‧‧溝槽
A‧‧‧溝槽閘極
B‧‧‧溝槽觸部
C‧‧‧閘極觸部
[0026] 　　[圖1]實施形態的SJ-MOSFET之構造的斷面圖。 　　[圖2]實施形態的SJ-MOSFET之製造中途之狀態的斷面圖(其1)。 　　[圖3]實施形態的SJ-MOSFET之製造中途之狀態的斷面圖(其2)。 　　[圖4]實施形態的SJ-MOSFET之製造中途之狀態的斷面圖(其3)。 　　[圖5]實施形態的SJ-MOSFET之製造中途之狀態的斷面圖(其4)。 　　[圖6]實施形態的SJ-MOSFET之製造中途之狀態的斷面圖(其5)。 　　[圖7]實施形態的SJ-MOSFET之製造中途之狀態的斷面圖(其6)。 　　[圖8]實施形態的MOSFET之構造的斷面圖。 　　[圖9]實施形態的IGBT之構造的斷面圖。 　　[圖10]習知SJ-MOSFET之構造的斷面圖。 　　[圖11]習知SJ-MOSFET之製造中途之狀態的斷面圖(其1)。 　　[圖12]習知SJ-MOSFET之製造中途之狀態的斷面圖(其2)。

Claims (9)

  1. 一種半導體裝置，其特徵為： 　　具備：第1導電型的半導體基板； 　　第1導電型的漂移層，設於上述半導體基板之第1主面上；及 　　第2導電型的第1半導體層，設於上述漂移層之表面層； 　　具備：供主電流流動的活化區域，該活化區域具有從上述第1半導體層之表面到達上述漂移層的溝槽，及在上述溝槽之內部隔著閘極絕緣膜而設置的閘極電極；及 　　終端區域，其具有閘極觸部(gate contact)，且包圍上述活化區域之周圍，該閘極觸部係與連接於上述閘極電極的閘極金屬接觸； 　　上述終端區域具有：第2導電型之第1半導體區域，其連接於上述第1半導體層，且延伸至上述閘極觸部之底部。
  2. 如申請專利範圍第1項之半導體裝置，其中 　　於上述終端區域中，在上述第1半導體區域與上述閘極金屬之間設有絕緣膜， 　　上述閘極觸部的上述底部的下部之上述絕緣膜之膜厚，係較未設置有上述閘極觸部的區域中的上述絕緣膜之膜厚薄。
  3. 如申請專利範圍第2項之半導體裝置，其中 　　上述閘極觸部的上述底部的下部之上述絕緣膜之膜厚，係較未設置有上述閘極觸部的區域中的上述絕緣膜之膜厚薄3~15%。
  4. 如申請專利範圍第1至3項中任一項之半導體裝置，其中 　　上述閘極觸部的上述底部的下部之上述第1半導體區域之膜厚為1.4μm以上2.0μm以下。
  5. 如申請專利範圍第1至4項中任一項之半導體裝置，其中 　　設置有上述閘極觸部的區域中的上述第1半導體區域之雜質濃度在5×1016 /cm3 以上1×1017 /cm3 以下。
  6. 如申請專利範圍第1至5項中任一項之半導體裝置，其中 　　上述閘極觸部的上述終端構造部側之側面與上述第1半導體區域的上述終端構造部側之端部之間之距離在3.5μm以上。
  7. 如申請專利範圍第1項之半導體裝置，其中 　　在上述漂移層中，第1導電型的第1柱與第2導電型的第2柱在上述第1主面上沿著與上述第1主面平行的方向交替且反複地配置。
  8. 一種半導體裝置之製造方法，該半導體裝置具備：第1導電型的半導體基板；第1導電型的漂移層，配置於上述半導體基板之第1主面上；活化區域，設於上述漂移層之表面，供主電流流動；及終端區域，包圍上述活化區域之周圍；其特徵為該製造方法具有以下工程： 　　第1工程，係進行離子植入而在上述終端區域之上述漂移層之表面層形成第2導電型之第1半導體區域； 　　第2工程，係在上述第1工程後在上述終端區域之第1半導體區域與上述終端區域之上述漂移層之表面形成LOCOS氧化膜； 　　第3工程，係由上述活化區域之上述漂移層之表面沿著與上述第1主面垂直的方向形成溝槽； 　　第4工程，係在上述第3工程後在上述漂移層之整個上表面形成閘極絕緣膜； 　　第5工程，係在上述第4工程後在閘極絕緣膜之整個上表面沈積多晶矽； 　　第6工程，係在上述第5工程後形成上述溝槽內之閘極電極與上述終端區域之閘極配線； 　　第7工程，係在上述第6工程後在上述活化區域之上述漂移層之表面層形成第2導電型的阱區域； 　　第8工程，係在上述第1半導體層之表面層形成第1導電型的源極區域； 　　第9工程，係在上述第8工程後在上述漂移層之整個上表面形成層間絕緣膜；及 　　第10工程，係將上述層間絕緣膜之一部分除去而由連接於上述閘極電極的上述閘極配線來形成與閘極金屬接觸的閘極觸部； 　　上述第1工程中，係使上述第1半導體區域延伸至設置有上述閘極觸部的區域。
  9. 如申請專利範圍第8項之半導體裝置之製造方法，其中 　　上述第10工程中，係同時形成設於上述活化區域的溝槽觸部及上述閘極觸部。
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