JP5271515B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP5271515B2 JP5271515B2 JP2007183917A JP2007183917A JP5271515B2 JP 5271515 B2 JP5271515 B2 JP 5271515B2 JP 2007183917 A JP2007183917 A JP 2007183917A JP 2007183917 A JP2007183917 A JP 2007183917A JP 5271515 B2 JP5271515 B2 JP 5271515B2
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- 239000004065 semiconductor Substances 0.000 title claims description 116
- 229910010271 silicon carbide Inorganic materials 0.000 claims abstract description 37
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims abstract description 36
- 239000000758 substrate Substances 0.000 claims abstract description 35
- 239000000463 material Substances 0.000 claims description 17
- 230000004888 barrier function Effects 0.000 claims description 9
- 238000004519 manufacturing process Methods 0.000 description 21
- 239000012535 impurity Substances 0.000 description 17
- 238000005468 ion implantation Methods 0.000 description 14
- 238000009792 diffusion process Methods 0.000 description 13
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 12
- 229920005591 polysilicon Polymers 0.000 description 12
- 238000010586 diagram Methods 0.000 description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 238000000034 method Methods 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 238000001459 lithography Methods 0.000 description 6
- 239000002184 metal Substances 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 210000000746 body region Anatomy 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000002457 bidirectional effect Effects 0.000 description 2
- 229910052799 carbon Inorganic materials 0.000 description 2
- 238000000605 extraction Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 238000000137 annealing Methods 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000003252 repetitive effect Effects 0.000 description 1
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- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
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- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
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Description
まず、本実施の形態1では、ゲート制御型の半導体素子(スイッチング素子、トランジスタ)として接合FETを備えた半導体装置について図1〜図4を参照して説明する。図1〜図4は、それぞれ本実施の形態1における半導体装置の等価回路図、平面図、要部平面図、および要部断面図を示している。図2には、チップ状態の半導体装置(チップCHP)が示されており、そのチップCHP上にはゲートパッドGPおよびソースパッドSPが設けられている。また、図3は図2のゲートパッドGP領域であって、ゲートパッドGPを取り除いた場合の平面図である。また、図3のA−A’線の断面が図4に示されている。なお、本願においてはゲートパッドGPをゲート電極と、またソースパッドSPをソース電極として説明する場合もある。また、図2のチップCHPの裏面電極として図4に示すようにドレイン電極17が設けられている。
本実施の形態2では、ゲート制御型の半導体素子(スイッチング素子、トランジスタ)として接合FETを備えた半導体装置について図13、図14を参照して説明する。図13および図14は、それぞれ本実施の形態2における半導体装置の等価回路図および要部断面図を示している。
本実施の形態3では、ゲート制御型の半導体素子(スイッチング素子、トランジスタ)としてMISFETを備えた半導体装置について図15〜図17を参照して説明する。図15および図16は、それぞれ本実施の形態3における半導体装置の要部平面図および要部断面図を示している。図15は例えば図2で示したゲートパッドGP領域であって、ゲートパッドGPを取り除いた場合の平面図であり、図15のB−B’線の断面が図16に示されている。また、図17は、本実施の形態3における半導体装置をインバータ回路に適用した場合の回路図を示す。
まず、本実施の形態4では、ゲート制御型の半導体素子(スイッチング素子、トランジスタ)として接合FETを備えた半導体装置について図18〜図20を参照して説明する。図18〜図20は、それぞれ本実施の形態4における半導体装置の等価回路図、要部平面図、および要部断面図を示している。図19は例えば図2で示したゲートパッドGP領域であって、ゲートパッドGPを取り除いた場合の平面図であり、図19のC−C’線の断面が図20に示されている。
本実施の形態5では、ゲート制御型の半導体素子(スイッチング素子、トランジスタ)として接合FETおよびゲートドライバ回路を備えた半導体装置について図25を参照して説明する。図25は、本実施の形態5における半導体装置の等価回路図を示している。
2 pnダイオード
3 pnダイオード
4 n+層
5 p+層
6 n+層
7 p+層
8 n+層
9 p+層
10 pウェル
11 n−層
12 n+基板
13 nウェル
14 ゲート電極
15 コンタクト電極
16 ソース電極
17 ドレイン電極
18 ショットキーバリアダイオード
19 ショットキーメタル
20、20’ ゲート配線
21 フリーホイールダイオード
22 pnダイオード
23、23’、23’’ pnダイオード
24 pnダイオード
25、25’ pnダイオード
26 n+層
27 p+層
28 p層
29 n−層
30 n+基板
31 埋め込みn層
32 酸化膜
33 ソース電極
34 ゲート電極
35 ドレイン電極
36 絶縁膜
37 ポリシリコン膜
38 p+層
39 n+層
40 絶縁膜
41 トレンチ
51、52、53、54 イオン注入マスク
55 絶縁膜
56、57 レジスト膜
CHP チップ
GDR ゲートドライバ回路
GP ゲートパッド
SP ソースパッド
Claims (7)
- 炭化珪素を母材とする半導体素子には、前記半導体素子のチップ上に複数のダイオードが内蔵されており、
前記複数のダイオードのうちの第1ダイオードはアノードが前記半導体素子のゲートに、カソードが前記チップのゲートパッドに接続されており、
前記複数のダイオードのうちの第2ダイオードはカソードが前記半導体素子の前記ゲートに、アノードが前記チップの前記ゲートパッドに接続されており、
前記第1ダイオードが炭化珪素を母材とするショットキーバリアダイオードであり、
前記第2ダイオードが炭化珪素を母材とするpnダイオードであることを特徴とする半導体装置。 - 請求項1記載の半導体装置において、
前記半導体素子が接合FET、MISFET、IGBTのいずれかであることを特徴とする半導体装置。 - 第1面に第1電極および第2電極、前記第1面とは反対の第2面に第3電極を有する炭化珪素基板と、
前記炭化珪素基板の主面に設けられたゲート制御型のトランジスタと、
前記炭化珪素基板の主面に設けられたダイオードと、
を備え、
前記第1電極は前記トランジスタのゲートと電気的に接続されており、
前記第2電極および前記第3電極は前記トランジスタのドリフト領域と電気的に接続されており、
前記ダイオードが前記第1電極と前記ゲートとの間で電気的に接続されており、
前記ダイオードは第1ダイオードと第2ダイオードとで並列に接続されてなり、
前記第1ダイオードのカソードが前記第1電極と、前記第1ダイオードのアノードが前記ゲートと電気的に接続されており、
前記第2ダイオードのアノードが前記第1電極と、前記第2ダイオードのカソードが前記ゲートと電気的に接続されており、
前記第1ダイオードがショットキーダイオード、前記第2ダイオードがpnダイオードであることを特徴とする半導体装置。 - 請求項3記載の半導体装置において、
前記トランジスタは、接合FET、MISFET、またはIGBTの何れかであることを特徴とする半導体装置。 - 請求項3記載の半導体装置において、
前記第2ダイオードは複数で直列に接続されてなることを特徴とする半導体装置。 - 第1面に第1電極および第2電極、前記第1面とは反対の第2面に第3電極を有する炭化珪素基板と、
前記炭化珪素基板の主面に設けられた接合FETと、
前記炭化珪素基板の主面に設けられたダイオードと、
を備え、
第1導電型の前記炭化珪素基板の主面に、前記接合FETの前記第1導電型のドリフト領域が設けられており、
前記炭化珪素基板の主面に、前記ドリフト領域に接合し、前記第1導電型とは逆の第2導電型のゲート領域が設けられており、
前記第1電極は前記ゲート領域と電気的に接続されており、
前記2電極および前記第3電極は前記接合FETの前記ドリフト領域と電気的に接続されており、
前記ダイオードが前記第1電極と前記ゲート領域との間で電気的に接続されており、
前記ダイオードは第1ダイオードと第2ダイオードとで並列に接続されてなり、
前記第1ダイオードのカソードが前記第1電極と、前記第1ダイオードのアノードが前記ゲートと電気的に接続されており、
前記第2ダイオードのアノードが前記第1電極と、前記第2ダイオードのカソードが前記ゲートと電気的に接続されており、
前記第1電極下であって前記炭化珪素の主面に、前記ゲート領域に接合し、第2導電型の第1ウェルが設けられており、
前記炭化珪素の主面であって、前記第1ウェル内に第1導電型の第2ウェルが設けられており、
前記炭化珪素の主面であって、前記第1ウェル内に第1導電型の第1半導体領域が設けられており、
前記炭化珪素の主面であって、前記第2ウェル内に第2導電型の第2半導体領域が設けられており、
前記第1ダイオードのカソードが、前記第1半導体領域であり、
前記第1ダイオードのアノードが、前記第1ウェルであり、
前記第2ダイオードの前記カソードが、前記第2ウェルであり、
前記第2ダイオードの前記アノードが、前記第2半導体領域であることを特徴とする半導体装置。 - 請求項6記載の半導体装置において、
前記第1電極下に前記ダイオードが形成されており、前記第2電極下にトランジスタが形成されていることを特徴とする半導体装置。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007183917A JP5271515B2 (ja) | 2007-07-13 | 2007-07-13 | 半導体装置 |
US12/126,887 US8049223B2 (en) | 2007-07-13 | 2008-05-25 | Semiconductor device with large blocking voltage |
CN2008101081994A CN101345243B (zh) | 2007-07-13 | 2008-05-30 | 半导体器件 |
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JP2007183917A JP5271515B2 (ja) | 2007-07-13 | 2007-07-13 | 半導体装置 |
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JP2009021461A JP2009021461A (ja) | 2009-01-29 |
JP5271515B2 true JP5271515B2 (ja) | 2013-08-21 |
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JP2007183917A Expired - Fee Related JP5271515B2 (ja) | 2007-07-13 | 2007-07-13 | 半導体装置 |
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US (1) | US8049223B2 (ja) |
JP (1) | JP5271515B2 (ja) |
CN (1) | CN101345243B (ja) |
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JP2841936B2 (ja) * | 1991-07-12 | 1998-12-24 | 松下電工株式会社 | 絶縁ゲート型電界効果半導体装置 |
JPH08172188A (ja) * | 1994-12-19 | 1996-07-02 | Kawasaki Steel Corp | 半導体装置 |
US6107649A (en) * | 1998-06-10 | 2000-08-22 | Rutgers, The State University | Field-controlled high-power semiconductor devices |
JP4846106B2 (ja) * | 2001-02-16 | 2011-12-28 | 三菱電機株式会社 | 電界効果型半導体装置及びその製造方法 |
JP4197400B2 (ja) * | 2001-03-29 | 2008-12-17 | 三菱電機株式会社 | 炭化珪素半導体からなる半導体装置 |
JP4961646B2 (ja) * | 2001-08-29 | 2012-06-27 | 株式会社デンソー | 半導体装置およびその製造方法 |
JP2004134547A (ja) * | 2002-10-10 | 2004-04-30 | Hitachi Ltd | 半導体装置 |
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