JP5607947B2 - 半導体装置およびその製造方法 - Google Patents
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/1608—Silicon carbide
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
- H01L29/808—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a PN junction gate, e.g. PN homojunction gate
- H01L29/8083—Vertical transistors
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
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Description
以下、本実施の形態における半導体装置の態様を図面を用いて説明する。図1は本実施の形態の接合FETの平面図を示している。図2および図3は、図1におけるA−A線およびB−B線における断面図をそれぞれ示している。なお、図1、図2および図3では、トレンチ5を埋め込むように形成された層間絶縁膜ならびにその上部に形成された配線および絶縁膜は図示していない。
次に、本実施の形態の接合FETについて、図13に示す断面図を用いて説明する。本実施の形態の接合FETはn+型基板1上にエピタキシャル成長により形成されたn−型ドリフト層2を有し、n−型ドリフト層2の上面にはn+型ソース領域3が形成され、n+型ソース領域3を貫いてn−型ドリフト層2の途中深さまで達するトレンチ5が形成されており、トレンチ5の側壁および底面のn−型ドリフト層2にはp+型ゲート領域4が形成されている。トレンチ5の側壁および底面の表面には絶縁体材料膜である酸化シリコン膜からなる半導体酸化膜16が形成されている。なお、ここではn+型基板1、n−型ドリフト層2、n+型ソース領域3、p+型ゲート領域4、半導体酸化膜16およびp+型ゲート接合層10(図示しない)を含む領域を半導体基板21とする。
2 n−型ドリフト層
3 n+型ソース領域
4 p+型ゲート領域
5 トレンチ
6 ドレイン電極
7 ソースコンタクト層
8 n型層
9 n+型層
10 p+型ゲート接合層
11 ゲートコンタクト層
12 酸化シリコン膜
13 層間絶縁膜
14 アルミニウム配線
15 絶縁膜
16 半導体酸化膜
21 半導体基板
23 ソース領域
24 ゲート領域
Claims (13)
- 第1導電型の半導体基板と、
前記半導体基板上に形成された第1導電型のドリフト層と、
前記ドリフト層の上面から前記ドリフト層の途中深さに達するトレンチと、
前記ドリフト層の上面および前記トレンチの側壁に形成された前記第1導電型のソース領域と、
前記ソース領域の下部の前記ドリフト層内において前記トレンチの側壁および底面に形成された第2導電型のゲート領域と、
を有し、
前記トレンチの側壁の表面において、前記ゲート領域と前記ソース領域とは隣接しており、
前記ゲート領域と前記ソース領域との境界を含む、前記トレンチの表面の前記ゲート領域内に窒素が導入されていることを特徴とする半導体装置。 - 前記ゲート領域が形成されている前記トレンチの側壁および底面に前記窒素を不純物とする前記第1導電型の半導体領域が形成されていることを特徴とする請求項1記載の半導体装置。
- 前記ゲート領域が形成されている前記トレンチの側壁および底面に前記窒素を含む絶縁体材料膜が形成されていることを特徴とする請求項1記載の半導体装置。
- 前記半導体基板は炭化珪素を含むことを特徴とする請求項1記載の半導体装置。
- 前記半導体基板は窒化ガリウムを含むことを特徴とする請求項1記載の半導体装置。
- 前記ソース領域の下部の前記ドリフト層内において前記トレンチの側壁および底面に導入された前記窒素の濃度は1×1018cm-3以下であることを特徴とする請求項1記載の半導体装置。
- 前記半導体領域は前記トレンチの側面および底面を覆っており、前記ゲート領域と前記ソース領域との界面であるpn接合領域は前記トレンチの側壁において露出していないことを特徴とする請求項2記載の半導体装置。
- 第1導電型の半導体基板の主面に形成された接合型電界効果トランジスタを備えた半導体装置の製造方法であって、
(a)前記半導体基板上に前記第1導電型のドリフト層を形成する工程と、
(b)前記(a)工程の後、前記ドリフト層の上面に不純物を注入し、第2導電型のソース領域を形成する工程と、
(c)前記(b)工程の後、エッチングにより前記ソース領域の上面から前記ドリフト層の途中深さまで達するトレンチを形成する工程と、
(d)前記(c)工程の後、前記ソース領域上にマスクを形成し、前記ドリフト層内であって前記トレンチの側壁および底面に不純物を導入し、前記第2導電型のゲート領域を形成する工程と、
(e)前記(d)工程の後、前記トレンチの側壁および底面に窒素を導入する工程と、
(f)前記(e)工程の後、前記マスクを除去し、前記半導体基板上に前記トレンチを埋め込む層間絶縁膜を形成する工程と、
(g)前記(f)工程の後、前記ソース領域上において前記層間絶縁膜の一部を開口し、前記ソース領域の上面を露出させる工程と、
(h)前記(g)工程の後、前記ソース領域の上面および前記半導体基板の下面にそれぞれ電極を形成する工程と、
を有することを特徴とする半導体装置の製造方法。 - 前記(e)工程では、イオン注入によって前記トレンチの側壁および底面に前記窒素を導入し、前記トレンチの側壁および底面に前記窒素を不純物とする前記第1導電型の半導体領域を形成することを特徴とする請求項8記載の半導体装置の製造方法。
- 前記(e)工程では、前記半導体基板の主面に垂直な方向および前記半導体基板の主面に垂直な方向に対して斜めの角度からイオン注入を行うことで、前記トレンチの側壁および底面に前記半導体領域を形成することを特徴とする請求項9記載の半導体装置の製造方法。
- 前記(e)工程では、前記窒素を導入して形成した前記半導体領域により前記トレンチの側面および底面を覆い、前記ゲート領域と前記ソース領域との界面であるpn接合領域を前記トレンチの側壁において露出させないことを特徴とする請求項9記載の半導体装置の製造方法。
- 前記(a)工程では、NOまたはN2O雰囲気中でのアニールにより前記トレンチの側壁および底部に前記窒素を導入し、前記トレンチの側壁および底部にパッシベーション膜を形成することを特徴とする請求項8記載の半導体装置の製造方法。
- 前記(a)工程では、1200℃以上のNOまたはN2O雰囲気中でのアニールにより前記トレンチの側壁および底部に前記窒素を導入し、前記トレンチの側壁および底部にパッシベーション膜を形成することを特徴とする請求項12記載の半導体装置の製造方法。
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JP5692145B2 (ja) | 2012-04-17 | 2015-04-01 | 株式会社デンソー | 炭化珪素半導体装置の製造方法 |
JP2014131008A (ja) * | 2012-11-29 | 2014-07-10 | Fuji Electric Co Ltd | ワイドバンドギャップ半導体装置 |
JP6073719B2 (ja) * | 2013-03-21 | 2017-02-01 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法および半導体装置 |
JP6138619B2 (ja) * | 2013-07-30 | 2017-05-31 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法および半導体装置 |
CN112510080B (zh) * | 2020-11-30 | 2023-06-06 | 西安微电子技术研究所 | 一种抗单粒子高压mos场效应晶体管的辐射加固结构和制备方法 |
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US7279368B2 (en) * | 2005-03-04 | 2007-10-09 | Cree, Inc. | Method of manufacturing a vertical junction field effect transistor having an epitaxial gate |
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