CN112510080B - 一种抗单粒子高压mos场效应晶体管的辐射加固结构和制备方法 - Google Patents

一种抗单粒子高压mos场效应晶体管的辐射加固结构和制备方法 Download PDF

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CN112510080B
CN112510080B CN202011376406.1A CN202011376406A CN112510080B CN 112510080 B CN112510080 B CN 112510080B CN 202011376406 A CN202011376406 A CN 202011376406A CN 112510080 B CN112510080 B CN 112510080B
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王晨杰
王英民
刘存生
薛智民
孙有民
王小荷
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Xian Microelectronics Technology Institute
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Abstract

本发明公开了一种抗单粒子高压MOS场效应晶体管的辐射加固结构和制备方法,结构包括从下至上依次堆叠的衬底、缓冲外延层、PN结超结外延、垫氧层、层间介质层和金属层;PN结超结为周期性交替的P柱和N柱,N柱上方的垫氧层和层间介质层之间从下至上依次设置有JFET加固栅氧和栅极多晶;P柱上方的垫氧层中从下至上依次设置有P+体区和N+源区;P柱上方的层间介质层上设置有源极沟槽,源极沟槽穿过N+源区,源极沟槽的底部不超过P+体区,源极沟槽内通过离子注入形成P+深源,P+深源与P+体区和P柱相连接;源极沟槽内和层间介质层的表面上设置有金属过渡层,金属层设置在金属过渡层上。起到抑制单粒子烧毁效应的作用,有效消除单粒子栅穿现象的产生。

Description

一种抗单粒子高压MOS场效应晶体管的辐射加固结构和制备 方法
技术领域
本发明属于电子技术领域,具体属于一种抗单粒子高压MOS场效应晶体管的辐射加固结构和制备方法。
背景技术
超结(super-junction)单元结构利用周期性交替的P型和N型外延柱体(简称P柱和N柱)形成电荷平衡的全耗尽漂移区,使导通电阻和雪崩击穿关系由Ron,sp∝VB 2.5“硅极限”降低至Ron,sp∝VB 1.32~Ron,sp∝VB 1.03,利用该优良特性使MOS场效应晶体管在设计较高额定击穿电压(>250V)同时有较低的通态比导通电阻RDS(on),更加适合卫星、空间飞行器中大功率电源控制和管理系统的设计要求。
但是这种横向周期性交替PN结的电荷平衡全超结耗尽结构的抗单粒子效应能力不佳,对N型超结MOS场效应晶体管,粒子沿P柱入射诱发路径上空穴沿P柱耗尽区迅速向P+体区和N+源区漂移,导致P+体区易形成大量二次电子-空穴对诱发雪崩,造成源极附近发生热烧毁,即单粒子烧毁;粒子沿N柱入射诱发路径上空穴沿N柱耗尽区迅速向JFET区漂移并大量聚集在靠近漏极的栅氧界面处,易造成器件栅极氧化层击穿,即单粒子栅穿。
有文献报告对250V全超结外延结构MOS场效应晶体管,经地面重离子辐射模拟试验证实,暴露在特定的辐射线性能量传递值LET 53.1MeV·cm2/mg的Xe粒子辐射环境中,当器件按50%额定电压工作,在Xe粒子沿P柱入射剂量达105ion/cm2时P+体区电流迅速增加并诱发热烧毁;当器件按80%额定电压工作,在Xe粒子经过N柱且入射剂量达104ion/cm2时会突然发生栅击穿现象。
发明内容
为了解决现有技术中存在的问题,本发明提供一种抗单粒子高压MOS场效应晶体管的辐射加固结构和制备方法。起到抑制单粒子烧毁效应的作用,能够有效消除单粒子栅穿现象的产生。
为实现上述目的,本发明提供如下技术方案:
一种抗单粒子高压MOS场效应晶体管的辐射加固结构,包括从下至上依次堆叠的衬底、缓冲外延层、PN结超结外延、垫氧层、层间介质层和金属层;
所述PN结超结为周期性交替的P柱和N柱,所述N柱上方的垫氧层和层间介质层之间从下至上依次设置有JFET加固栅氧和栅极多晶;
所述P柱上方的垫氧层中从下至上依次设置有P+体区和N+源区;所述P柱上方的层间介质层上设置有源极沟槽,所述源极沟槽穿过N+源区,源极沟槽的底部不超过P+体区,源极沟槽内通过离子注入形成P+深源,P+深源与P+体区和P柱相连接;所述源极沟槽内和层间介质层的表面上设置有金属过渡层,金属层设置在金属过渡层上。
优选的,所述源极沟槽伸入P+体区的深度不超过P+体区深度的三分之二。
一种抗单粒子高压MOS场效应晶体管的辐射加固结构的制备方法,包括以下步骤,
步骤1,在衬底上生长缓冲外延层以及周期性交替的P柱和N柱形成的PN结超结外延;
步骤2,在PN结超结外延上生长垫氧层,对垫氧层进行离子注入形成P+体区,并在垫氧层上形成JFET加固栅氧;
步骤3,在JFET加固栅氧上形成栅极多晶,并在P+体区上进行离子注入形成N+源区;
步骤4,在形成N+源区的垫氧层上进行淀积形成层间介质层,在层间介质层上通过刻蚀形成源极沟槽,
步骤5,在源极沟槽内通过离子注入形成P+深源,P+深源连接P+体区和P柱的P埋层;
步骤6,在层间介质层的表面和源极沟槽中淀积金属过渡层;
步骤7,在金属过渡层上淀积金属层,完成高压MOS场效应晶体管的辐射加固结构。
优选的,步骤1中,所述N柱经过四次外延生长形成;P柱通过P型离子注入形成。
优选的,步骤2中,在PN结超结外延上生长垫氧层,在垫氧层上通过光刻定义P+体区的图形,采用硼离子分别进行P+体区的体内和表面注入,形成P+体区;
在垫氧层上的器件有源区进行磷离子注入形成JFET区,再通过光刻定义JFET区栅氧加固图形,通过隔离氧化湿法氧化工艺形成JFET加固栅氧。
优选的,通过砷离子注入形成N+源区,注入能量不超过120KeV;通过900℃的RTA快速热退火激活N+源区砷杂质。
优选的,步骤4中,通过高密度等离子化学气相淀积USG和BPSG形成层间介质层(13),通过等离子刻蚀形成源极沟槽,源极沟槽伸入P+体区的深度不超过P+体区深度的三分之二。
优选的,步骤5中,通过P+深源注入形成连结P+体区和P柱的P埋层,分别通过能量不低于200KeV的硼离子注入和能量不超过80KeV的BF2离子注入。
优选的,步骤6中,在源极沟槽中淀积金属过渡层,金属过渡层的厚度不超过90nm,通过850℃的RTA快速热退火形成欧姆接触。
优选的,步骤7中,在金属过渡层上通过淀积铝硅铜合金形成金属层,层间介质层表面的金属层厚度不小于4μm。
与现有技术相比,本发明具有以下有益的技术效果:
本发明一种抗单粒子高压MOS场效应晶体管的辐射加固结构,通过在P柱上方的层间介质层上设置有源极沟槽,能够有效调节P柱和P+体区连结处的P埋层浓度分布,调整P+体区的杂质形貌和浓度分布,提高P+体区寄生三极管形成正反馈的开启电压,起到抑制单粒子烧毁效应的作用;在周期性交叠P柱和N柱超结外延层下方增加N+缓冲外延层,调节漏极漂移区的电场分布,结合JFET区上方栅氧加固工艺,能够有效消除单粒子栅穿现象的产生。在电荷平衡的周期性交替N柱和P柱超结外延漂移区下方增加磷掺杂缓冲外延层,在实施过程中结合抗辐射栅氧化工艺和JFET区栅氧加固方法,降低抗单粒子对P柱和N柱宽度和均匀性的要求,能提高器件抗单粒子栅穿能力。
本发明一种抗单粒子高压MOS场效应晶体管的辐射加固结构的制备方法,由于栅极形成过程中采用了栅氧加固工艺和抗辐射工艺流程,其电离总剂量能力仍达到100k rad(Si);通过源极沟槽和P+体区扩展注入工艺能够有效调整P+体区和超结P柱间埋层的浓度分布和体区形貌,减少寄生三极管发生正反馈的几率,有较优的抗单粒子烧毁能力;通过半超结外延层结构和JFET栅氧加固工艺,减小了器件发生单粒子栅穿的可能性。地面重离子辐射试验表明,入射粒子LET值为75MeV·cm2/mg条件下,工作电压满额时无单粒子烧毁现象;对高压器件,工作电压不超过75%额定电压时,抗单粒子栅穿。此外,与对标的抗辐射平面栅MOS场效应晶体管相比,其通态比导通电阻RDS(on)减小了50%。
进一步的,通过采用多次外延和P型注入补偿方式形成超结外延设计的工艺方法,能够降低抗单粒子对P柱和N柱宽度和均匀性的工艺要求,增加了设计和工艺的冗余量。
附图说明
图1为本发明高压MOS场效应晶体管的辐射加固结构示意图;
图2为本发明实施例步骤1所述的半超结外延层结构;
图3为本发明实施例步骤4所述的P+体区注入和JFET区栅氧加固;
图4为本发明实施例步骤5所述的栅极多晶形成和N+源区注入;
图5为本发明实施例步骤6所述的层间介质层及源极沟槽形成;
图6为本发明实施例步骤7所述的P+深源注入和推结形成P+埋层;
图7为本发明实施例步骤8所述的金属过渡层;
图8为本发明实施例步骤9所述的金属层;
附图中:1为JFET加固栅氧;2为沟道和源极栅氧;3为栅极多晶;4为金属过渡层;5为LOCOS掩蔽膜;6为氮化硅和氧化硅膜掩蔽层;7为衬底;8为缓冲外延层;9为N柱;10为P柱;11为P+体区;12为N+源区;13为层间介质层;14为P+深源;15为金属层。
具体实施方式
下面结合具体的实施例对本发明做进一步的详细说明,所述是对本发明的解释而不是限定。
本发明涉及一种宇航应用的抗辐射高压MOS场效应晶体管单元结构和制造工艺方法,通过辐射加固工艺制作含半超结电荷平衡外延结构和源极沟槽结构的MOS场效应晶体管,其具有较低通态比导通电阻和较优抗单粒子能力。
本发明针对宇航应用超结型MOS场效应晶体管的抗单粒子效应需求,提出一种含对称源极沟槽的单元结构,该结构能够有效调节P柱和P+体区连结处的P埋层浓度分布,提高P+体区寄生三极管形成正反馈的开启电压,起到抑制单粒子烧毁效应的作用;在周期性交叠P柱和N柱超结外延层下方增加N+缓冲外延层,调节漏极漂移区的电场分布,结合JFET区上方栅氧加固工艺,能够有效消除单粒子栅穿现象的产生。
本发明提出的高压MOS场效应晶体管沟槽型半超结单元结构能有效提升抗单粒子能力;针对采用多次外延和P型注入补偿方式形成超结外延设计的工艺方法,本结构能够降低抗单粒子对P柱和N柱宽度和均匀性的工艺要求,增加了设计和工艺的冗余量。
针对高压超结MOS场效应晶体管抗单粒子效应的问题,发明了一种含源极沟槽的半超结单元结构,工作电压250V~600V,在电荷平衡的周期性交替N柱和P柱超结外延漂移区下方增加磷掺杂缓冲外延层,在实施过程中结合抗辐射栅氧化工艺和JFET区栅氧加固方法,降低抗单粒子对P柱和N柱宽度和均匀性的要求,能提高器件抗单粒子栅穿能力;在源极采用沟槽结构,更适合调整P+体区的杂质形貌和浓度分布,提高器件寄生三极管形成正反馈的开启电压,减小单粒子烧毁的风险。
实施例
实现高压MOS场效应晶体管半超结沟槽单元结构的工艺制作流程如下:
步骤1.在电阻率(0.002~0.005)Ω·cm的N型硅衬底7上生长缓冲外延层8、以及周期性交替的PN结超结外延,额定击穿电压是超结外延层和缓冲外延层8两者击穿电压之和。对此类半超结外延,有公式:
超结柱体:
临界电场:E0=VB/De;
E0=EC/2=6.18×105×VB-1/6(1+25.7f)
式中:VB为衬底电压,Ec为击穿电场。
几何因子:f=0.742×(Wp+Wn)/De,f取值范围0.1~0.5
缓冲外延:
浓度:Nb=1.9×1018×BV-1.4
厚度:Db=0.018×BV1.2
超结N柱9由四次外延生长形成,经过牺牲氧化通过P型离子注入补偿形成超结P柱10,每次外延后分别进行大于600KeV和小于100KeV的硼离子注入以获得较优的柱体形貌,根据设计和工艺仿真确认每次P柱10补偿注入的版图宽度Wp。
依据额定电压计算缓冲外延层8和和器件外延层的浓度和厚度,外延磷掺杂。
实施例中优选,采用电阻率(0.002~0.003)Ω·cm的N<100>硅片作为衬底7材料,按265V设计额定电压,根据公式计算,在缓冲外延层8分压60V时其厚度和浓度分别为:
Db≥4.0μm;ρb≥0.55Ω.cm。
超结外延N柱9的厚度和浓度分别为:
De≥16.0μm;ρb在(0.45~1.0)Ω.cm范围内。
超结外延层P柱10通过硼离子注入进行补偿,工艺条件为:
Figure BDA0002808309140000071
器件外延层厚度不小于5.0μm,浓度由设计电特性参数决定。
步骤2.通过场氧化、光刻、刻蚀和离子注入工艺定义并形成MOS场效应晶体管的终端柱体结构。终端采用柱体结构,设计额定电压265V,通过光刻定义厚度1000nm的场氧1作为掩蔽层,200KeV硼离子注入补偿P柱浓度,峰值浓度不低于8.0×1014cm-3
步骤3.通过场氧化、光刻和刻蚀工艺定义并形成MOS场效应晶体管的走线和器件有源区;走线沿场氧分布,场氧厚度不小于250nm,优选300nm。
步骤4.外延层表面生长厚度不大于70nm的垫氧层,对整个器件有源区进行磷离子的JFET注入,注入能量不低于150KeV,优选300KeV,注入剂量不超过1.5×1012cm-2;通过光刻定义P+体区11图形,采用硼离子分两次分别进行P+体区11的体内和表面注入,调整P+体区11形貌和浓度,注入剂量分别不超过5.0×1013cm-2和1.0×1013cm-2,体内注入能量不低于200KeV,表面注入能量不超过60KeV,并通过最高温度不低于1000℃推结工艺激活JFET区和P+体区11杂质;随后通过光刻定义漏极JFET区栅氧加固图形,通过LOCOS湿法氧化工艺形成加厚的JFET加固栅氧1,氧化最高温度不超过1000℃,栅氧厚度不小于150nm,氧化最高温度不超过1000℃;并进行最高温度不超过1000℃的N2O退火,LOCOS掩蔽层5由氮化硅和氧化硅膜构成,氧化层厚度200nm。
步骤5.湿法去除LOCOS掩蔽层5和牺牲氧化层,清洗后通过最高温度不超过900℃的湿氧工艺形成沟道和源极栅氧2,栅氧厚度不超过90nm;通过光刻定义、等离子刻蚀形成器件的栅极结构,栅极多晶3厚度不小于200nm;随后由砷离子注入形成N+源区12,注入能量不超过120KeV,其结深不超过1.5μm;;通过900℃的RTA快速热退火激活N+源区12砷杂质。
步骤6.通过高密度等离子化学气相淀积USG和BPSG形成层间介质层13,介质膜厚度不超过600nm。随后在层间介质层13上方通过低温LTO工艺依次淀积氮化硅和氧化硅膜做为后续源极沟槽刻蚀的掩蔽层,氮化硅膜厚度不超过80nm,氧化膜不超过200nm。通过光刻定义器件源极沟槽和走线栅极孔的图形,等离子刻蚀形成源极沟槽结构,源极沟槽伸入P+体区11的深度不超过P+体区11深度的三分之二。
实施例中优选,层间介质层13经过900℃推结致密后厚度550nm;源极沟槽宽度不超过2.0μm,深度不超过0.8μm,
步骤7.通过P+深源14注入形成连结P+体区11和超结P柱的P埋层,分别通过能量不低于200KeV的硼离子注入和能量不超过80KeV的BF2离子注入埋层,其杂质峰值不小于5.0×1014cm-3并分布在P埋层和P+体区边界。起到调整P+体区11浓度分布的作用,并一定程度改善沟道与漏端交叠处电场集中的问题;随后通过湿法腐蚀去除氮化硅和氧化硅膜掩蔽层6,清洗后通过最高温度不超过950℃的推结工艺激活P+深源14杂质并致密层间介质层。
步骤8.清洗后在源极沟槽中淀积金属过渡层4,金属过渡层4包括钛和氮化钛,淀积厚度不超过90nm,通过850℃的RTA快速热退火形成欧姆接触。
步骤9.淀积铝硅铜合金,表面铝硅铜合金厚度不小于4μm;通过光刻定义、湿法腐蚀铝硅铜合金、等离子刻蚀金属过渡层形成栅极和源极金属图形;随后进行420℃的合金退火形成金属层15,完成高压MOS场效应晶体管的辐射加固结构。
后续步骤与传统功率MOS场效应晶体管制造方法相同。
本发明提出的一种半超结沟槽型的高压MOS场效应晶体管辐射加固结构,对其栅极JFET区进行栅氧加固,源极采用沟槽结构以便于调整P+体区浓度分布,半外延结构由电荷平衡超结柱体和缓冲外延层共同构成,该单元结构是对常规超结型高压MOS场效应晶体管的改进,具备较好的抗单粒子能力。
由于栅极形成过程中采用了栅氧加固工艺和抗辐射工艺流程,其电离总剂量能力仍达到100k rad(Si);通过源极沟槽和P+体区扩展注入工艺能够有效调整P+体区和超结P柱间埋层的浓度分布和体区形貌,减少寄生三极管发生正反馈的几率,有较优的抗单粒子烧毁能力;通过半超结外延层结构和JFET栅氧加固工艺,减小了器件发生单粒子栅穿的可能性。地面重离子辐射试验表明,入射粒子LET值为75MeV·cm2/mg条件下,工作电压满额时无单粒子烧毁现象;对高压器件,工作电压不超过75%额定电压时,抗单粒子栅穿。此外,与对标的抗辐射平面栅MOS场效应晶体管相比,其通态比导通电阻RDS(on)减小了50%。
本发明使用的低温栅氧化、JFET栅氧加固等工艺方法和辐射加固工艺流程是基于0.5μm硅基MOS工艺实施的,与抗辐射平面栅MOS场效应晶体管的制造工艺有良好的兼容性,研制单位能够迅速开展抗辐射半超结高压MOS场效应晶体管的设计制造。
通过本实施例制作的N型250V半超结沟槽型MOS场效应晶体管,具有265V的额定雪崩击穿电压,其栅氧耐压大于85V,阈值电压辐射前后均在2.0V~4.0V范围内,漏源漏电流小于10μA,通态比导通电阻为500mΩ·mm-2,输出电流达75A;具备抗辐射能力:抗电离总剂量达到100k rad(Si),;入射粒子LET 75.0MeV·cm2/mg、器件栅源零偏置时抗单粒子烧毁,工作电压降至75%额定击穿时抗单粒子栅穿。

Claims (1)

1.一种抗单粒子高压MOS场效应晶体管的辐射加固结构的制备方法,其特征在于,包括以下步骤,
步骤1,在衬底(4)上生长缓冲外延层以及周期性交替的P柱和N柱形成的PN结超结外延;所述N柱(9)经过四次外延生长形成;P柱(10)通过P型离子注入形成;
步骤2,在PN结超结外延上生长垫氧层,进行离子注入形成P+体区(11),并在垫氧层上形成JFET加固栅氧(1);通过光刻定义P+体区(11)图形,采用硼离子分两次分别进行P+体区(11)的体内和表面注入,调整P+体区(11)形貌和浓度,注入剂量分别不超过5.0×1013cm-2和1.0×1013cm-2,体内注入能量不低于200KeV,表面注入能量不超过60KeV,并通过温度不低于1000℃推结工艺激活JFET区和P+体区(11)杂质;
在垫氧层上的器件有源区进行磷离子注入形成JFET区,磷离子注入能量不低于150KeV,注入剂量不超过1.5×1012cm-2;通过光刻定义JFET区栅氧加固图形,通过LOCOS湿法氧化工艺形成加厚的JFET加固栅氧(1),氧化温度不超过1000℃,栅氧厚度不小于150nm;并进行温度不超过1000℃的N2O退火;
步骤3,在JFET加固栅氧(1)上形成栅极多晶(3),并在P+体区(11)上进行离子注入形成N+源区(12);通过砷离子注入形成N+源区(12),注入能量不超过120KeV;通过900℃的RTA快速热退火激活N+源区(12)砷杂质;
步骤4,在形成N+源区(12)的垫氧层上进行淀积形成层间介质层(13),在层间介质层(13)上通过刻蚀形成源极沟槽,通过高密度等离子化学气相淀积USG和BPSG形成层间介质层(13),通过等离子刻蚀形成源极沟槽,源极沟槽伸入P+体区(11)的深度不超过P+体区(11)深度的三分之二;
步骤5,在源极沟槽内通过离子注入形成P+深源(14),通过P+深源(14)注入形成连结P+体区(11)和P柱(10)的P埋层,分别通过能量不低于200KeV的硼离子注入和能量不超过80KeV的BF2离子注入;
步骤6,在层间介质层(13)的表面和源极沟槽中淀积金属过渡层(4);金属过渡层(4)的厚度不超过90nm,通过850℃的RTA快速热退火形成欧姆接触;
步骤7,在金属过渡层(4)上淀积铝硅铜合金形成金属层(15),完成高压MOS场效应晶体管的辐射加固结构;层间介质层(13)表面的金属层(15)厚度不小于4μm。
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JP5607947B2 (ja) * 2010-02-17 2014-10-15 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
JP5560931B2 (ja) * 2010-06-14 2014-07-30 富士電機株式会社 超接合半導体装置の製造方法
WO2013128480A1 (en) * 2012-02-28 2013-09-06 Stmicroelectronics S.R.L. Vertical semiconductor device and manufacturing process of the same
JP2018186140A (ja) * 2017-04-24 2018-11-22 富士電機株式会社 炭化珪素半導体装置および炭化珪素半導体装置の製造方法

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