CN105140289A - N型ldmos器件及工艺方法 - Google Patents
N型ldmos器件及工艺方法 Download PDFInfo
- Publication number
- CN105140289A CN105140289A CN201510607048.3A CN201510607048A CN105140289A CN 105140289 A CN105140289 A CN 105140289A CN 201510607048 A CN201510607048 A CN 201510607048A CN 105140289 A CN105140289 A CN 105140289A
- Authority
- CN
- China
- Prior art keywords
- type
- ldmos device
- drift region
- trap
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 22
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 31
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 229920005591 polysilicon Polymers 0.000 claims description 28
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 14
- 238000000151 deposition Methods 0.000 claims description 9
- 238000005468 ion implantation Methods 0.000 claims description 9
- 238000001259 photo etching Methods 0.000 claims description 9
- 239000012535 impurity Substances 0.000 claims description 6
- 230000008021 deposition Effects 0.000 claims description 5
- 238000005530 etching Methods 0.000 claims description 5
- 229910052738 indium Inorganic materials 0.000 claims description 5
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 5
- 238000004519 manufacturing process Methods 0.000 claims description 5
- 239000000377 silicon dioxide Substances 0.000 claims description 5
- 239000002019 doping agent Substances 0.000 claims description 4
- 238000002347 injection Methods 0.000 claims description 4
- 239000007924 injection Substances 0.000 claims description 4
- 238000002955 isolation Methods 0.000 claims description 4
- 229910052751 metal Inorganic materials 0.000 claims description 4
- 239000002184 metal Substances 0.000 claims description 4
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 4
- 238000001312 dry etching Methods 0.000 claims description 3
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 claims description 3
- 239000007943 implant Substances 0.000 claims 1
- 239000000203 mixture Substances 0.000 claims 1
- 230000005684 electric field Effects 0.000 abstract description 4
- 230000015556 catabolic process Effects 0.000 abstract description 3
- 238000000407 epitaxy Methods 0.000 abstract 3
- 238000010586 diagram Methods 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000000137 annealing Methods 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
Abstract
本发明公开了一种N型LDMOS器件,在低阻衬底上具有N型埋层,埋层之上为N型外延,N型外延中具有相互抵靠的P阱和漂移区:所述漂移区中还具有N阱及STI结构;所述P阱中具有LDMOS器件的源区,所述漂移区的N阱中具有LDMOS器件的漏区;所述P阱中还具有重掺杂P型区,将P阱引出;N型外延表面具有LDMOS器件的栅氧化层及多晶硅栅极,多晶硅栅极两侧为侧墙;所述漂移区中的STI结构底部具有重掺杂的多晶硅。通过在漂移区STI底部增加P型掺杂的多晶硅层,在漂移区上方形成P型的辅助耗尽区,降低表面电场强度,使器件具有较低的导通电阻的同时具有较高的击穿电压。本发明还公开了所述N型LDMOS器件的工艺方法。
Description
技术领域
本发明涉及半导体器件制造领域,特别是指一种N型LDMOS器件,本发明还涉及所述N型LDMOS器件的工艺方法。
背景技术
由于具有耐高压,大电流驱动能力和极低功耗等特点,目前在电源管理电路中被广泛采用。在LDMOS(LaterallyDiffusedMetalOxideSemiconductor横向双扩散金属氧化物半导体)器件中,导通电阻是一个重要的指标。如图1所示,为传统的LDMOS器件的结构示意图,其源区及漏区是重掺杂N型区112,位于P阱107中,P阱107中还具有重掺杂P型区113将P型阱引出,位于N阱106中。在BCD(Bipolar-CMOS-DMOS)工艺中,DMOS虽然与CMOS集成在同一块芯片中,但由于高耐压和低导通电阻的要求,DMOS在本底区和漂移区的条件与CMOS现有的工艺条件共享的前提下,其导通电阻较高,往往无法满足开关管应用的要求。因此,为了制作高性能的LDMOS,需要采用各种方法优化器件的导通电阻。通常需要在器件的漂移区增加一道额外的N型注入,使器件有较低的导通电阻,而采用这种方法会降低器件的击穿电压。
发明内容
本发明所要解决的技术问题是提供一种N型LDMOS器件,具有较低的导通电阻及较高的击穿电压。
本发明还要解决的技术问题在于提供所述N型LDMOS器件的工艺方法。
为解决上述问题,本发明所述的N型LDMOS器件,在低阻衬底上具有N型埋层,埋层之上为N型外延,N型外延中具有相互抵靠的P阱和漂移区:
所述漂移区中还具有N阱及STI结构;
所述P阱中具有LDMOS器件的源区,所述漂移区的N阱中具有LDMOS器件的漏区;
所述P阱中还具有重掺杂P型区,将P阱引出;
N型外延表面具有LDMOS器件的栅氧化层及多晶硅栅极,多晶硅栅极两侧为侧墙;
所述漂移区中的STI结构底部具有重掺杂的多晶硅。
所述漂移区中STI底部的多晶硅,掺杂类型为P型。
本发明所述的N型LDMOS器件的工艺方法,包含如下的工艺步骤:
第1步,在低阻衬底上离子注入形成N型埋层;
第2步,在N型埋层上形成N型外延;
第3步,光刻及刻蚀在N型外延上形成STI沟槽,并在位于漂移区中的STI沟槽中淀积多晶硅及进行杂质注入;
第4步,在STI沟槽中填充氧化硅并研磨,形成浅槽隔离;
第5步,光刻打开阱区及漂移区,进行离子注入形成N阱、P阱及漂移区;
第6步,淀积氧化层及多晶硅,光刻及刻蚀形成栅氧化层及多晶硅栅极;
第7步,淀积氧化硅,刻蚀形成栅极侧墙;
第8步,进行离子注入形成源区、漏区以及将P阱引出的重掺杂P型区;
第9步,进行接触孔工艺,制作金属引线形成电极。
进一步地,所述第1步中,低阻衬底电阻率为0.007~0.013Ω·cm。
进一步地,所述第3步中,对STI沟槽中多晶硅注入杂质为铟。
进一步地,所述第7步中,淀积氧化硅厚度为干法刻蚀形成侧墙。
本发明所述的N型LDMOS器件,通过在漂移区STI底部增加多晶硅层并对其进行掺杂,在漂移区上方形成P型的辅助耗尽区,利用P型区域辅助耗尽,降低表面电场强度,避免导通电流增加时出现击穿电压下降的情况,使得器件保持较好特性的前提下,导通电流大幅增加,使器件有较低的导通电阻,同时保证器件导通状态下击穿电压达到应用要求。本发明所述的工艺方法,与BCD工艺兼容,可集成在BCD工艺中。
附图说明
图1是传统的LDMOS器件结构示意图;
图2~10是本发明N型LDMOS器件的制造工艺步骤示意图;
图11是本发明电场强度仿真对比图;
图12是是本发明N型LDMOS器件的制造工艺流程图。
附图标记说明
101是衬底,102是N型埋层,103是外延,104是多晶硅,105是STI(氧化硅),106是N阱,107是P阱,108是漂移区,109是栅氧化层,110是多晶硅栅极,111是侧墙,112是重掺杂N型区(源区,漏区),113是重掺杂P型区,114是接触孔,115是金属。
具体实施方式
本发明所述的N型LDMOS器件如图10所示,在电阻率为0.007~0.013Ω·cm的低阻衬底101上具有N型埋层102,埋层102之上为N型外延103,N型外延103中具有相互抵靠的P阱107和漂移区108;
所述漂移区108中还具有N阱106及STI隔离结构105;
所述P阱107中具有LDMOS器件的源区112,所述漂移区108的N阱106中具有LDMOS器件的漏区112(同为重掺杂N型区,采用同一附图标记);
所述P阱107中还具有重掺杂P型区113,将P阱107引出;P阱107作为LDMOS器件的沟道区;
N型外延103表面具有LDMOS器件的栅氧化层109及多晶硅栅极110,多晶硅栅极两侧为侧墙;
所述漂移区108中的STI结构105底部具有重掺杂的多晶硅104。
所述漂移区108中STI结构105底部的多晶硅104,掺杂类型为P型,优选地为铟。
上述LDMOS器件通过在漂移区STI底部增加P型辅助耗尽区,降低表面电场强度,经过仿真如图11所示,图11左上图为传统结构的剖面图,右上图为本发明结构的剖面图,左下图为器件击穿时沿剖面切线方向的电场分布,右下图为器件击穿时沿剖面切线方向的电压分布。从本发明结构与传统结构比较来看,本发明结构可使电场分布更加均匀,从而获得的击穿电压也较高。
本发明所述的N型LDMOS器件的工艺方法,包含如下的工艺步骤:
第1步,如图2所示,在电阻率为0.007~0.013Ω·cm的低阻衬底101上离子注入形成N型埋层102。
第2步,在N型埋层102上形成N型外延103。如图3所示。
第3步,光刻及刻蚀在N型外延上形成STI沟槽,并在位于漂移区中的STI沟槽中淀积多晶硅104及进行P型杂质注入,如图4所示;注入杂质为铟,由于后续要通过热氧化方法生长栅氧化层并在源漏注入后进行热退火,因此多晶硅层中P型杂质注入采用铟杂质,以防止其扩散过快压缩漂移区。
第4步,在STI沟槽中填充氧化硅并研磨,形成浅槽隔离结构。如图5所示。
第5步,光刻打开阱区及漂移区,进行离子注入形成N阱106、P阱107及漂移区108,如图6所示。
第6步,淀积氧化层及多晶硅,光刻及刻蚀形成栅氧化层109及多晶硅栅极110,如图7所示。
第7步,淀积厚度为的氧化硅,干法刻蚀形成栅极侧墙111,如图8所示。
第8步,进行离子注入形成源区、漏区以及将P阱引出的重掺杂P型区113,如图9所示。
第9步,进行接触孔114工艺,制作金属引线115形成电极。器件制作完成,如图10所示。
以上仅为本发明的优选实施例,并不用于限定本发明。对于本领域的技术人员来说,本发明可以有各种更改和变化。凡在本发明的精神和原则之内,所作的任何修改、等同替换、改进等,均应包含在本发明的保护范围之内。
Claims (6)
1.一种N型LDMOS器件,在低阻衬底上具有N型埋层,埋层之上为N型外延,N型外延中具有相互抵靠的P阱和漂移区:
所述漂移区中还具有N阱及STI结构;
所述P阱中具有LDMOS器件的源区,所述漂移区的N阱中具有LDMOS器件的漏区;
所述P阱中还具有重掺杂P型区,将P阱引出;
N型外延表面具有LDMOS器件的栅氧化层及多晶硅栅极,多晶硅栅极两侧为侧墙;
其特征在于:所述漂移区中的STI结构底部具有重掺杂的多晶硅。
2.如权利要求1所述的N型LDMOS器件,其特征在于:所述漂移区中STI底部的多晶硅,掺杂类型为P型。
3.制造如权利要求1所述的N型LDMOS器件的工艺方法,其特征在于:包含如下的工艺步骤:
第1步,在低阻衬底上离子注入形成N型埋层;
第2步,在N型埋层上形成N型外延;
第3步,光刻及刻蚀在N型外延上形成STI沟槽,并在位于漂移区中的STI沟槽中淀积多晶硅及进行杂质注入;。第4步,在STI沟槽中填充氧化硅并研磨,形成浅槽隔离;
第5步,光刻打开阱区及漂移区,进行离子注入形成N阱、P阱及漂移区;
第6步,淀积氧化层及多晶硅,光刻及刻蚀形成栅氧化层及多晶硅栅极;
第7步,淀积氧化硅,刻蚀形成栅极侧墙;
第8步,进行离子注入形成源区、漏区以及将P阱引出的重掺杂P型区;
第9步,进行接触孔工艺,制作金属引线形成电极。
4.如权利要求3所述的一种N型LDMOS器件的工艺方法,其特征在于:所述第1步中,低阻衬底电阻率为0.007~0.013Ω·cm。
5.如权利要求3所述的一种N型LDMOS器件的工艺方法,其特征在于:所述第3步中,淀积多晶硅的厚度为对STI沟槽中多晶硅注入杂质为P型,掺入杂质优选地为铟,掺杂能量需小于20kev,掺杂剂量为1e12~1e14/cm2。
6.如权利要求3所述的一种N型LDMOS器件的工艺方法,其特征在于:所述第7步中,淀积氧化硅厚度为干法刻蚀形成侧墙。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201510607048.3A CN105140289A (zh) | 2015-09-22 | 2015-09-22 | N型ldmos器件及工艺方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201510607048.3A CN105140289A (zh) | 2015-09-22 | 2015-09-22 | N型ldmos器件及工艺方法 |
Publications (1)
Publication Number | Publication Date |
---|---|
CN105140289A true CN105140289A (zh) | 2015-12-09 |
Family
ID=54725577
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201510607048.3A Pending CN105140289A (zh) | 2015-09-22 | 2015-09-22 | N型ldmos器件及工艺方法 |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN105140289A (zh) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN106298935A (zh) * | 2016-08-16 | 2017-01-04 | 上海华虹宏力半导体制造有限公司 | Ldmos器件及其制造方法 |
CN106449412A (zh) * | 2016-09-30 | 2017-02-22 | 上海华虹宏力半导体制造有限公司 | 开关n型ldmos器件的工艺方法 |
CN111261722A (zh) * | 2020-01-21 | 2020-06-09 | 东南大学 | 一种集成电容的低反向恢复电荷的横向二极管 |
CN112736078A (zh) * | 2019-10-28 | 2021-04-30 | 上海先进半导体制造有限公司 | 基于bcd工艺的pnp型高压esd器件及ldmos |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011049457A (ja) * | 2009-08-28 | 2011-03-10 | Tokai Rika Co Ltd | 高耐圧半導体装置及びその製造方法 |
CN103839998A (zh) * | 2012-11-27 | 2014-06-04 | 上海华虹宏力半导体制造有限公司 | Ldmos器件及其制造方法 |
CN104282563A (zh) * | 2013-07-03 | 2015-01-14 | 中芯国际集成电路制造(上海)有限公司 | Ldmos器件及其形成方法 |
-
2015
- 2015-09-22 CN CN201510607048.3A patent/CN105140289A/zh active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011049457A (ja) * | 2009-08-28 | 2011-03-10 | Tokai Rika Co Ltd | 高耐圧半導体装置及びその製造方法 |
CN103839998A (zh) * | 2012-11-27 | 2014-06-04 | 上海华虹宏力半导体制造有限公司 | Ldmos器件及其制造方法 |
CN104282563A (zh) * | 2013-07-03 | 2015-01-14 | 中芯国际集成电路制造(上海)有限公司 | Ldmos器件及其形成方法 |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN106298935A (zh) * | 2016-08-16 | 2017-01-04 | 上海华虹宏力半导体制造有限公司 | Ldmos器件及其制造方法 |
CN106298935B (zh) * | 2016-08-16 | 2019-08-13 | 上海华虹宏力半导体制造有限公司 | Ldmos器件及其制造方法 |
CN106449412A (zh) * | 2016-09-30 | 2017-02-22 | 上海华虹宏力半导体制造有限公司 | 开关n型ldmos器件的工艺方法 |
CN112736078A (zh) * | 2019-10-28 | 2021-04-30 | 上海先进半导体制造有限公司 | 基于bcd工艺的pnp型高压esd器件及ldmos |
CN111261722A (zh) * | 2020-01-21 | 2020-06-09 | 东南大学 | 一种集成电容的低反向恢复电荷的横向二极管 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN104517852B (zh) | 横向漏极金属氧化物半导体元件及其制造方法 | |
CN102769037B (zh) | 减少表面电场的结构及横向扩散金氧半导体元件 | |
US8610206B2 (en) | Split-gate lateral diffused metal oxide semiconductor device | |
US10263070B2 (en) | Method of manufacturing LV/MV super junction trench power MOSFETs | |
US9825164B2 (en) | Silicon carbide semiconductor device and manufacturing method for same | |
US8445958B2 (en) | Power semiconductor device with trench bottom polysilicon and fabrication method thereof | |
CN102386211B (zh) | Ldmos器件及其制造方法 | |
JP2013258327A (ja) | 半導体装置及びその製造方法 | |
CN102376762B (zh) | 超级结ldmos器件及制造方法 | |
CN105070759A (zh) | Nldmos器件及其制造方法 | |
CN108242467B (zh) | Ldmos器件及其制作方法 | |
CN104716177A (zh) | 一种改善漏电的射频ldmos器件及其制造方法 | |
CN104377244A (zh) | 一种降低ldmos导通电阻的器件结构 | |
CN104659090B (zh) | Ldmos器件及制造方法 | |
CN105140289A (zh) | N型ldmos器件及工艺方法 | |
CN102751332A (zh) | 耗尽型功率半导体器件及其制造方法 | |
CN104659091A (zh) | Ldmos器件及制造方法 | |
CN104658913A (zh) | Nldmos的制造方法 | |
KR20110078621A (ko) | 반도체 소자 및 그 제조 방법 | |
JP2021506118A (ja) | Ldmosデバイス及びその製造方法 | |
CN115274859B (zh) | Ldmos晶体管及其制造方法 | |
CN104409500B (zh) | 射频ldmos及其制作方法 | |
CN102694020B (zh) | 一种半导体装置 | |
CN104821334A (zh) | N型ldmos器件及工艺方法 | |
KR20110078861A (ko) | 수평형 디모스 트랜지스터 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
WD01 | Invention patent application deemed withdrawn after publication | ||
WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20151209 |