CN103839998A - Ldmos器件及其制造方法 - Google Patents
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Abstract
本申请公开了一种LDMOS器件,包括第一n阱,作为器件的漂移区;在第一n阱中具有p阱和第二n阱,所述p阱作为器件的沟道所在区域;在第一n阱之上具有栅氧化层和栅极;在p阱中具有n型掺杂区作为器件的源极;在p阱底部具有第一p型掺杂区,所述第一p型掺杂区还延伸到栅氧化层的正下方;在第二n阱中具有第三p型掺杂区作为器件的漏极。或者,将上述各部分的掺杂类型变为相反。本申请还公开了所述LDMOS器件的制造方法。本申请LDMOS器件具有较小的导通电阻,同时又基本不会降低击穿电压。其制造方法仅采用CMOS工艺,因而可集成于BCD工艺之中,并且不会增加制造成本。
Description
技术领域
本申请涉及一种半导体集成电路器件,特别是涉及一种LDMOS器件。
背景技术
DMOS器件由于具有耐高压、大电流驱动能力和极低功耗等特点,目前在电源管理电路中被广泛采用。DMOS器件主要分为两种类型:VDMOS(垂直扩散MOS晶体管)器件和LDMOS(横向扩散MOS晶体管)器件。
BCD工艺是指能够在同一芯片上制作双极晶体管(Bipolar)、CMOS器件和DMOS器件的工艺。采用BCD工艺制造DMOS器件时,由于与CMOS器件共享工艺条件,制造出的DMOS器件的导通电阻较高,往往无法满足功率开关管应用的要求。
为了降低以BCD工艺制造的DMOS器件的导通电阻,一种现有的做法是在DMOS器件的漂移区增加一道额外的离子注入(例如,n型LDMOS器件在漂移区增加额外的n型杂质注入)。但这种方法会造成器件的击穿电压降低。
请参阅图6,这是采用纯CMOS工艺(因而可集成于BCD工艺之中)制造的n型LDMOS器件。在p型衬底101之上具有n型埋层102,再之上具有第一n阱103,第一n阱103的底部与n型埋层102相接触。在第一n阱103中具有隔离结构104、第二n阱105、p阱106。第二n阱105的深度大致与隔离结构104相同。p阱106的深度显著地大于隔离结构104。在p型衬底101之上具有栅氧化层108,在栅氧化层108之上具有多晶硅栅极109,在栅氧化层108和多晶硅栅极109的两侧具有侧墙110。栅氧化层108与多晶硅栅极109的部分下方为p阱106,还有部分的下方为第一n阱103。在p阱106中具有n型掺杂区111和第二p型掺杂区112。在第二n阱105中具有第二n型掺杂区115。n型掺杂区111、第二p型掺杂区112、第二n型掺杂区115之上都具有接触孔电极121,并由金属引线122将接触孔电极121引出。
图6所示的n型LDMOS器件中,p阱106作为沟道所在区域,第一n阱103作为n型漂移区,它们均可采用CMOS工艺中的阱工艺。n型掺杂区111作为源极,第二p型掺杂区112作为p阱106的引出端,第二n型掺杂区115作为漏极,它们均可以采用CMOS工艺中的源漏注入工艺。
请参阅图7,这是在漂移区增加额外的离子注入所制造的n型LDMOS器件。在图6所示的n型LDMOS器件的基础上仅有如下区别:在n型漂移区103中增加了额外的n型离子注入区116,其从栅氧化层108的下方延伸到第二n阱105的下方。
发明内容
本申请所要解决的技术问题是提供一种LDMOS器件,可以采用BCD工艺制造。所述LDMOS器件拥有较小的导通电阻,同时又不会降低击穿电压。为此,本申请还要提供所述LDMOS器件的制造方法。
为解决上述技术问题,本申请LDMOS器件包括第一n阱,作为器件的漂移区;在第一n阱中具有p阱和第二n阱,所述p阱作为器件的沟道所在区域;在第一n阱之上具有栅氧化层和栅极;在p阱中具有n型掺杂区作为器件的源极;在p阱底部具有第一p型掺杂区,所述第一p型掺杂区还延伸到栅氧化层的正下方;在第二n阱中具有第三p型掺杂区作为器件的漏极;
或者,将上述各部分结构的掺杂类型变为相反。
上述LDMOS器件的制造方法包括如下步骤:
第1步,在p型衬底上形成n型埋层;
第2步,在n型埋层上外延生长一层外延层;
第3步,在外延层中注入n型杂质形成第一n阱,其底部与n型埋层相接触;
第4步,在第一n阱中形成多个隔离结构;
第5步,在第一n阱中注入n型杂质、p型杂质,分别形成第二n阱、p阱,分别作为n型LDMOS器件的漂移区、沟道所在区域;
第6步,在p阱底部形成第一p型掺杂区,其还横向延伸到栅氧化层正下方;
第7步,在第一n阱上形成栅氧化层和多晶硅栅极,它们部分落在p阱上方,还部分地相隔第一n阱而落在第一p型掺杂区的上方;
第8步,在栅氧化层和多晶硅栅极的两侧形成侧墙;
第9步,在p阱中形成n型掺杂区作为n型LDMOS器件的源极,在p阱和第二n阱还形成第二p型掺杂区、第三p型掺杂区分别作为n型LDMOS器件的p阱引出端、漏极;
第10步,以接触孔电极将n型掺杂区、第二p型掺杂区、第三p型掺杂区引出;
或者,将上述各部分结构的掺杂类型变为相反。
本申请LDMOS器件具有较小的导通电阻,同时又基本不会降低击穿电压。其制造方法仅采用CMOS工艺,因而可集成于BCD工艺之中,并且不会增加制造成本。
附图说明
图1是本申请n型LDMOS器件的结构示意图;
图2a至图2i本申请n型LDMOS器件的制造方法的各步骤示意图;
图3a、图3b、图3c分别是纯CMOS工艺制造的n型LDMOS器件、在漂移区增加离子注入制造的n型LDMOS器件、本申请n型LDMOS器件在相同位置测得的载流子分布图;
图4a、图4b、图4c分别是纯CMOS工艺制造的n型LDMOS器件、在漂移区增加离子注入制造的n型LDMOS器件、本申请n型LDMOS器件的耗尽区仿真示意图;
图5a、图5b均是纯CMOS工艺制造的n型LDMOS器件、在漂移区增加离子注入制造的n型LDMOS器件、本申请n型LDMOS器件的导通电流与器件电压之间的变化关系图;
图6是现有的一种n型LDMOS器件的结构示意图;
图7是现有的另一种n型LDMOS器件(在漂移区具有额外的离子注入区)的结构示意图。
图中附图标记说明:
101为p型衬底;102为n型埋层;103为第一n阱;104为隔离结构;105为第二n阱;106为p阱;107为第一p型掺杂区;108为栅氧化层;109为多晶硅栅极;110为侧墙;111为n型掺杂区;112为第二p型掺杂区;113为第三p型掺杂区;114为外延层;115为第二n型掺杂区;116为n型离子注入区;121为接触孔电极;122为引线。
具体实施方式
请参阅图1,这是本申请LDMOS器件的一个实施例,以n型LDMOS器件为例。在p型衬底101之上具有n型埋层102,再之上具有第一n阱103,第一n阱103的底部与n型埋层102相接触。在第一n阱103中具有隔离结构104、第二n阱105、p阱106和第一p型掺杂区107。第二n阱105位于第三隔离结构104c和第四隔离结构104d之间,并且第二n阱105的深度大致与隔离结构104相同。P阱106在部分的第一隔离结构104a的下方、以及第一隔离结构104a与第二隔离结构104b之间、以及全部的第二隔离结构104b的下方、以及部分的第二隔离结构104b与第三隔离结构104c之间。并且,p阱106的深度显著地大于隔离结构104,p阱106的底部与第一p型掺杂区107相接触。所述第一p型掺杂区107除了在p阱106的底部,还横向延伸到栅氧化层108的正下方。在p型衬底101之上具有栅氧化层108,在栅氧化层108之上具有多晶硅栅极109,在栅氧化层108和多晶硅栅极109的两侧具有侧墙110。栅氧化层108与多晶硅栅极109在第二隔离结构104b与第三隔离结构104c之间。并且,栅氧化层108与多晶硅栅极109的部分下方为p阱106,还有部分的下方依次为第一n阱103和第一p型掺杂区107。在p阱106中具有n型掺杂区111和第二p型掺杂区112。n型掺杂区111在第二隔离结构104b与多晶硅栅极109之间。第二p型掺杂区112在第一隔离结构104a与第二隔离结构104b之间。在第二n阱105中具有第三p型掺杂区113。n型掺杂区111、第二p型掺杂区112、第三p型掺杂区113之上都具有接触孔电极121,并由金属引线122将接触孔电极121引出。
图1所示的n型LDMOS器件中,p阱106作为沟道所在区域,第一n阱103作为n型漂移区,它们均可采用CMOS工艺中的阱工艺。n型掺杂区111作为源极,第二p型掺杂区112作为p阱106的引出端,第三p型掺杂区113作为漏极,它们均可以采用CMOS工艺中的源漏注入工艺。所述漂移区为轻掺杂,以提高第一n阱103与p阱106之间的PN结击穿电压。
如果是p型LDMOS器件,只需将上述各部分结构的掺杂类型变为相反即可。
与现有的n型LDMOS器件相比,本申请在结构上具有如下特点:
其一,将漏极113由传统的n型重掺杂改为p型重掺杂,这样p型漏极113便与其下方的第二n阱105形成PN结。这可以增加空穴载流子,降低器件的导通电阻。
请参阅图3c,这是本申请n型LDMOS器件在图1所示的X轴测得的载流子分布情况。横轴为X轴的坐标,纵轴为log(载流子数量)。图3a、图3b分别是现有的以纯CMOS工艺制造的n型LDMOS器件、现有的在漂移区增加离子注入以降低导通电阻的n型LDMOS器件在相同位置测得的载流子分布情况。显然,本申请的载流子分布情况与图3b大体相同,而远大于图3a。
如果单纯调整漏极113的注入类型,虽然可以降低器件的导通电阻,但是器件的击穿电压也会大幅降低。有仿真实验表明,击穿电压由53V降低到32V。
其二,新增了与p阱106的底部相接触的第一p型掺杂区107,其在p阱106底部,并在栅氧化层108的下方,用来降低器件表面电场强度,增加耗尽区宽度,从而提高器件的击穿电压。
请参阅图4c,这是本申请n型LDMOS器件的耗尽区的仿真示意图。斜线填充区域表示耗尽区,虚线表示PN结的分界线。图4a、图4b则是现有的以纯CMOS工艺制造的n型LDMOS器件、现有的在漂移区增加离子注入以降低导通电阻的n型LDMOS器件的耗尽区的仿真示意图。显然,本申请的耗尽区更宽。图4a~图4c中,由斜线填充区域所包围的“等高线”区域表示碰撞电离强度的变化,被包围在越里面,碰撞电离越强。比较后可发现本申请中碰撞电离最强的点从第三隔离结构104c的左下角转向下方,因而可以提升器件的击穿电压。
同时采用上述两种技术手段,本申请n型LDMOS器件便在降低导通电阻的同时,维持击穿电压基本不变。本申请n型LDMOS器件便在最重要的两项指标——较低的导通电阻和较高的击穿电压——之间取得了较好的平衡,可以满足功率开关器件和模拟器件的应用要求。
请参阅图5a,这是三种n型LDMOS器件的导通电流与器件电压的变化关系图。横轴为器件电压,单位为V。纵轴为导通电流,单位为A。显然,在相同的器件电压条件下,本申请n型LDMOS器件的导通电流(实线)与现有的在漂移区增加离子注入以降低导通电阻的n型LDMOS器件的导通电流(点划线)大体相同,而远大于现有的以纯CMOS工艺制造的n型LDMOS器件的导通电流(虚线)。而相同的器件电压条件下,导通电流越大,说明导通电阻越小。
请参阅图5b,这是三种n型LDMOS器件的导通电流与器件电压的变化关系图,其中表示出了器件的击穿电压。横轴为器件电压,单位为V。纵轴为导通电流,单位为A。显然,本申请n型LDMOS器件的击穿电压(实线)略小于现有的以纯CMOS工艺制造的n型LDMOS器件的击穿电压(虚线),而远大于现有的在漂移区增加离子注入以降低导通电阻的n型LDMOS器件的击穿电压(点划线)。
本申请n型LDMOS器件的制造方法包括如下步骤:
第1步,请参阅图2a,在p型衬底101的上表面注入n型杂质形成n型埋层102。所述p型衬底101优选为电阻率在0.007~0.013Ω·cm之间的低阻衬底。所述n型埋层102优选为重掺杂。
第2步,请参阅图2b,在n型埋层102的上表面采用外延工艺淀积一层外延层114。
第3步,请参阅图2c,在外延层114中注入n型杂质形成第一n阱103,第一n阱103的底部与n型埋层102相接触。
第4步,请参阅图2d,在第一n阱103中形成多个隔离结构104。例如,可采用浅槽隔离(STI)工艺,包括光刻定义沟槽区域、刻蚀出沟槽、以氧化物填充沟槽、将填充物上表面研磨平整等。
第5步,请参阅图2e,在第一n阱103中分别注入n型杂质、p型杂质,分别形成第二n阱105、p阱106,分别作为n型LDMOS器件的漂移区、沟道所在区域。所述第二n阱105的深度显著地大于隔离结构104,并且第二n阱105的范围包括第一隔离结构104a下方的部分区域、第一隔离结构104a与第二隔离结构104b之间的全部区域、第二隔离结构104b正下方的全部区域、以及第二隔离结构104b与第三隔离结构104c之间的部分区域。所述第二n阱105优选为轻掺杂。所述p阱106的深度大致与隔离结构104相同,并且p阱106的范围局限在第三隔离结构104c与第四隔离结构104d之间的区域。
第6步,请参阅图2f,在第一n阱103中靠近p阱106底部的区域、和/或p阱106的底部区域注入p型杂质形成第一p型掺杂区107。所述第一p型掺杂区107与p阱106的底部相接触。所述第一p型掺杂区107除了在p阱106的底部且相互接触,还横向延伸到部分栅氧化层108的正下方。例如,p型杂质采用硼,离子注入的能量为100~2000keV,离子注入的剂量为1*1011~1*1016原子每平方厘米。
第7步,请参阅图2g,在第一n阱103之上采用热氧生长出一层二氧化硅,在其上淀积一层多晶硅,以光刻和刻蚀工艺对所述多晶硅层和氧化硅层进行刻蚀形成栅氧化层108和多晶硅栅极109。所述栅氧化层108和多晶硅栅极109部分地落在p阱106的上方,还部分地相隔第一n阱103而落在第一p型掺杂区107的上方。
第9步,请参阅图2i,在p阱106中注入n型杂质形成n型掺杂区111。所述n型掺杂区111作为n型LDMOS器件的源极,其在第二隔离结构104b与多晶硅栅极109之间。还分别在p阱106和第二n阱105中注入p型杂质(同时或先后),分别形成第二p型掺杂区112、第三p型掺杂区113。所述第二p型掺杂区112作为n型LDMOS器件的p阱引出端,其在第一隔离结构104a与第二隔离结构104b之间。所述第三p型掺杂区113作为n型LDMOS器件的漏极,其在第三隔离结构104c与第四隔离结构104d之间。该步骤优选采用源漏注入工艺。所形成的源极111、p阱引出端112均相隔p阱106而落在第一p型掺杂区107的上方。
虽然图2i中显示p阱引出端112在第一p型掺杂区107的上方,然而这并不是必须的。第一p型掺杂区107只需保证与p阱106的底部相连,并在部分的栅氧化层108的下方即可。
第10步,请参阅图1,在整个硅片上形成层间介质(未图示),并在n型掺杂区111、第二p型掺杂区112、第三p型掺杂区113上方形成接触孔,在接触孔中填充金属形成电极121,例如采用钨塞工艺,并以金属线122将接触孔电极121引出。
如果是p型LDMOS器件,只需将上述各部分结构的掺杂类型变为相反即可。
上述LDMOS器件的制造方法完全采用了现有的CMOS制造工艺,因而可以集成在BCD工艺中。所有制造步骤与现有的制造步骤相比,没有增加额外的光刻掩膜版,采用的也都是现有的离子注入工艺,这不仅保持了制造工艺的良好兼容性,而且使得制造成本不会提升。
以上仅为本申请的优选实施例,并不用于限定本申请。对于本领域的技术人员来说,本申请可以有各种更改和变化。凡在本申请的精神和原则之内,所作的任何修改、等同替换、改进等,均应包含在本申请的保护范围之内。
Claims (5)
1.一种LDMOS器件,其特征是,包括第一n阱,作为器件的漂移区;在第一n阱中具有p阱和第二n阱,所述p阱作为器件的沟道所在区域;在第一n阱之上具有栅氧化层和栅极;在p阱中具有n型掺杂区作为器件的源极;在p阱底部具有第一p型掺杂区,所述第一p型掺杂区还延伸到栅氧化层的正下方;在第二n阱中具有第三p型掺杂区作为器件的漏极;
或者,将上述各部分的掺杂类型变为相反。
2.根据权利要求1所述的LDMOS器件,其特征是,所述第一p型掺杂区既与p阱底部相连;所述第一p型掺杂区还在栅氧化层的下方,两者之间相隔第一n阱。
3.一种LDMOS器件的制造方法,其特征是,包括如下步骤:
第1步,在p型衬底上形成n型埋层;
第2步,在n型埋层上外延生长一层外延层;
第3步,在外延层中注入n型杂质形成第一n阱,其底部与n型埋层相接触;
第4步,在第一n阱中形成多个隔离结构;
第5步,在第一n阱中注入n型杂质、p型杂质,分别形成第二n阱、p阱,分别作为n型LDMOS器件的漂移区、沟道所在区域;
第6步,在p阱底部形成第一p型掺杂区,其还横向延伸到栅氧化层正下方;
第7步,在第一n阱上形成栅氧化层和多晶硅栅极,它们部分落在p阱上方,还部分地相隔第一n阱而落在第一p型掺杂区的上方;
第8步,在栅氧化层和多晶硅栅极的两侧形成侧墙;
第9步,在p阱中形成n型掺杂区作为n型LDMOS器件的源极,在p阱和第二n阱还形成第二p型掺杂区、第三p型掺杂区分别作为n型LDMOS器件的p阱引出端、漏极;
第10步,以接触孔电极将n型掺杂区、第二p型掺杂区、第三p型掺杂区引出;
或者,将上述各部分的掺杂类型变为相反。
4.根据权利要求3所述的LDMOS器件的制造方法,其特征是,所述方法第1步中,p型衬底的电阻率在0.007~0.013Ω·cm之间。
5.根据权利要求3所述的LDMOS器件的制造方法,其特征是,所述方法第6步中,p型杂质采用硼,离子注入的能量为100~2000keV,离子注入的剂量为1*1011~1*1016原子每平方厘米。
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