CN111509044A - 半导体结构及其形成方法 - Google Patents

半导体结构及其形成方法 Download PDF

Info

Publication number
CN111509044A
CN111509044A CN201910097564.4A CN201910097564A CN111509044A CN 111509044 A CN111509044 A CN 111509044A CN 201910097564 A CN201910097564 A CN 201910097564A CN 111509044 A CN111509044 A CN 111509044A
Authority
CN
China
Prior art keywords
region
doping
doped
ions
isolation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201910097564.4A
Other languages
English (en)
Other versions
CN111509044B (zh
Inventor
李茂�
郑大燮
陈德艳
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
Original Assignee
Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Manufacturing International Shanghai Corp, Semiconductor Manufacturing International Beijing Corp filed Critical Semiconductor Manufacturing International Shanghai Corp
Priority to CN201910097564.4A priority Critical patent/CN111509044B/zh
Priority to US16/745,601 priority patent/US11239358B2/en
Publication of CN111509044A publication Critical patent/CN111509044A/zh
Application granted granted Critical
Publication of CN111509044B publication Critical patent/CN111509044B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/761—PN junctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

一种半导体结构及其形成方法，半导体结构的形成方法包括：提供基底，基底内具有邻接的第一掺杂区和第二掺杂区，第一掺杂区内具有第一掺杂离子，第二掺杂区内具有第二掺杂离子，第二掺杂离子与第一掺杂离子导电类型相反；在第二掺杂区内形成若干个相互分立的第一隔离结构；在相邻第一隔离结构之间以及第一隔离结构底部的第二掺杂区内形成第三掺杂区，第三掺杂区内具有第三掺杂离子，第三掺杂离子与第二掺杂离子导电类型相反；在部分第一掺杂区、第二掺杂区和第一隔离结构表面形成栅极结构；在栅极结构一侧的第一掺杂区内形成源区；在栅极结构另一侧的第二掺杂区内形成漏区，部分所第一隔离结构位于栅极结构与漏区之间。所形成的器件性能较好。

Description

半导体结构及其形成方法
技术领域
本发明涉及半导体制造领域，尤其涉及一种半导体结构及其形成方法。
背景技术
横向双扩散金属氧化物半导体晶体管(lateral double diffusion MOS，LDMOS)，由于具备高压击穿电压，与互补金属氧化物半导体(CMOS)工艺兼容的特性，被广泛应用于功率器件中。与传统MOS晶体管相比，传统MOS器件中的源极区域和漏极区域相对于栅极对称；而横向双扩散金属氧化物半导体晶体管中的漏极区域比源极更远离栅极，在漏极区域与栅极之间有一个较长的轻掺杂区域，被称为漂移区。横向双扩散金属氧化物半导体晶体管在源漏接高压时，通过漂移区来承受较高的电压降，获得高击穿电压的目的。横向双扩散金属氧化物半导体晶体管除了需要耐高压外，还需要低的开态电阻和高安全工作范围。
然而，现有技术形成的横向双扩散金属氧化物半导体晶体难以同时满足上述性能要求。
发明内容
本发明解决的技术问题是提供一种半导体结构及其形成方法，以提高半导体器件的性能。
为解决上述技术问题，本发明提供一种半导体结构的形成方法，包括：提供基底，所述基底内具有邻接的第一掺杂区和第二掺杂区，所述第一掺杂区内具有第一掺杂离子，所述第二掺杂区内具有第二掺杂离子，所述第二掺杂离子与第一掺杂离子的导电类型相反；在所述第二掺杂区内形成若干个相互分立的第一隔离结构；在相邻所述第一隔离结构之间以及第一隔离结构底部的第二掺杂区内形成第三掺杂区，所述第三掺杂区内具有第三掺杂离子，所述第三掺杂离子的导电类型与第二掺杂离子的导电类型相反；在部分所述第一掺杂区、第二掺杂区和第一隔离结构表面形成栅极结构；在栅极结构一侧的第一掺杂区内形成源区；在栅极结构另一侧的第二掺杂区内形成漏区，部分所述第一隔离结构位于栅极结构与漏区之间。
可选的，所述第一隔离结构的形成方法包括：在所述基底、第一掺杂区和第二掺杂区顶部形成第一掩膜层，所述第一掩膜层内具有若干个暴露出第二掺杂区顶部表面的第一掩膜开口；以所述第一掩膜开口为掩膜，刻蚀所述第二掺杂区，在所述第二掺杂区内形成第一隔离开口；在所述第一隔离开口内形成第一隔离结构，所述第一隔离结构充满第一隔离开口。
可选的，所述第一隔离结构的材料包括氧化硅或者氮氧化硅。
可选的，所述漏区上的电压为：500伏特～700伏特。
可选的，沿源区和漏区连线方向上，若干个相互分离的第一隔离结构的尺寸之和为：40微米～50微米；沿源区和漏区连线方向上，所述第一隔离结构的个数为：3个～4个。
可选的，所述第一隔离结构的厚度为：360纳米～400纳米。
可选的，所述第二掺杂离子的掺杂浓度为：2e15原子数/每平方厘米～3e15原子数/每平方厘米。
相应的，本发明还提供一种半导体结构，包括：基底，所述基底内具有邻接的第一掺杂区和第二掺杂区，所述第一掺杂区内具有第一掺杂离子，所述第二掺杂区内具有第二掺杂离子，所述第二掺杂离子与第一掺杂离子的导电类型相反；位于所述第二掺杂区内的若干个相互分立的第一隔离结构；位于相邻所述第一隔离结构之间以及第一隔离结构底部第二掺杂区内的第三掺杂区，所述第三掺杂区内具有第三掺杂离子，所述第三掺杂离子与第二掺杂离子的导电类型相反；位于部分所述第一掺杂区、第二掺杂区和第一隔离结构表面的栅极结构；位于所述栅极结构一侧第一掺杂区内的源区；位于所述栅极结构另一侧第二掺杂区内的漏区，部分所述第一隔离结构位于栅极结构与漏区之间。
可选的，所述第一隔离结构的材料包括氧化硅。
可选的，所述漏区上的电压为：500伏特～700伏特。
可选的，沿源区和漏区连线方向上，若干个相互分离的第一隔离结构的尺寸之和为：40微米～50微米；沿源区和漏区连线方向上，所述第一隔离结构的个数为：3个～4个。
可选的，所述第一隔离结构的厚度为：360纳米～400纳米。
可选的，所述第二掺杂离子的掺杂浓度为：2e15原子数/每平方厘米～3e15原子数/每平方厘米。
与现有技术相比，本发明实施例的技术方案具有以下有益效果：
本发明技术方案提供的半导体结构的形成方法中，由于所述第二掺杂区内的第二掺杂离子与第三掺杂区内的第三掺杂离子的导电类型相反，因此，所述第二掺杂区与第三掺杂区构成PN结。尽管所述第二掺杂区内第二掺杂离子的掺杂浓度较高，但是，由于所述第三掺杂区不仅位于第一隔离结构底部，还位于若干相邻第一隔离结构之间，使得所述PN结的耗尽区能够完全耗尽，在所述耗尽区产生电场增强效应，因此，有利于提高器件的击穿电压。同时，由于第二掺杂离子的掺杂浓度较高，使得器件的开启电阻较低。综上，所述方法能够同时提高器件的击穿电压、降低开态电阻。
附图说明
图1是一种横向双扩散金属氧化物半导体晶体管的结构示意图；
图2是另一种横向双扩散金属氧化物半导体晶体管的结构示意图；
图3至图6是本发明半导体结构的形成方法一实施例各步骤的结构示意图。
具体实施方式
正如背景技术所述，横向双扩散金属氧化物半导体晶体管的性能较差。
图1是一种横向双扩散金属氧化物半导体晶体管的结构示意图。
请参考图1，基底100，所述基底100内具有相邻的第一掺杂区101和第二掺杂区102，所述第一掺杂区101内具有第一掺杂离子，所述第二掺杂区102内具有第二掺杂离子，所述第二掺杂离子与第一掺杂离子的导电类型相反；位于所述第二掺杂区102内的第一隔离结构103；位于所述基底100顶部的栅极结构104，所述栅极结构104覆盖部分第一掺杂区101、第二掺杂区102和第一隔离结构103；位于所述栅极结构104一侧第一掺杂区101内的源区105；位于所述栅极结构104和第一隔离结构103一侧第二掺杂区102内的漏区106。
上述横向双扩散金属氧化物半导体晶体管具有两个重要性能参数，包括击穿电压和开态电阻。当击穿电压较高时，有利于提高器件的可靠性；当所述开态电阻较小时，有利于提高器件的电学性能。因此，性能良好的横向双扩散金属氧化物半导体晶体管具有较高的击穿电压和较低的开态电阻。
目前，提高器件击穿电压的方法有两种，一种方法是：增加第一隔离结构103沿源区105和漏区106连线方向上的尺寸；另一种方法是：降低第二掺杂区102内第二掺杂离子的掺杂浓度。然而，增加第一隔离结构103沿源区105和漏区106连线方向上的尺寸，容易增大器件的开态电阻；降低所述第二掺杂离子的掺杂浓度时，由于所述第二掺杂离子用于提高第二掺杂区102的导电能力，使得第二掺杂区102的电阻较大。相反的，减小第一隔离结构103沿源区105和漏区106连线方向上的尺寸，或者增加第二掺杂区102内第二掺杂离子的掺杂浓度，能够降低态电阻，但是，器件的击穿电压较小。综上，所述方法难以同时提高器件击穿电压和降低开态电阻。
图2是另一种横向双扩散金属氧化物半导体晶体管的结构示意图。图2所示横向双扩散金属氧化物半导体晶体管与图1所示横向双扩散金属氧化物半导体晶体管的不同点仅在于：在所述第一隔离结构103底部的第二掺杂区102内形成第三掺杂区200，所述第三掺杂区200内具有第三掺杂离子，所述第三掺杂离子与第二掺杂离子的导电类型相反。
上述横向双扩散金属氧化物半导体晶体管中，由于第三掺杂离子与第二掺杂离子的导电类型相反，使得第三掺杂区200与第二掺杂区102之间形成PN结。为了降低开态电阻，增加所述第二掺杂区102内第二掺杂离子的掺杂浓度较高。尽管所述第二掺杂区102内第二掺杂离子的掺杂浓度较高，但是，所述PN结耗尽区能够被完全耗尽，因此，有利于提高击穿电压。
为了进一步降低开态电阻，需进一步增大第二掺杂离子的掺杂浓度。然而，所述第二掺杂离子的掺杂浓度过大，使得第二掺杂区与第三掺杂区形成的PN结耗尽区难以完全耗尽，因此，不利于提高器件的击穿电压。
由此可见，所述第三掺杂区200提高击穿电压、降低开态电阻的能力有限。
为解决所述技术问题，本发明提供了一种半导体结构的形成方法，在所述第二掺杂区内形成若干个相互分立的第一隔离结构；在相邻所述第一隔离结构之间以及第一隔离结构底部的第二掺杂区内形成第三掺杂区，所述第三掺杂区内具有第三掺杂离子，所述第三掺杂离子与第二掺杂离子的导电类型相反。所述方法能够同时提高击穿电压、降低开态电阻。
为使本发明的上述目的、特征和有益效果能够更为明显易懂，下面结合附图对本发明的具体实施例做详细的说明。
图3至图6是本发明半导体结构的形成方法一实施例各步骤的结构示意图。
请参考图3，提供基底300，所述基底300内具有邻接的第一掺杂区301和第二掺杂区302，所述第一掺杂区301内具有第一掺杂离子，所述第二掺杂区302内具有第二掺杂离子，所述第二掺杂离子与第一掺杂离子的导电类型相反。
所述基底300的材料包括硅或者硅锗。
所述第一掺杂区301的形成工艺包括第一离子注入工艺；所述第二掺杂区302的形成工艺包括第二离子注入工艺。
在本实施例中，所述第一掺杂离子为P型离子，所述第二掺杂离子为N型离子。所述P型离子包括硼离子，所述N型离子包括磷离子或者砷离子。
所述第二掺杂离子用于降低第二掺杂区302的电阻，所述第二掺杂离子的掺杂浓度为：2e15原子数/每平方厘米～3e15原子数/每平方厘米，所述第二掺杂离子的掺杂浓度较高，因此，有利于降低器件的开态电阻，提高器件的电学性能。
请参考图4，在所述第二掺杂区302内形成若干个相互分立的第一隔离结构304；在相邻所述第一隔离结构304之间以及第一隔离结构304底部的第二掺杂区302内形成第三掺杂区303，所述第三掺杂区303内具有第三掺杂离子，所述第三掺杂离子与第二掺杂离子的导电类型相反。
所述第一隔离结构304的形成方法包括：在所述基底300、第一掺杂区301和第二掺杂区302顶部形成第一掩膜层(图中未示出)，所述第一掩膜层内具有若干个暴露出第二掺杂区302顶部表面的第一掩膜开口(图中未示出)；以所述第一掩膜开口为掩膜，刻蚀所述第二掺杂区302，在所述第二掺杂区302内形成第一隔离开口；在所述第一隔离开口内形成第一隔离结构304，所述第一隔离结构304充满第一隔离开口。
所述第一掩膜层的材料包括氮化硅或者氮化钛，所述第一掩膜层用于形成第一隔离开口的掩膜。
以所述第一掩膜开口为掩膜，刻蚀所述第二掺杂区302的工艺包括干法刻蚀工艺和湿法刻蚀工艺中的一种或者两种组合。
所述第一隔离结构304的材料包括氧化硅。
所述第三掺杂区303的形成工艺包括：第三离子注入工艺。所述第三掺杂区303内第三掺杂离子的导电类型与第二掺杂离子的导电类型相反。
在本实施例中，所述第三掺杂离子的导电类型为P型，如：硼离子。
由于所述第三掺杂离子与第二掺杂离子的导电类型相反，因此，第三掺杂区303和第二掺杂区302之间形成PN结。所述第三掺杂区303提高击穿电压的同时降低开态电阻的原理包括：由于第三掺杂区303和第二掺杂区302之间形成PN结，尽管所述第二掺杂区302内第二掺杂离子的掺杂浓度较高，但是，由于第三掺杂区303不仅位于第一隔离结构304底部，还位于相邻第一隔离结构304之间，使得第三掺杂区303与第二掺杂区302形成的PN结的耗尽区能够完全耗尽，因此，有利于提高器件的击穿电压。同时，由于第二掺杂离子的掺杂浓度较高，使得器件的开启电阻较低。
后续在第二掺杂区302内形成漏区，在第一掺杂区301内形成源区，后续在漏区上接电压。可以根据所述电压的范围，调节第一隔离结构304沿源区和漏区连线上的尺寸之和以及第一隔离结构304沿源漏连续上的个数。
在本实施例中，所述漏区电压为：500伏特～700伏特，所述第一隔离结构304沿源区和漏区连线方向上的尺寸之和为：40微米～50微米，所述第一隔离结构沿源区和漏区连续上的个数为3个～4个，所述第一隔离结构304用于提高半导体器件的击穿电压。
所述形成方法还包括：在第一掺杂区301和第二掺杂区302内形成第二隔离结构305。
所述第二隔离结构305的材料包括氧化硅。
所述第二隔离结构305用于实现与周围器件之间的电隔离。
请参考图5，在部分所述第一掺杂区301、第二掺杂区302和部分第一隔离结构304表面形成栅极结构306，；在所述栅极结构306一侧的第一掺杂区301内形成源区307；在所述栅极结构306另一侧的第二掺杂区302内形成漏区308。部分所述第一隔离结构304位于栅极结构306与漏区308之间。
所述栅极结构306包括栅介质层(图中未标出)和位于栅介质层顶部的栅极层(图中未标出)。
所述栅介质层的材料包括氧化硅，所述栅极层的材料包括硅。
所述源区307内具有源离子，所述源离子的导电类型与第二掺杂离子的导电类型相同。在本实施例中，所述源离子为N型离子。
所述漏区308内具有漏离子，所述漏离子的导电类型与第二掺杂离子的导电类型相同。在本实施例中，所述漏离子为N型离子。
所述形成方法还包括：在所述栅极结构306一侧的第一掺杂区301内形成体区(图中未标出)，所述体区内具有体离子，所述体离子的导电类型与源离子的导电类型相同。
通常在漏区308上接电压。可根据所述电压的大小调节第一隔离结构304沿源区和漏区连线上的尺寸之和以及第一隔离结构304沿源区和漏区连线上的个数，使得器件的击穿电压较大，有利于提高器件的可靠性。
请参考图6，在所述基底300、第一掺杂区301、第二掺杂区302和栅极结构306的侧壁和顶部表面形成介质层309；去除部分介质层309，在所述介质层309内形成若干个互连开口(图中未标出)，部分所述互连开口底部暴露出体区，部分所述互连开口底部暴露出源区307顶部，部分所述互连开口底部暴露出漏区308顶部；在所述互连开口内形成互连结构310。
所述介质层309的材料包括氧化硅或者氮氧化硅。
所述介质层309的形成工艺包括化学气相沉积工艺或者物理气相沉积工艺。
所述互连结构310的材料为金属，所述互连结构310用于实现体区、源区307和漏区308与外部电路之间的电连接。
相应的，本发明还提供一种半导体结构，请参考图6，包括：
基底300，所述基底300内具有邻接的第一掺杂区301和第二掺杂区302，所述第一掺杂区301内具有第一掺杂离子，所述第二掺杂区302内具有第二掺杂离子，所述第二掺杂离子与第一掺杂离子的导电类型相反；
位于所述第二掺杂区302内的若干个相互分立的第一隔离结构304；
位于相邻所述第一隔离结构304之间以及第一隔离结构304底部的第三掺杂区303，所述第三掺杂区303内具有第三掺杂离子，所述第三掺杂离子与第二掺杂离子的导电类型相反；
位于部分所述第一掺杂区301、第二掺杂区302和第一隔离结构304表面的栅极结构306；
位于所述栅极结构306一侧第一掺杂区301内的源区307；
位于所述栅极结构306另一侧第二掺杂区302内的漏区308，部分所述第一隔离结构304位于漏区308与栅极结构306之间。
所述第一隔离结构304的材料包括氧化硅。
所述漏区308上的电压为：500伏特～700伏特。
沿源区307和漏区308连线方向上，若干个相互分离的第一隔离结构304的尺寸之和为：40微米～50微米；沿源区307和漏区308连线方向上，所述第一隔离结构304的个数为：3个～4个。
所述第一隔离结构304的厚度为：360纳米～400纳米。
所述第二掺杂离子的掺杂浓度为：2e15原子数每平方厘米～3e15原子数/每平方厘米。
虽然本发明披露如上，但本发明并非限定于此。任何本领域技术人员，在不脱离本发明的精神和范围内，均可作各种更动与修改，因此本发明的保护范围应当以权利要求所限定的范围为准。

Claims (13)

1.一种半导体结构的形成方法，其特征在于，包括：
提供基底，所述基底内具有邻接的第一掺杂区和第二掺杂区，所述第一掺杂区内具有第一掺杂离子，所述第二掺杂区内具有第二掺杂离子，所述第二掺杂离子与第一掺杂离子的导电类型相反；
在所述第二掺杂区内形成若干个相互分立的第一隔离结构；
在相邻所述第一隔离结构之间以及第一隔离结构底部的第二掺杂区内形成第三掺杂区，所述第三掺杂区内具有第三掺杂离子，所述第三掺杂离子与第二掺杂离子的导电类型相反；
在部分所述第一掺杂区、部分第二掺杂区和部分第一隔离结构表面形成栅极结构；
在栅极结构一侧的第一掺杂区内形成源区；
在栅极结构另一侧的第二掺杂区内形成漏区，部分所述第一隔离结构位于栅极结构与漏区之间。
2.如权利要求1所述的半导体结构的形成方法，其特征在于，所述第一隔离结构的形成方法包括：在所述基底、第一掺杂区和第二掺杂区顶部形成第一掩膜层，所述第一掩膜层内具有若干个暴露出第二掺杂区顶部表面的第一掩膜开口；以所述第一掩膜开口为掩膜，刻蚀所述第二掺杂区，在所述第二掺杂区内形成第一隔离开口；在所述第一隔离开口内形成第一隔离结构，所述第一隔离结构充满第一隔离开口。
3.如权利要求1所述的半导体结构的形成方法，其特征在于，所述第一隔离结构的材料包括氧化硅或者氮氧化硅。
4.如权利要求1所述的半导体结构的形成方法，其特征在于，所述漏区上的电压为：500伏特～700伏特。
5.如权利要求4所述的半导体结构的形成方法，其特征在于，沿源区和漏区连线方向上，若干个相互分离的第一隔离结构的尺寸之和为：40微米～50微米；沿源区和漏区连线方向上，所述第一隔离结构的个数为：3个～4个。
6.如权利要求1所述的半导体结构的形成方法，其特征在于，所述第一隔离结构的厚度为：360纳米～400纳米。
7.如权利要求1所述的半导体结构的形成方法，其特征在于，所述第二掺杂离子的掺杂浓度约为：2e15原子数/每平方厘米～3e15原子数/每平方厘米。
8.一种半导体结构，其特征在于，包括：
基底，所述基底内具有邻接的第一掺杂区和第二掺杂区，所述第一掺杂区内具有第一掺杂离子，所述第二掺杂区内具有第二掺杂离子，所述第二掺杂离子与第一掺杂离子的导电类型相反；
位于所述第二掺杂区内的若干个相互分立的第一隔离结构；
位于相邻所述第一隔离结构之间以及第一隔离结构底部第二掺杂区内的第三掺杂区，所述第三掺杂区内具有第三掺杂离子，所述第三掺杂离子与第二掺杂离子的导电类型相反；
位于部分所述第一掺杂区、第二掺杂区和部分第一隔离结构表面的栅极结构；
位于所述栅极结构一侧第一掺杂区内的源区；
位于所述栅极结构另一侧第二掺杂区内的漏区，部分所述第一隔离结构位于所述栅极结构与漏区之间。
9.如权利要求8所述的半导体结构，其特征在于，所述第一隔离结构的材料包括氧化硅。
10.如权利要求8所述的半导体结构，其特征在于，所述漏区上的电压为：500伏特～700伏特。
11.如权利要求10所述的半导体结构，其特征在于，沿源区和漏区连线方向上，若干个相互分离的第一隔离结构的尺寸之和为：40微米～50微米；沿源区和漏区连线方向上，所述第一隔离结构的个数为：3个～4个。
12.如权利要求8所述的半导体结构，其特征在于，所述第一隔离结构的厚度为：360纳米～400纳米。
13.如权利要求8所述的半导体结构，其特征在于，所述第二掺杂离子的掺杂浓度约为：2e15原子数/每平方厘米～3e15原子数/每平方厘米。
CN201910097564.4A 2019-01-31 2019-01-31 半导体结构及其形成方法 Active CN111509044B (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN201910097564.4A CN111509044B (zh) 2019-01-31 2019-01-31 半导体结构及其形成方法
US16/745,601 US11239358B2 (en) 2019-01-31 2020-01-17 Semiconductor structure with isolation structures in doped region and fabrication method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201910097564.4A CN111509044B (zh) 2019-01-31 2019-01-31 半导体结构及其形成方法

Publications (2)

Publication Number Publication Date
CN111509044A true CN111509044A (zh) 2020-08-07
CN111509044B CN111509044B (zh) 2023-09-19

Family

ID=71837966

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201910097564.4A Active CN111509044B (zh) 2019-01-31 2019-01-31 半导体结构及其形成方法

Country Status (2)

Country Link
US (1) US11239358B2 (zh)
CN (1) CN111509044B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112951829A (zh) * 2021-04-07 2021-06-11 芯盟科技有限公司 半导体结构及其形成方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104425591A (zh) * 2013-08-20 2015-03-18 中芯国际集成电路制造(上海)有限公司 晶体管及其形成方法
US20150243766A1 (en) * 2014-02-24 2015-08-27 Vanguard International Semiconductor Corporation Method and apparatus for power device with multiple doped regions
CN108598001A (zh) * 2018-04-24 2018-09-28 上海华虹宏力半导体制造有限公司 半导体结构及其形成方法

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6559499B2 (ja) * 2015-08-10 2019-08-14 ルネサスエレクトロニクス株式会社 半導体装置の製造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104425591A (zh) * 2013-08-20 2015-03-18 中芯国际集成电路制造(上海)有限公司 晶体管及其形成方法
US20150243766A1 (en) * 2014-02-24 2015-08-27 Vanguard International Semiconductor Corporation Method and apparatus for power device with multiple doped regions
CN108598001A (zh) * 2018-04-24 2018-09-28 上海华虹宏力半导体制造有限公司 半导体结构及其形成方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112951829A (zh) * 2021-04-07 2021-06-11 芯盟科技有限公司 半导体结构及其形成方法

Also Published As

Publication number Publication date
US11239358B2 (en) 2022-02-01
US20200251590A1 (en) 2020-08-06
CN111509044B (zh) 2023-09-19

Similar Documents

Publication Publication Date Title
US7417266B1 (en) MOSFET having a JFET embedded as a body diode
TWI518908B (zh) 半導體裝置及其製造方法
KR101430824B1 (ko) 수직형 파워 ｍｏｓｆｅｔ 및 이의 형성 방법
US20080258214A1 (en) Semiconductor Device and Method of Fabricating the Same
KR20130061036A (ko) 전력 ｍｏｓｆｅｔ 및 그 형성 방법
TWI415173B (zh) 低米勒電容之超級接面功率電晶體製造方法
US11264269B1 (en) Method of manufacturing trench type semiconductor device
CN113611750B (zh) Soi横向匀场高压功率半导体器件及制造方法和应用
JP2005510088A (ja) 多結晶シリコンソースコンタクト構造を有するトレンチ金属酸化膜半導体電界効果トランジスタデバイス
CN109216470B (zh) 半导体结构及其形成方法
TW201822295A (zh) 屏蔽閘極溝槽式半導體裝置及其製造方法
CN111029408A (zh) 一种集成esd的vdmos器件及制备方法
US7649222B2 (en) Semiconductor device
US8492221B2 (en) Method for fabricating power semiconductor device with super junction structure
TWI751431B (zh) 具有低閃爍雜訊的半導體裝置及其形成方法
CN111508843B (zh) 半导体器件及其形成方法
KR101469343B1 (ko) 수직 파워 ｍｏｓｆｅｔ 및 그 제조 방법
CN108885999B (zh) 半导体装置及其制造方法
CN111509029B (zh) 半导体器件及其形成方法
CN111509044B (zh) 半导体结构及其形成方法
CN109585558B (zh) 具有多个栅极结构的ldmos finfet结构
CN106384718B (zh) 一种中高压沟槽型mosfet器件的制作方法及结构
US11444167B2 (en) Method of manufacturing trench type semiconductor device
CN211017088U (zh) 一种集成esd的vdmos器件
KR100940643B1 (ko) 반도체 소자의 제조방법

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant