TWI518908B - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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TWI518908B
TWI518908B TW102118366A TW102118366A TWI518908B TW I518908 B TWI518908 B TW I518908B TW 102118366 A TW102118366 A TW 102118366A TW 102118366 A TW102118366 A TW 102118366A TW I518908 B TWI518908 B TW I518908B
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gate electrode
layer
semiconductor
drain region
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TW201351651A (zh
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蘇柏智
周學良
柳瑞興
伍震威
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台灣積體電路製造股份有限公司
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Description

半導體裝置及其製造方法
本發明係有關於一種半導體技術，特別為有關於一種垂直功率金屬氧化物半導體場效電晶體及其製造方法。
在習知的垂直功率金屬氧化物半導體場效電晶體(metal oxide semiconductor field effect transistor，MOSFET)內，具有兩個P型基底區形成於N型磊晶區內。垂直功率金屬氧化物半導體場效電晶體的名稱源自於其源極電極及汲極區重疊。在兩個P型基底區之間的一部分磊晶區進行輕摻雜製程以形成N型摻雜汲極區，其有時稱為N型接面場效電晶體(n-junction field effect transistor，n-JFET)區。P型基底區及N型接面場效電晶體區位於閘極介電層及閘極電極下方。當閘極施加正電壓，在P型基底區會形成電子累積區，作為垂直功率金屬氧化物半導體場效電晶體的源極區連接N型接面場效電晶體區的通道區，N型接面場效電晶體區更透過N型磊晶區連接垂直功率金屬氧化物半導體場效電晶體的汲極區。因此，源極至汲極電流從源極區傳導至P型基底區內的通道、N型接面場效電晶體區、磊晶區而接著至汲極區。
N型接面場效電晶體區位於閘極電極下方，而閘極介電層設置於N型接面場效電晶體區及閘極電極之間。N型接 面場效電晶體區與閘極電極之間具有很大的重疊區域。如此一來，會形成顯著的閘極至汲極的電容，其對其垂直功率金屬氧化物半導體場效電晶體的效能(包括速度)具有不利影響。再者，因為N型接面場效電晶體區為N型磊晶區的一部分，N型接面場效電晶體區為輕摻雜，所以其電阻高，而對驅動垂直功率金屬氧化物半導體場效電晶體的電流具有不利影響。
本發明係提供一種半導體裝置，包括一半導體晶片內的一半導體區、位於半導體區上方的一閘極介電層以及位於閘極介電層上方的一閘極電極。一汲極區位於半導體區上表面且與閘極電極相鄰。一閘極間隙壁位於閘極電極側壁。一介電層位於閘極電極及閘極間隙壁上方。一導電場效板位於介電層上方，其中導電場效板具有一部分位於閘極電極的汲極側上。一深金屬介層連接窗位於半導體區內。一源極電極位於半導體區下方，其透過深金屬介層連接窗而與導電場效板電性短路。
本發明係提供另一種半導體裝置，包括一金屬源極電極、位於金屬源極電極上方的具有第一導電型的重摻雜半導體層、位於重摻雜半導體層上方的具有第一導電型的輕摻雜半導體層、位於輕摻雜半導體層上方的閘極介電層、位於該閘極介電層上方的閘極電極。一汲極區及一源極區位於閘極電極的相對側，其中汲極區及源極區具有相反於第一導電型的第二導電型以及深金屬介層連接窗，從源極區的上表面向下延伸至接觸重摻雜半導體層，其中深金屬介層連接窗與金屬源極電極 電性短路。
本發明係提供一種半導體裝置的製造方法，包括進行磊晶製程，以在具有第一導電型的重摻雜半導體基板上方形成第一導電型的輕摻雜半導體層。在輕摻雜半導體層上方形成閘極介電層。在閘極介電層上方形成閘極電極。在閘極電極的相對側形成汲極區及源極區，其中汲極區及源極區具有相反於第一導電型的第二導電型。形成溝槽從源極區的上表面向下延伸至接觸重摻雜半導體基板。將金屬材料填充於溝槽，以形成深金屬介層連接窗。以及在重摻雜半導體基板下方沉積源極電極，其中深金屬介層連接窗與源極區及源極電極電性短路。
20‧‧‧半導體層
22‧‧‧磊晶層
24‧‧‧淺溝槽隔離區
32‧‧‧閘極氧化層
34‧‧‧閘極層
62‧‧‧彎曲箭頭
64‧‧‧通道區
100‧‧‧垂直功率金屬氧化物半導體場效電晶體區
134、234、334、434‧‧‧閘極電極
134 A、234 A‧‧‧閘極邊緣
135、235、335、435‧‧‧閘極堆疊
136、236‧‧‧P型基底區
138、238‧‧‧N型摻雜汲極區
138A、238A‧‧‧N型摻雜汲極區邊緣
139、239、339、439‧‧‧閘極間隙壁
140、240、340‧‧‧N型重摻雜源極區
142、242、342‧‧‧N型重摻雜汲極區
146、246‧‧‧介電層
148‧‧‧溝槽
150‧‧‧深金屬介層連接窗
152、252‧‧‧導電場效板
153‧‧‧源極電極
154‧‧‧接觸插塞
158‧‧‧金屬線
160‧‧‧垂直功率金屬氧化物半導體場效電晶體區
200‧‧‧高側金屬氧化物半導體場效電晶體區
226、326、426‧‧‧高電壓N型井區
244、344‧‧‧P型重摻雜接點區
260‧‧‧高側金屬氧化物半導體場效電晶體區
300‧‧‧低電壓N型金屬氧化物半導體場效電晶體區
330‧‧‧P型井區
360‧‧‧低電壓N型金屬氧化物半導體場效電晶體區
400‧‧‧低電壓P型金屬氧化物半導體場效電晶體區
440‧‧‧P型重摻雜源極區
442‧‧‧P型重摻雜汲極區
444‧‧‧N型重摻雜接點區
460‧‧‧低電壓P型金屬氧化物半導體場效電晶體區
第1至9圖係繪示出本發明實施例之一種半導體裝置的製造方法的剖面示意圖。
以下說明本發明實施例之製作與使用。然而，可輕易了解本發明實施例提供許多合適的發明概念而可實施於廣泛的各種特定背景。所揭示的特定實施例僅僅用於說明以特定方法製作及使用本發明，並非用以侷限本發明的範圍。
配合各實施例提供一種垂直功率金屬氧化物半導體場效電晶體(metal oxide semiconductor field effect transistor，MOSFET)及其製造方法，並以一實施例說明製造階段及討論各種實施例。圖式及說明中使用相同的標號表示相同或相似的部件。
第1至9圖係繪示出本發明實施例之N型垂直功率金屬氧化物半導體場效電晶體(MOSFET)中間製造階段的剖面示意圖。請參照第1圖，提供一半導體層20，其可為半導體基板。半導體層20可具有矽結晶結構。另外，半導體層20可由其他半導體材料(例如矽鍺)所構成。在某些實施例中，半導體層20為具有P型雜質(例如磷或砷)的重摻雜層(P+層)，例如雜質濃度大約為1019/cm3至1021/cm3的範圍。在上述實施例中，“重摻雜“意指雜質濃度大約為1019/cm3以上。然而，本發明所屬技術領域中具有通常知識者可以理解重摻雜為技術用語且取決於特定裝置類型、科技世代、最小特徵尺寸及類似的因素，因此，該用語可以依照技術評價作解釋而不限於上述的實施例。
透過磊晶製程，在重摻雜半導體層20上方形成磊晶層22，且以P型雜質進行輕摻雜製程，磊晶層22的雜質濃度可大約1014/cm3至1016/cm3的範圍。然而，可以理解的是上述數值僅為範例且可改變成不同數值。磊晶層22為P型層，因此以下稱為P型磊晶層22。P型磊晶層22可為矽層，不過其他半導體材料(例如鍺、矽鍺、III-V族化合物半導體或類似的材料)也可用來形成P型磊晶層22。
在相鄰P型磊晶層22的上表面形成隔離區24，隔離區24可為淺溝槽隔離(shallow trench isolation，STI)區，因此以下稱為淺溝槽隔離區24，不過也可為其他類型的隔離區(例如透過區域性氧化P型磊晶層22形成的場氧化層)。淺溝槽隔離區24可用以隔離不同裝置區，包括垂直功率金屬氧化物半導體場效電晶體區100、高側金屬氧化物半導體場效電晶體區200、 低電壓N型金屬氧化物半導體場效電晶體區300及低電壓P型金屬氧化物半導體場效電晶體區400。
請參照第2圖，在高側金屬氧化物半導體場效電晶體區200內形成高電壓N型井區(high-voltage N-well，HVNW)226，例如透過將N型雜質離子植入磊晶層22。在低電壓N型金屬氧化物半導體場效電晶體區300及低電壓N型金屬氧化物半導體場效電晶體區400內也分別形成高電壓N型井區326及高電壓N型井區426。高電壓N型井區226、326及426從P型磊晶層22的上表面向下延伸入P型磊晶層22，高電壓N型井區226、326及426的下表面高於重摻雜半導體層20的上表面。因此，高電壓N型井區226、326及426透過P型磊晶層22的一部分，與重摻雜半導體層20隔開。在一實施例中，高電壓N型井區226、326及426的雜質濃度可大約為1014/cm3至1017/cm3的範圍。
請同樣參照第2圖，在低電壓N型金屬氧化物半導體場效電晶體區300內形成P型井區330，例如透過離子植入製程。P型井區330從高電壓N型井區326的上表面延伸入高電壓N型井區326，P型井區330的下表面可高於高電壓N型井區326的下表面。因此，P型井區330透過高電壓N型井區326的一部分，與P型磊晶層22分離。P型井區330的雜質濃度可大約為1015/cm3至1018/cm3的範圍。
接著，請參照第3圖，形成閘極氧化層32。在某些實施例中，形成的方法包括熱氧化製程。因此，閘極氧化層32可包括氧化矽。在另一實施例中，閘極氧化層32透過沉積製程形成，該閘極氧化層32可包括氧化矽、氮化矽、氮氧化矽、碳 化矽、其組合或其多層結構。在閘極氧化層32上方形成閘極層34，形成方法可包括毯覆式沉積導電材料。在某些實施例中，閘極層34包括多晶矽，不過也可使用其他導電材料(例如金屬、金屬矽化物或類似的材料)。
請同樣參照第3圖，垂直功率金屬氧化物半導體場效電晶體區100及高側金屬氧化物半導體場效電晶體區200內的閘極層34的某些部分在圖案化步驟中去除。接著，透過將P型雜質離子植入至P型磊晶層22，形成P型基底區136及236。P型基底區136及236的P型雜質濃度可大約為1016/cm3至1019/cm3的範圍。在某些實施例中，在圖案化閘極層34的步驟後以及在去除位於已去除的部分閘極層34下方的部份閘極氧化層32的步驟前，進行離子植入製程以形成P型基底區136及236。在離子植入製程的步驟後，位於已去除的部分閘極層34下方的部份閘極氧化層32也會被去除。
接著，請參照第4圖，進一步圖案化閘極氧化層32及閘極層34以在裝置區100、200、300及400分別形成閘極堆疊135、235、335及435。然後進行離子植入製程以在垂直功率金屬氧化物半導體場效電晶體區100及高側金屬氧化物半導體場效電晶體區200內分別形成N型摻雜汲極(N-type doped drain，NDD)區138及238。N型雜質可包括磷及/或砷。N型摻雜汲極區138及238的N型雜質濃度可大約為1016/cm3至1019/cm3的範圍。離子植入製程大致上可為垂直的，因此邊緣138A及238A分別對準於閘極電極134的邊緣134A及閘極電極234的邊緣234A。因此，N型摻雜汲極區138及238自對準於邊緣134A及 234A。如此一來，閘極電極134及N型摻雜汲極區138之間大致上無重疊，且閘極電極234及N型摻雜汲極區238之間大致上亦無重疊，有助於裝置區100及200內的金屬氧化物半導體場效電晶體的閘極至汲極的電容降低。
請參照第5圖，形成閘極間隙壁139、239、339及439。例如透過沉積介電層及蝕刻介電層以去除水平部分，介電層保留的垂直部分則形成閘極間隙壁139、239、339及439。
請參照第6圖，進行N型離子植入的步驟以形成N型重摻雜源極區140、240及340、N型重摻雜汲極區142、242及342以及N型重摻雜接點(pickup)區444。例如，離子植入區的N型雜質濃度可大約為1019/cm3至1021/cm3的範圍。再者，進行P型離子植入的步驟形成P型重摻雜源極區440、P型重摻雜汲極區442、P型重摻雜接點區244及344。例如，離子植入區的P型雜質濃度可大約為1019/cm3至1021/cm3的範圍。
請參照第7圖，形成介電層146及246。介電層146可包括某些部分位於閘極電極134、閘極間隙壁139及/或N型摻雜汲極區138的上方。在某些實施例中，介電層146可進一步覆蓋N型重摻雜區140。介電層246可包括某些部分位於閘極電極234、閘極間隙壁239及/或N型摻雜汲極區238的上方。介電層146及246可包括氧化物、氮化物、氮氧化物、其組合及其多層結構。形成方法可包括毯覆式沉積步驟以形成毯覆層，然後進行圖案化步驟以圖案化毯覆層。在另一實施例中，圖案化毯覆層的步驟可在形成導電場效板152及252以及深金屬介層連接窗150(未繪示於第7圖，請參照第8圖)的步驟之後進行。
請同樣參照第7圖，進行蝕刻步驟以蝕刻N型重摻雜源極區140、P型基底區136及P型磊晶層22。重摻雜半導體層20露出於所產生的溝槽148，溝槽148亦可延伸入重摻雜半導體層20的上部，重摻雜半導體層20底部則未被蝕刻。在某些實施例中，透過溝槽148可暴露出N型重摻雜源極區140及P型基底區136的側壁。
請參照第8圖，導電材料填入溝槽148且位於介電層146及246上方。形成方法可包括毯覆式沉積步驟及圖案化/回蝕刻的步驟，以去除過量的導電材料部分。介電層146及246上方的導電材料部分分別形成導電場效板152及252。導電場效板152可包括或不包括重疊於一部分閘極電極134的第一部分，以及可包括與閘極電極134的汲極側切齊並位於其上的第二部分。導電場效板152的第二部分重疊於N型摻雜汲極區138。同樣地，導電場效板252可包括或不包括重疊於一部分閘極電極234的第一部分，以及可更包括與閘極電極234的汲極側切齊並位於其上的第二部分。形成導電場效板152及252的導電材料可包括金屬(例如鎢、鋁、鎳或類似的金屬)，不過亦可使用其他導電材料(例如多晶矽、金屬矽極類似的材料)。導電材料的一部分形成深金屬介層連接窗150，電性耦接且接觸N型重摻雜區140及P型基底區136，深金屬介層連接窗150亦與重摻雜半導體層20電性短路。
請參照第9圖，形成一電性連接以使深金屬介層連接窗150與導電場效板152電性短路。例如電性連接可包括接觸插塞154及金屬線158。再者，導電材料沉積於重摻雜半導體區 20上以形成源極電極153。在對應於晶圓及晶片的相對兩側形成源極區140及汲極區142與源極電極153。在某些實施例中，源極電極153包括金屬(例如鋁、銅、鎢、鎳及/或類似的金屬)。由於形成深金屬介層連接窗150，導電場效板152透過重摻雜半導體層20而與源極電極153電性短路。再者，源極區140透過深金屬介層連接窗150連接源極電極153。垂直功率金屬氧化物半導體場效電晶體區160因此形成。亦形成高側金屬氧化物半導體場效電晶體區260、低電壓N型金屬氧化物半導體場效電晶體區360及低電壓P型金屬氧化物半導體場效電晶體區460。
彎曲箭頭62係表示出垂直功率金屬氧化物半導體場效電晶體區100的開啟電流，其通過汲極區142、N型摻雜汲極區138、P型磊晶層22內的通道區64及P型基底區136、源極區140、深金屬介層連接窗150、重摻雜半導體層20及源極電極153。
第1至9圖係繪示出本發明實施例之N型垂直功率金屬氧化物半導體場效電晶體的形成方法，然而本發明所屬技術領域中具有通常知識者可以理解的是，對應的摻雜半導體區為相反的導電型時，上述方法可輕易地用於形成P型垂直功率金屬氧化物半導體場效電晶體。
在本實施例中，N型摻雜汲極區138自對準於閘極電極134的邊緣。因此，使閘極電極134及N型摻雜汲極區138之間的重疊範圍最小化，進而最小化閘極至汲極的電容。導電場效板152與半導體源極區140及源極電極153電性短路，所以導電場效板152無利於降低閘極至汲極的電容。源極電極153與 源極/汲極區140及142位於各自晶片的相對側，且源極電極153位於源極/汲極區140及142的下方。因為通道64為水平的，因此各個垂直功率金屬氧化物半導體場效電晶體160的崩潰電壓取決於橫向的尺寸，例如N型摻雜汲極區138的寬度、P型基底區136的寬度以及P型基底區136與N型摻雜汲極區138之間的P型磊晶層22的寬度。深金屬介層連接窗150連接至重摻雜半導體層20且形成基底連接區，以降低垂直功率金屬氧化物半導體場效電晶體160的體電阻(bulk resistance)。
配合本發明一實施例之一種半導體裝置，包括一半導體晶片內的一半導體區、位於半導體區上方的一閘極介電層以及位於閘極介電層上方的一閘極電極。一汲極區位於半導體區上表面且與閘極電極相鄰。一閘極間隙壁位於閘極電極側壁。一介電層位於閘極電極及閘極間隙壁上方。一導電場效板位於介電層上方，其中導電場效板具有一部分位於閘極電極的汲極側上。一深金屬介層連接窗位於半導體區內。一源極電極位於半導體區下方，其透過深金屬介層連接窗而與導電場效板電性短路。
配合本發明另一實施例之一種半導體裝置，包括金屬源極電極、位於金屬源極電極上方的具有第一導電型的重摻雜半導體層、位於重摻雜半導體層上方的具有第一導電型的輕摻雜半導體層、位於輕摻雜半導體層上方的閘極介電層、位於該閘極介電層上方的閘極電極。一汲極區及一源極區位於閘極電極的相對側，其中汲極區及源極區具有相反於第一導電型的第二導電型以及深金屬介層連接窗，從源極區的上表面向下 延伸至接觸重摻雜半導體層，其中深金屬介層連接窗與金屬源極電極電性短路。
配合本發明又一實施例之一種半導體裝置的製造方法，包括進行磊晶製程，以在具有第一導電型的重摻雜半導體基板上方形成第一導電型的輕摻雜半導體層。在輕摻雜半導體層上方形成閘極介電層。在閘極介電層上方形成閘極電極。在閘極電極的相對側形成汲極區及源極區，其中汲極區及源極區具有相反於第一導電型的第二導電型。形成溝槽從源極區的上表面向下延伸至接觸重摻雜半導體基板；將金屬材料填充於溝槽，以形成深金屬介層連接窗；以及在重摻雜半導體基板下方沉積源極電極，其中深金屬介層連接窗與源極區及源極電極電性短路。
雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作更動、替代與潤飾。再者，本發明之保護範圍並未侷限於說明書內所述特定實施例中的製程、機器、製造、物質組成、裝置、方法及步驟，任何所屬技術領域中具有通常知識者可從本發明揭示內容中理解現行或未來所發展出的製程、機器、製造、物質組成、裝置、方法及步驟，只要可以在此處所述實施例中實施大體相同功能或獲得大體相同結果皆可使用於本發明中。因此，本發明之保護範圍包括上述製程、機器、製造、物質組成、裝置、方法及步驟。另外，每一申請專利範圍所構成個別的實施例，且本發明之保護範圍也包括各個申請專利範圍及實施例的組合。
20‧‧‧半導體層
22‧‧‧磊晶層
24‧‧‧淺溝槽隔離區
62‧‧‧彎曲箭頭
64‧‧‧通道區
100‧‧‧垂直功率金屬氧化物半導體場效電晶體區
134、234、334、434‧‧‧閘極電極
136、236‧‧‧P型基底區
138、238‧‧‧N型摻雜汲極區
140、240、340‧‧‧N型重摻雜源極區
142、242、342‧‧‧N型重摻雜汲極區
146、246‧‧‧介電層
150‧‧‧深金屬介層連接窗
152、252‧‧‧導電場效板
153‧‧‧源極電極
154‧‧‧接觸插塞
158‧‧‧金屬線
160‧‧‧垂直功率金屬氧化物半導體場效電晶體區
200‧‧‧高側金屬氧化物半導體場效電晶體區
226、326、426‧‧‧高電壓N型井區
244、344‧‧‧P型重摻雜接點區
260‧‧‧高側金屬氧化物半導體場效電晶體區
300‧‧‧低電壓N型金屬氧化物半導體場效電晶體區
330‧‧‧P型井區
360‧‧‧低電壓N型金屬氧化物半導體場效電晶體區
400‧‧‧低電壓P型金屬氧化物半導體場效電晶體區
440‧‧‧P型重摻雜源極區
442‧‧‧P型重摻雜汲極區
444‧‧‧N型重摻雜接點區
460‧‧‧低電壓P型金屬氧化物半導體場效電晶體區

Claims (10)

  1. 一種半導體裝置，包括：一半導體區，位於一半導體晶片內；一閘極介電層，位於該半導體區上方；一閘極電極，位於該閘極介電層上方；一汲極區，位於該半導體區一上表面，且與該閘極電極相鄰；一閘極間隙壁，位於該閘極電極的一側壁上，其中該閘極間隙壁位於該閘極電極的一汲極側上；一介電層，位於該閘極電極及該閘極間隙壁上方；一導電場效板，位於該介電層上方，其中該導電場效板包括一第一部分位於該閘極電極的該汲極側上，該第一部分延伸地比該閘極間隙壁還遠離該閘極電極，且該導電場效板還包括一第二部分，該第二部分延伸地比該閘極電極還遠離該半導體區；一深金屬介層連接窗，位於該半導體區內；以及一源極電極，位於該半導體區下方，其中該源極電極透過該深金屬介層連接窗與該導電場效板電性短路。
  2. 如申請專利範圍第1項所述之半導體裝置，更包括位於該半導體區的一摻雜汲極區，其中該摻雜汲極區的雜質濃度低於該汲極區的雜質濃度，及其中該摻雜汲極區橫向位於該閘極電極及該汲極區之間，且具有一底部低於該汲極區的一底部及該摻雜汲極區的一邊緣大致上對準於該閘極電極的一邊緣。
  3. 如申請專利範圍第1項所述之半導體裝置，更包括：一半導體源極區，其中該半導體源極區及該半導體汲極區位於該閘極電極的相對側，且為相同的一導電型；以及一基底區，延伸於該閘極電極下方，其中該基底區內具有該半導體源極區，且其中該深金屬介層連接窗接觸該半導體源極區的側壁及該基底區的側壁。
  4. 如申請專利範圍第1項所述之半導體裝置，其中該半導體區包括：一重摻雜層；以及一輕摻雜層，位於該重摻雜層上方，其中該輕摻雜層及該重摻雜層具有相反於該汲極區的該導電型的一導電型，且其中該深金屬介層連接窗穿透該輕摻雜層，且接觸該重摻雜層。
  5. 一種半導體裝置，包括：一金屬源極電極；一重摻雜半導體層，具有一第一導電型，位於該金屬源極電極上方；一輕摻雜半導體層，具有該第一導電型，位於該重摻雜半導體層上方；一閘極介電層，位於該輕摻雜半導體層上方；一閘極電極，位於該閘極介電層上方；一汲極區及一源極區，位於該閘極電極的相對側，其中該汲極區及該源極區具有相反於該第一導電型的一第二導電型； 一介電層，包括一第一部分位於該閘極電極的一上表面，及一第二部分位於該閘極電極的一汲極側上；一導電場效板，位於該介電層上方，其中該導電場效板包括一第一部分位於該閘極電極的該汲極側上，該第一部分與該閘極電極切齊，且該導電場效板還包括一第二部分，該第二部分延伸地比該閘極電極還遠離該輕摻雜半導體層；以及一深金屬介層連接窗，從該源極區的一上表面向下延伸至接觸該重摻雜半導體層，其中該深金屬介層連接窗與該金屬源極電極電性短路。
  6. 如申請專利範圍第5項所述之半導體裝置，更包括：一摻雜汲極區，具有一邊緣大致上對準於該閘極電極的一邊緣，其中該汲極區位於該摻雜汲極區內，且其中該摻雜汲極區的一部分橫向隔開該汲極區與該閘極電極其中該介電層的該第二部分與該摻雜汲極區重疊且該導電場效板的該第一部分覆蓋該摻雜汲極區，且其中該導電場效板電性短路該深金屬介層連接窗。
  7. 如申請專利範圍第5項所述之半導體裝置，更包括：一高電壓井區，具有該第二導電型，位於該輕摻雜半導體層的一上部；以及一低電壓金屬氧化物半導體裝置或高側金屬氧化物半導體裝置，包括一源極區及一汲極區，其中該源極區及該汲極區位於該高電壓井區內。
  8. 一種半導體裝置的製造方法，包括： 進行一磊晶製程，以在具有一第一導電型的一重摻雜半導體基板上方形成該第一導電型的一輕摻雜半導體層；在該輕摻雜半導體層上方形成一閘極介電層；在該閘極介電層上方形成一閘極電極；在該閘極電極的相對側形成一汲極區及一源極區，其中該汲極區及該源極區具有相反於該第一導電型的一第二導電型；形成一介電層，該介電層包括一第一部分位於該閘極電極的一上表面，及一第二部分位於該閘極電極的一汲極側上；在該介電層上方形成一導電場效板，其中該導電場效板包括一第一部分位於該閘極電極的該汲極側上，該第一部分與該閘極電極切齊，且該導電場效板還包括一第二部分，該第二部分延伸地比該閘極電極還遠離該輕摻雜半導體層；形成一溝槽，其從該源極區的一上表面向下延伸至接觸該重摻雜半導體基板；將一金屬材料填充於該溝槽，以形成一深金屬介層連接窗；以及在該重摻雜半導體基板下方沉積一源極電極，其中該深金屬介層連接窗與該源極區及該源極電極電性短路。
  9. 如申請專利範圍第8項所述之半導體裝置的製造方法，更包括：形成一電性連接，使該導電場效板與該深金屬介層連接窗電性短路。
  10. 如申請專利範圍第8項所述之半導體裝置的製造方法，更包括對該輕摻雜半導體層進行一垂直離子植入製程，以形成具有該第二導電型的一摻雜汲極區，其中該汲極區位於該摻雜汲極區內，且其中該摻雜汲極區的一部分橫向隔開該汲極區與該閘極電極。
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