CN105990421A - 半导体器件及其制备方法 - Google Patents

半导体器件及其制备方法 Download PDF

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Publication number
CN105990421A
CN105990421A CN201510048182.4A CN201510048182A CN105990421A CN 105990421 A CN105990421 A CN 105990421A CN 201510048182 A CN201510048182 A CN 201510048182A CN 105990421 A CN105990421 A CN 105990421A
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China
Prior art keywords
oxide layer
grid
region
gate oxide
gate
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CN201510048182.4A
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English (en)
Inventor
李伟
郝龙
金炎
王德进
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CSMC Technologies Corp
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Wuxi CSMC Semiconductor Co Ltd
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Publication date
Application filed by Wuxi CSMC Semiconductor Co Ltd filed Critical Wuxi CSMC Semiconductor Co Ltd
Priority to CN201510048182.4A priority Critical patent/CN105990421A/zh
Priority to US15/547,239 priority patent/US20180012890A1/en
Priority to PCT/CN2015/090476 priority patent/WO2016119479A1/zh
Publication of CN105990421A publication Critical patent/CN105990421A/zh
Pending legal-status Critical Current

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Abstract

本发明涉及一种半导体器件的制备方法，包括步骤：提供包括低压器件区域和高压器件区域的半导体基底；在高压器件区域的非栅极区域和低压器件区域形成第一栅氧化层并在高压器件区域的栅极区域形成第二栅氧化层；第二栅氧化层的厚度大于第一栅氧化层的厚度；在低压器件区域的第一栅氧化层的表面形成第一多晶硅栅以及第一侧墙结构并在第二栅氧化层的表面形成第二多晶硅栅以及第二侧墙结构；第二栅氧化层的宽度大于第二多晶硅栅的宽度；进行源漏极离子注入形成源漏极引出区；淀积金属硅化物阻挡层后进行光刻腐蚀并形成金属硅化物。上述半导体器件的制备方法简化了工艺步骤的同时也降低了工艺成本。还涉及一种半导体器件。

Description

半导体器件及其制备方法
技术领域
本发明涉及半导体制备技术领域，特别是涉及一种半导体器件及其制备方法
背景技术
集成电路产品中，很多需要用到高压器件(例如高压金属氧化物半导体场效晶体管)，其包括源极、漏极以及栅极，且工作电压在10～40V区间。这类产品在生产工艺过程通常需要使用较厚(＞300埃，以实现较高的工作电压)的氧化层作为高压器件的栅氧。由于高压器件源漏极注入(N+，P+)通常能量小剂量大，如果高压器件的源漏极区域剩余氧化层厚度较厚(＞250埃)，源漏极离子注入将会达不到硅表面，导致不能形成表面高掺杂区，造成器件特性异常。此外，源漏极区还需要形成金属硅化物(salicide)，如果没有专门的步骤把高压器件的源漏极区域残留氧化层减薄，那么金属硅化物阻挡层(Silicide Area Block，SAB)蚀刻之后，高压器件的源漏极区域会残余＞100埃的氧化层，从而导致高压器件的源漏极区域不能正常形成金属硅化物，造成器件异常。
传统的高压器件的制备过程通常是与低压器件集成制备的。在栅氧化层形成的过程中，高压器件表面形成氧化层厚度大于低压器件表面的氧化层厚度。因此，在多晶硅(poly)图形形成之后，需要加一个特殊的层次，用光刻胶把低压器件区域盖起来，而把所有高压器件露出来，再用干法腐蚀把高压区域的氧化层吃薄，剩余氧化层厚度一般控制在50～150埃。这样高、低压器件区域的氧化层厚度差异不超过100埃，后续源漏注入和金属硅化物形成才不会受到影响。图1为传统的制备方法所获得的半导体器件中高压器件(NMOS管)区域的结构示意图，图2为图1所示的NMOS管的结构版图。其中，TO表示有源区，GT表示多晶硅栅，SN表示N型源漏极注入区；SP表示P型源漏极注入区，CNT表示接触孔，HV表示栅氧化层，HVPW表示高压P阱，NDDD表示N型双扩散区，STI表示沟槽隔离结构。
发明内容
基于此，有必要针对上述问题，提供一种工艺简单且成本交底的半导体器件栅的制备方法。
还提供一种半导体器件。
一种半导体器件的制备方法，包括步骤：提供包括低压器件区域和高压器件区域的半导体基底；在所述高压器件区域的非栅极区域和所述低压器件区域形成第一栅氧化层并在所述高压器件区域的栅极区域形成第二栅氧化层；所述第二栅氧化层的厚度大于所述第一栅氧化层的厚度；在所述低压器件区域的第一栅氧化层的表面形成第一多晶硅栅以及第一侧墙结构并在所述第二栅氧化层的表面形成第二多晶硅栅以及第二侧墙结构；所述第二栅氧化层的宽度大于所述第二多晶硅栅的宽度；进行源漏极离子注入形成源漏极引出区；淀积金属硅化物阻挡层后进行光刻腐蚀并形成金属硅化物。
在其中一个实施例中，所述第二栅氧化层的宽度比所述第二多晶硅栅的宽度大0.2～1微米。
在其中一个实施例中，所述在所述高压器件区域的非栅极区域和所述低压器件区域形成第一栅氧化层并在所述高压器件区域的栅极区域形成第二栅氧化层的步骤具体包括：在所述半导体基底上形成第二栅氧化层；在所述第二栅氧化层上形成光刻阻挡层并进行光刻腐蚀以在所述高压器件区域的非栅极区域和所述低压器件区域形成窗口；以所述光刻阻挡层为掩膜层将所述窗口区的第二栅氧化层去除；在所述半导体基底表面形成第一栅氧化层。
在其中一个实施例中，所述在所述半导体基底表面形成第一栅氧化层的步骤之后还包括：去除所述光刻阻挡层。
在其中一个实施例中，所述第一栅氧化层的厚度为20～80埃，所述第二栅氧化层的厚度为300～700埃。
在其中一个实施例中，所述淀积金属硅化物阻挡层后进行光刻腐蚀并形成金属硅化物的步骤之后还包括步骤：淀积层间介质层后进行光刻腐蚀形成通孔，并对所述通孔进行金属填充。
在其中一个实施例中，所述提供包括低压器件区域和高压器件区域的半导体基底的步骤包括：提供衬底；在所述衬底上制备沟槽隔离结构并进行表面平坦化；在所述衬底上进行第一导电类型离子注入形成第一导电类型阱；在所述第一导电类型阱中进行第二导电类型离子的注入形成第二导电类型双扩散区。
在其中一个实施例中，所述第一导电类型为P型、所述第二导电类型为N型，或者所述第一导电类型为N型、所述第二导电类型为P型。
一种半导体器件，包括：包括低压器件区域和高压器件区域的半导体基底；形成于所述高压器件区域的非栅极区域和所述低压器件区域的第一栅氧化层以及形成于所述高压器件区域的栅极区域的第二栅氧化层；形成于所述低压器件区域的第一栅氧化层表面的第一多晶硅栅以及第一侧墙结构；形成于所述第二栅氧化层表面的第二多晶硅栅以及第二侧墙结构；形成于所述半导体基底上的源漏极引出区；形成于所述第一栅氧化层表面、第一多晶硅栅以及第一侧墙结构表面的第一金属硅化物阻挡层；形成于所述第二栅氧化层表面、所述第二多晶硅栅以及所述第二侧墙结构表面的第二金属硅化物阻挡层；以及形成于所述源漏极引出区、所述第一多晶硅栅以及所述第二多晶硅栅上的金属硅化物。
在其中一个实施例中，所述第二栅氧化层的宽度比所述第二多晶硅栅的宽度大0.2～1微米。
上述半导体器件以及制备方法，在栅氧化层的制备过程中仅高压器件区域的栅极区域形成有厚度较大的第二栅氧化层，而在其他区域(高压器件的非栅极区域和低压器件区域)形成厚度较小的第一栅氧化层。因此，在多晶硅栅形成后可以直接进行源漏极离子的注入而无需增加单独的工艺步骤来对高压器件区域的剩余氧化层进行减薄，简化了工艺步骤的同时也降低了工艺成本。
附图说明
图1为传统的半导体器件的制备方法得到的半导体器件中高压器件区域的结构示意图；
图2为图1所示高压器件区域的结构版图；
图3为一实施例中的半导体器件的制备方法的流程图；
图4为图3所示实施例中步骤S110的具体流程图；
图5为图3所示实施例中的半导体器件的制备方法中执行步骤S114后器件的结构示意图；
图6为图3所示实施例中的半导体器件的制备方法中执行步骤S118后器件的结构示意图；
图7为图3所示实施例中的半导体器件的制备方法中步骤S120的具体流程图；
图8为图3所示实施例中的半导体器件的制备方法中完成步骤S120后的高压器件区域的结构示意图；
图9为图3所示实施例中的半导体器件的制备方法中完成步骤S130后高压器件区域的结构示意图；
图10为图3所示实施例中的半导体器件的制备方法中完成步骤S140后高压器件区域的结构示意图；
图11为图3所示实施例中的半导体器件的制备方法中完成步骤S150后高压器件区域的结构示意图；
图12为图3所示实施例中的半导体器件的制备方法中完成步骤S160后高压器件区域的结构示意图；
图13为图12所示的高压器件区域的结构版图。
具体实施方式
为使本发明的目的、特征和优点能够更为明显易懂，下面结合附图对本发明的具体实施方式做详细的说明。
在本说明书和附图中，分配给层或区域的参考标记N和P表示这些层或区域分别包括大量电子或空穴。进一步地，分配给N或P的参考标记+和－表示掺杂剂的浓度高于或低于没有这样分配到标记的层中的浓度。在下文的优选实施例的描述和附图中，类似的组件分配有类似的参考标记且该处省略其冗余说明。
一种半导体器件的制备方法，可以同时制备低压器件和高压器件。其中，高压和低压是相对于同时制备的器件的工作电压而言的，即同时制备的器件中的工作电压较高的器件为高压器件，工作电压较低的器件则为低压器件。在本实施例中，制备的低压器件和高压器件为金属氧化物半导体场效应管(MOS管)图3为一实施例中的半导体器件的制备方法，包括以下步骤。
S110，提供半导体基底。
半导体器件需要同时制备低压器件和高压器件，因此在提供的半导体基底中包括高压器件区域以及低压器件区域。在本实施例中，提供半导体基底的步骤的具体流程如图4所示。
提供半导体基底的步骤具体包括S112～S118。
S112，提供衬底。
S114，在衬底上制备沟槽隔离结构并进行表面平坦化。
在衬底表面形成光刻阻挡层，并对光刻阻挡层进行光刻形成窗口区域后对衬底硅进行腐蚀形成沟槽结构。对形成的沟槽结构进行绝缘介质填充形成沟槽隔离结构(Shallow Trench Isolation，STI)。在本实施例中，还会对形成的沟槽隔离结构进行化学机械抛光(Chemical Mechanical Polishing，CMP)处理，以实现器件表面的平坦化。根据不同的技术要求，沟槽隔离结构的沟槽(trench)的深度约为3000～8000埃。图5为完成步骤S114后器件的结构示意图。其中，302为衬底，304则为沟槽隔离结构。
S116，在衬底上进行第一导电类型离子的注入形成第一导电类型阱。
S118，在第一导电类型阱中进行第二导电类型离子注入形成第二导电类型双扩散区。
图6为执行步骤S118后器件的结构示意图。如图6，在衬底302上形成有第一导电类型阱306，在第一导电类型阱306上形成有第二导电类型双扩散区(double diffused drain，DDD)308。
完成步骤S118后即完成了对半导体基底的制备。
S120，形成第一栅氧化层和第二栅氧化层。
在高压器件区域的非栅极区域和低压器件区域形成第一栅氧化层并在高压器件区域的栅极区域形成第二栅氧化层。其中，第二栅氧化层的厚度大于第一栅氧化层的厚度。这是因为，高压器件的工作电压比低压器件的工作电压高，因此需要使用较厚的栅氧化层才能够满足要求。
在本实施例中，形成第一栅氧化层和第二栅氧化层的步骤具体包括S122～S128，如图7所示。
S122，形成第二栅氧化层。
在提供的半导体基底表面进行整面生长第二栅氧化层。第二栅氧化层的厚度可以根据高压器件的工作电压需要进行设定。在本实施例中，高压器件的工作电压在10V～40V之间，故第二栅氧化层的厚度为300～700埃。
S124，在第二栅氧化层表面形成光刻阻挡层并进行光刻腐蚀形成窗口。
对在第二栅氧化层表面形成的光刻阻挡层进行光刻腐蚀，从而在高压器件区域的非栅极区域和低压器件区域形成窗口。
S126，去除窗口区的第二栅氧化层。
以光刻阻挡层为掩膜层将窗口区域的第二栅氧化层去除，即使得高压器件区域的非栅极区域和低压器件区域的半导体基底的表面露出。S128，形成第一栅氧化层。
在半导体基底的表面形成第一栅氧化层。在本实施例中，形成的第一栅氧化层的厚度为20～80埃。形成第一栅氧化层后还需要将光刻阻挡层去除。图8为完成步骤S128后高压器件区域的结构示意图。其中，310为第一栅氧化层，312为位于高压器件区域的栅极区域的第二栅氧化层。
通过步骤S120进行栅氧化层的制备过程，使得仅在高压器件区域的栅极区域形成有厚度相对较大的第二栅氧化层312，而在其他区域(高压器件区域的非栅极区域和低压器件区域)形成厚度相对较小的第一栅氧化层310。而传统的制备过程则会在高压器件区域的整个表面形成具有相对厚度较大的第二栅氧化层。
S130，形成多晶硅栅以及侧墙结构。
具体地，在低压器件区域的第一栅氧化层的表面形成第一多晶硅栅以及第一侧墙结构，第一侧墙结构同时也位于第一多晶硅栅的侧面。同时，在高压器件的第二栅氧化层的表面形成第二多晶硅栅以及第二侧墙结构。其中，第二栅氧化层的宽度大于第二多晶硅栅的宽度。在本实施例中，形成的第二栅氧化层的宽度比第二多晶硅栅的宽度宽0.2～1微米，具体尺寸可根据器件特性要求来进行调整。因为高压器件的第二栅氧化层需要耐受高压，如果第二栅氧化层不延伸一定尺寸的话，由于光刻工艺对位的偏差，可能会导致第二栅氧化层的边缘区域的厚度达不到耐压需求，从而不能满足高压器件的耐高压的要求，导致器件出现问题。在本实施例中，高压器件的第二侧墙结构位于第二多晶硅栅的侧壁，且同样位于第二栅氧化层的表面(即不与第二导电类型双扩散区表面接触)。图9为完成步骤S130后高压器件区域的结构示意图。其中314为第二多晶硅栅，316为第二侧墙结构。由于低压器件区域第一多晶硅栅以及第一侧墙结构的制备与高压器件的制备工艺相同，此处不作介绍。
S140，进行源漏极离子注入形成源漏极引出区。
对低压器件区域和高压器件区域进行源漏极离子注入形成各自的源漏极引出区。图10为执行步骤S140后的高压器件区域的结构示意图。在第二导电类型双扩散区306进行第二导电类型离子注入形成第二导电类型源漏极引出区318。在第一导电类型阱上且位于沟槽隔离结构304之间的区域进行第一导电类型离子的注入形成第一导电类型源漏极引出区320。
S150，淀积金属硅化物阻挡层后进行光刻腐蚀并形成金属硅化物。
进行金属硅化物阻挡层(Silicide Area Block，SAB)淀积，并对淀积形成的金属硅化物阻挡层进行光刻腐蚀并在源漏极引出区以及多晶硅栅上形成金属硅化物(Silicide)。具体地，在第一栅氧化层、第一多晶硅栅以及第一侧墙结构表面形成第一金属硅化物阻挡层，并在第二栅氧化层、第二多晶硅栅以及第二侧墙结构表面形成第二金属硅化物阻挡层，并在源漏极引出区、第一多晶硅栅以及第二多晶硅栅上形成金属硅化物。图11为完成步骤S150后高压器件区域的结构示意图。其中，322为第二金属硅化物阻挡层，324为金属硅化物。在本实施例中，高压器件的金属硅化物阻挡层位于第二栅氧化层312的表面以及第二侧墙结构316和第二多晶硅栅314的部分表面。金属硅化物324形成于第一导电类型源漏极引出区320、第二导电类型源漏极引出区318以及第二多晶硅栅314上。
传统的制备过程，由于在高压器件区域的表面整面形成了相对厚度较大的第二栅氧化层，在多晶硅(poly)图形形成之后，需要加一个特殊的层次，用光刻胶把低压器件区域盖起来，而把所有高压器件露出来，再用干法腐蚀把高压区域的氧化层吃薄，剩余氧化层厚度一般控制在50～150埃。这样高、低压器件区域的氧化层厚度差异不超过100埃，后续源漏注入和金属硅化物形成才不会受到影响，制备过程复杂且成本较高。而在本实施例中，由于在栅氧化层的制备过程中仅高压器件区域的栅极区域形成有厚度较大的第二栅氧化层312，而在其他区域(高压器件的非栅极区域和低压器件区域)则形成厚度较小的第一栅氧化层310，因此，在第二多晶硅栅314以及第二侧墙结构316形成后可以直接进行源漏极离子的注入而无需增加单独的工艺步骤来对高压器件区域的栅氧化层减薄，简化了工艺步骤的同时也降低了工艺成本。
在本实施例中，第一导电类型为P型，第二导电类型为N型，即制备得到的半导体器件包括为NMOS器件。在其他的实施例中，第一导电类型可以为N型，第二导电类型为P型，即制备得到的半导体器件为PMOS器件。
在本实施例中，还需要进行执行步骤S160。
S160，淀积层间介质层后进行光刻腐蚀形成通孔，并对所述通孔进行金属填充。
在形成的器件表面进行层间介质层(Inter Layer Dielectric，ILD)淀积，并进行光刻腐蚀形成通孔。在形成通孔后对通孔进行金属填充，并进行相关的后续操作后完成半导体器件的制备。图12为完成步骤S160后高压器件区域的结构示意图。其中，326为层间介质层，328为形成的通孔结构。
本发明还提供了一种半导体器件，该器件是通过前述实施例中的半导体器件的制备方法获得的。半导体器件包括：包括低压器件区域和高压器件区域的半导体基底；形成于高压器件区域的非栅极区域和低压器件区域的第一栅氧化层以及形成于高压器件区域的栅极区域表面的第二栅氧化层；形成于低压器件区域的第一栅氧化层表面的第一多晶硅栅以及第一侧墙结构；形成于第二栅氧化层表面的第二多晶硅栅以及第二侧墙结构，第二栅氧化层的宽度大于第二多晶硅栅的宽度；形成于半导体基底上的源漏极引出区；形成于第一栅氧化层、第一多晶硅栅以及第二侧墙结构表面的第一金属硅化物阻挡层；形成于第二栅氧化层、第二多晶硅栅以及第二侧墙结构表面的第二金属硅化物阻挡层；以及形成于源漏极引出区、第一多晶硅栅以及第二多晶硅栅上的金属硅化物。在本实施例中，半导体器件制备的低压器件和高压器件均为双扩散型。形成的第二栅氧化层的宽度比第二多晶硅栅的宽度宽0.2～1微米
图12为该半导体器件中高压器件区域的结构示意图。高压器件区域包括：衬底302，形成于衬底302上的沟槽隔离结构304以及第一导电类型阱306；形成于第一导电类型阱306上的第二导电类型双扩散区308；形成于器件的栅极区域表面的第二栅氧化层312；形成于第二栅氧化层312表面的第二多晶硅栅314和第二侧墙结构316；形成于第二导电类型双扩散区308上的第二导电类型源漏极引出区318；形成于第一导电类型阱304上的第一导电类型源漏极引出区320；形成于第二栅氧化层312、第二侧墙结构316以及第二多晶硅栅314表面的第二金属硅化物阻挡层322；形成于第二多晶硅栅314、第一导电类型源漏极引出区320以及第二导电类型源漏极引出区318上的金属硅化物324；形成于器件表面的层间介质层326。层间介质层326中形成有通孔328用于填充金属实现器件的连接。在本实施例中，第一导电类型为P型，第二导电类型为N型。在其他的实施例中，第一导电类型也可以为N型，第二导电类型为P型。图13为高压器件区域的结构版图，其中TO表示有源区，而CNT则表示接触孔，与通孔328的位置相对应。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (10)

1.一种半导体器件的制备方法，包括步骤：
提供包括低压器件区域和高压器件区域的半导体基底；
在所述高压器件区域的非栅极区域和所述低压器件区域形成第一栅氧化层并在所述高压器件区域的栅极区域形成第二栅氧化层；所述第二栅氧化层的厚度大于所述第一栅氧化层的厚度；
在所述低压器件区域的第一栅氧化层的表面形成第一多晶硅栅以及第一侧墙结构并在所述第二栅氧化层的表面形成第二多晶硅栅以及第二侧墙结构；所述第二栅氧化层的宽度大于所述第二多晶硅栅的宽度；
进行源漏极离子注入形成源漏极引出区；
淀积金属硅化物阻挡层后进行光刻腐蚀并形成金属硅化物。
2.根据权利要求1所述的半导体器件的制备方法，其特征在于，所述第二栅氧化层的宽度比所述第二多晶硅栅的宽度大0.2～1微米。
3.根据权利要求1所述的半导体器件的制备方法，其特征在于，所述在所述高压器件区域的非栅极区域和所述低压器件区域形成第一栅氧化层并在所述高压器件区域的栅极区域形成第二栅氧化层的步骤具体包括：
在所述半导体基底上形成第二栅氧化层；
在所述第二栅氧化层上形成光刻阻挡层并进行光刻腐蚀以在所述高压器件区域的非栅极区域和所述低压器件区域形成窗口；
以所述光刻阻挡层为掩膜层将所述窗口区的第二栅氧化层去除；
在所述半导体基底表面形成第一栅氧化层。
4.根据权利要求3所述的半导体器件的制备方法，其特征在于，所述在所述半导体基底表面形成第一栅氧化层的步骤之后还包括：去除所述光刻阻挡层。
5.根据权利要求1～4任一所述的半导体器件的制备方法，其特征在于，所述第一栅氧化层的厚度为20～80埃，所述第二栅氧化层的厚度为300～700埃。
6.根据权利要求1所述的半导体器件的制备方法，其特征在于，所述淀积金属硅化物阻挡层后进行光刻腐蚀并形成金属硅化物的步骤之后还包括步骤：
淀积层间介质层后进行光刻腐蚀形成通孔，并对所述通孔进行金属填充。
7.根据权利要求1所述的半导体器件的制备方法，其特征在于，所述提供包括低压器件区域和高压器件区域的半导体基底的步骤包括：
提供衬底；
在所述衬底上制备沟槽隔离结构并进行表面平坦化；
在所述衬底上进行第一导电类型离子注入形成第一导电类型阱；
在所述第一导电类型阱中进行第二导电类型离子的注入形成第二导电类型双扩散区。
8.根据权利要求7所述的半导体器件的制备方法，其特征在于，所述第一导电类型为P型、所述第二导电类型为N型，或者所述第一导电类型为N型、所述第二导电类型为P型。
9.一种半导体器件，其特征在于，包括：包括低压器件区域和高压器件区域的半导体基底；形成于所述高压器件区域的非栅极区域和所述低压器件区域的第一栅氧化层以及形成于所述高压器件区域的栅极区域的第二栅氧化层；形成于所述低压器件区域的第一栅氧化层表面的第一多晶硅栅以及第一侧墙结构；形成于所述第二栅氧化层表面的第二多晶硅栅以及第二侧墙结构；形成于所述半导体基底上的源漏极引出区；形成于所述第一栅氧化层、第一多晶硅栅以及第一侧墙结构表面的第一金属硅化物阻挡层；形成于所述第二栅氧化层、所述第二多晶硅栅以及所述第二侧墙结构表面的第二金属硅化物阻挡层；以及形成于所述源漏极引出区、所述第一多晶硅栅以及所述第二多晶硅栅上的金属硅化物。
10.根据权利要求9所述的半导体器件，其特征在于，所述第二栅氧化层的宽度比所述第二多晶硅栅的宽度大0.2～1微米。
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