TWI615966B - 半導體元件 - Google Patents

半導體元件 Download PDF

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TWI615966B
TWI615966B TW105143811A TW105143811A TWI615966B TW I615966 B TWI615966 B TW I615966B TW 105143811 A TW105143811 A TW 105143811A TW 105143811 A TW105143811 A TW 105143811A TW I615966 B TWI615966 B TW I615966B
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effect transistor
field effect
epitaxial layer
substrate
conductivity type
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TW201824538A (zh
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溫文瑩
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新唐科技股份有限公司
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Priority to CN201710205482.8A priority patent/CN108258046B/zh
Priority to US15/856,070 priority patent/US10170542B2/en
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Abstract

一種半導體元件，包括具有第一導電型的基底、金氧半場效電晶體、接面場效電晶體、隔離結構以及具有第二導電型的埋入層。金氧半場效電晶體位於基底上。接面場效電晶體位於基底上。隔離結構位於金氧半場效電晶體與接面場效電晶體之間。埋入層位於金氧半場效電晶體與基底之間。埋入層自金氧半場效電晶體的下方延伸至隔離結構的下方以及接面場效電晶體的下方。

Description

半導體元件
本發明是有關於一種積體電路，且特別是有關於一種半導體元件。
近年來，隨著環保意識抬頭，於是具有低功耗以及高效率能源轉換的高壓元件（high voltage device）愈來愈受到矚目。一般而言，高壓元件主要是應用在功率切換（power switch）元件，例如是開關式電源供應（switching mode power supply，SMPS）、照明、馬達控制或電漿顯示器驅動器等各種領域。
擴散金氧半導體（diffused metal-oxide semiconductor，DMOS）元件為一種典型的高壓元件。一般而言，擴散金氧半導體元件可分為橫向擴散金氧半導體（laterally diffused metal oxide semiconductor，LDMOS）元件與垂直擴散金氧半導體（vertical diffused metal-oxide semiconductor，VDMOS）元件。與LDMOS元件相比，VDMOS元件具有較小的面積，其有利於微型化的科技趨勢。VDMOS元件在操作時必須具有高崩潰電壓（breakdown voltage）以及低的開啟狀態電阻（on-state resistance，Ron）。然而，設計者若要達成高崩潰電壓的規格要求，通常會犧牲開啟狀態電阻，反之亦然。因此，崩潰電壓與開啟狀態電阻處於一種權衡關係（trade-off）。
本發明提供一種半導體元件，其將金氧半場效電晶體與接面場效電晶體串聯，使得所述半導體元件具有高崩潰電壓，同時維持低的開啟狀態電阻。
本發明提供一種半導體元件，包括具有第一導電型的基底、金氧半場效電晶體、第一接面場效電晶體、隔離結構以及具有第二導電型的埋入層。金氧半場效電晶體位於基底上。第一接面場效電晶體位於基底上。隔離結構位於金氧半場效電晶體與第一接面場效電晶體之間。埋入層位於金氧半場效電晶體與基底之間。埋入層自金氧半場效電晶體的下方延伸至隔離結構的下方以及第一接面場效電晶體的下方。
基於上述，本發明之金氧半場效電晶體藉由其下方的埋入層與接面場效電晶體串聯。接面場效電晶體其中之一位於汲極區與埋入層之間。而接面場效電晶體其中之另一位於源極區（或閘極結構）與埋入層之間。當汲極電壓低時，本發明之半導體元件的開啟狀態電阻即為接面場效電晶體的線性電阻。當汲極電壓高時，由於接面場效電晶體的夾止（pinch off）作用，分擔了大部分的壓降，藉此提高了本發明之半導體元件的崩潰電壓。因此，本發明之半導體元件不僅具有高崩潰電壓，同時可維持低的開啟狀態電阻。
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
參照本實施例之圖式以更全面地闡述本發明。然而，本發明亦可以各種不同的形式體現，而不應限於本文中所述之實施例。圖式中的層與區域的厚度會為了清楚起見而放大。相同或相似之標號表示相同或相似之元件，以下段落將不再一一贅述。
在以下的實施例中，第一導電型與第二導電型不同。在一實施例中，第一導電型為N型，第二導電型為P型。在另一實施例中，第一導電型為P型，第二導電型為N型。P型摻雜例如是硼；N型摻雜例如是磷或是砷。在本實施例中，是以第一導電型為P型，第二導電型為N型為例來說明，但本發明並不以此為限。
圖1是依照本發明之第一實施例的一種半導體元件的剖面示意圖。
請先參照圖1，半導體元件10包括具有第一導電型的基底102、具有第二導電型的埋入層104、金氧半場效電晶體100、接面場效電晶體200以及隔離結構300。
金氧半場效電晶體100與接面場效電晶體200皆位於基底102上。在平行於基底102的頂面方向來看，隔離結構300位於金氧半場效電晶體100與接面場效電晶體200之間。在垂直於基底102的頂面方向來看，埋入層104位於金氧半場效電晶體100與基底102之間。埋入層104自金氧半場效電晶體100的下方延伸至隔離結構300的下方以及接面場效電晶體200的下方。如圖1所示，金氧半場效電晶體100的底面、隔離結構300的底面以及接面場效電晶體200的底面可實質上共平面。但本發明不以此為限，在其他實施例中，如圖2所示，隔離結構302的底面亦可低於金氧半場效電晶體100與接面場效電晶體200的底面。
值得注意的是，本實施例之金氧半場效電晶體100藉由埋入層104與接面場效電晶體200電性連接或串聯。因此，當汲極電壓低時，本實施例之半導體元件10的開啟狀態電阻即為金氧半場效電晶體100與接面場效電晶體200的線性電阻。而當汲極電壓高時，由於接面場效電晶體200的夾止作用，分擔了大部分的壓降，藉此提高了本實施例之半導體元件10的崩潰電壓。如此一來，本實施例之半導體元件10不僅具有高崩潰電壓，同時可維持低的開啟狀態電阻。
詳細地說，基底102可以是半導體基底、半導體化合物基底或是絕緣層上有半導體基底（Semiconductor Over Insulator，SOI）。半導體例如是IVA族的原子，例如矽或鍺。半導體化合物例如是IVA族的原子所形成之半導體化合物，例如是碳化矽或是矽化鍺，或是IIIA族原子與VA族原子所形成之半導體化合物，例如是砷化鎵。
埋入層104位於基底102上。在一實施例中，埋入層104可例如是N型埋入層（N-buried layer）、N型磊晶層（N-epi layer）、N型深井區（deep N-well region）或其組合。埋入層104的摻雜濃度為1´10 18/cm 3至1´10 21/cm 3。埋入層104可提供一低電阻路徑，以電性連接金氧半場效電晶體100與接面場效電晶體200。
金氧半場效電晶體100位於埋入層104上，使得埋入層104位於金氧半場效電晶體100與基底102之間。詳細地說，金氧半場效電晶體100包括具有第二導電型的第一磊晶層106、具有第一導電型的基體區108a、108b、源極區110a、110b以及閘極結構120。
第一磊晶層106位於埋入層104上。在一實施例中，第一磊晶層106所植入的摻雜可例如是磷或是砷，其摻雜濃度可例如是1´10 15/cm 3至1´10 17/cm 3。在一實施例中，第一磊晶層106的摻雜濃度小於埋入層104的摻雜濃度。
基體區108a、108b位於第一磊晶層106中。基體區108a、108b彼此分離且不相連。在一實施例中，基體區108a、108b的摻雜濃度可分別是1´10 16/cm 3至1´10 19/cm 3。在一實施例中，基體區108a的摻雜濃度與基體區108b的摻雜濃度可以相同。在替代實施例中，基體區108a的摻雜濃度與基體區108b的摻雜濃度亦可以不同。
源極區110a位於基體區108a中；而源極區110b位於基體區108b中。源極區110a與源極區110b藉由內連線彼此連接。具體地說，源極區110a包括具有第二導電型的摻雜區112a以及具有第一導電型的摻雜區114a。源極區110b包括具有第二導電型的摻雜區112b以及具有第一導電型的摻雜區114b。摻雜區112a、112b靠近閘極結構120。在一實施例中，摻雜區114a、114b的摻雜濃度大於基體區108a、108b的摻雜濃度。摻雜區112a、112b的摻雜濃度大於第一磊晶層106的摻雜濃度。
閘極結構120包括閘介電層120a與閘電極120b。在平行於基底102的頂面方向來看，閘極結構120位於摻雜區112a、112b之間。在垂直於基底102的頂面方向來看，閘介電層120a位於第一磊晶層106（或基體區108a、108b）與閘電極120b之間。也就是說，閘極結構120覆蓋第一磊晶層106的頂面、基體區108a的部分頂面以及基體區108b的部分頂面。閘介電層120a可以是由單材料層所構成。單材料層例如是低介電常數材料或是高介電常數材料。低介電常數材料是指介電常數低於4的介電材料，例如是氧化矽或氮氧化矽。高介電常數材料是指介電常數高於4的介電材料，例如是HfAlO、HfO 2、Al 2O 3或Si 3N 4。閘介電層120a的厚度依不同介電材料的選擇而有所不同，舉例來說，若閘介電層120a為氧化矽的話，其厚度可為5 nm至100 nm。閘電極120b為導電材質，例如金屬、多晶矽、摻雜多晶矽、多晶矽化金屬或其組合而成之堆疊層。
在本實施例中，基體區108a、108b與第一磊晶層106可形成接面場效電晶體105。也就是說，當汲極電壓高時，本實施例之接面場效電晶體105亦可空乏第一磊晶層106，以達到夾止作用並分擔部分壓降，更進一步地提高了本實施例之半導體元件10的崩潰電壓。值得注意的是，基體區108a、108b之間相距一距離D1。在一實施例中，距離D1可例如是400 nm至20000 nm。當此距離D1太短，則會增加本實施例之半導體元件10的開啟狀態電阻。反之，當此距離D1太長且汲極電壓高時，閘介電層120a容易發生崩潰，導致半導體元件10毀損。
另一方面，接面場效電晶體200包括具有第二導電型的第二磊晶層206以及具有第一導電型的摻雜區208a、208b。
第二磊晶層206位於埋入層104上。在一實施例中，第二磊晶層206所植入的摻雜可例如是磷或是砷，其摻雜濃度可例如是1´10 15/cm 3至1´10 17/cm 3。在一實施例中，第二磊晶層206的摻雜濃度與第一磊晶層106的摻雜濃度可實質上相同。但本發明不以此為限，在其他實施例中，第二磊晶層206的摻雜濃度與第一磊晶層106的摻雜濃度亦可以不同。
摻雜區208a、208b分別位於第二磊晶層206中。在一實施例中，摻雜區208a、208b可彼此分離且不相連。在替代實施例中，摻雜區208a、208b亦可以是環狀，彼此相連於另一剖面上。在一實施例中，摻雜區208a、208b的摻雜濃度可分別是1´10 16/cm 3至1´10 19/cm 3。摻雜區208a、208b的形成方法可例如是在形成第二磊晶層206之後，於第二磊晶層206上形成罩幕層（未繪示）。罩幕層（未繪示）暴露出欲形成摻雜區208a、208b的區域。之後，對第二磊晶層206進行一離子佈植製程，以於第二磊晶層206中分別形成摻雜區208a、208b。摻雜區208a、208b之間相距一距離D2。在一實施例中，距離D2可例如是5 μm至20 μm。但本發明不以此為限，在其他實施例中，可隨著設計者的需求調整距離D2的長度。
本實施例之半導體元件10更包括具有第二導電型的摻雜區210位於摻雜區208a、208b之間的第二磊晶層206中。詳細地說，摻雜區210位於第二磊晶層206的上部。摻雜區210的頂面與第二磊晶層206的頂面實質上共平面。摻雜區210與摻雜區208a、208b彼此分離且不相連。在一實施例中，摻雜區210的摻雜濃度為1´10 19/cm 3至1´10 21/cm 3。在一實施例中，摻雜區210可視為金氧半場效電晶體100的汲極區。
此外，半導體元件10更包括接觸窗116a、116b、122、216。接觸窗116a位於源極區110a上；接觸窗116b位於源極區110b上；接觸窗122位於閘極結構120上；而接觸窗216位於摻雜區210（例如是汲極區）上。接觸窗116a、116b、216分別為導電材質，例如金屬、多晶矽、摻雜多晶矽、多晶矽化金屬或其組合。
在一實施例中，金氧半場效電晶體100可視為一種擴散金氧半導體元件；而接面場效電晶體105與接面場效電晶體200皆可視為一種垂直接面場效電晶體（vertical JFET）。在操作電壓下，當汲極電壓Vd、閘極電壓Vg以及接地電壓Vs分別施加在接觸窗216、接觸窗122以及接觸窗116a、116b時，可經由包括第二磊晶層206以及埋入層104所形成的低電阻路徑將汲極電壓Vd施加至第一磊晶層106。接著，一通道形成於閘極結構120下方的基體區108a、108b的頂面上，以開啟金氧半場效電晶體100。因此，當開啟金氧半場效電晶體100時（即汲極電壓低），半導體元件10的開啟狀態電阻可視為第一磊晶層106與第二磊晶層206的電阻總和。另一方面，當關閉金氧半場效電晶體100時（即汲極電壓高），由於接面場效電晶體105、200的夾止作用，分擔了大部分的壓降，藉此提高了本實施例之半導體元件10的崩潰電壓。
另外，本實施例之半導體元件10包括隔離結構300位於金氧半場效電晶體100與接面場效電晶體200之間。隔離結構300可用以分隔第一磊晶層106與摻雜區210（或第二磊晶層206），藉此引導電流以垂直方向（亦即經由第二磊晶層206以及埋入層104的方向）流向第一磊晶層106，進而提升本實施例之半導體元件10的崩潰電壓。在一實施例中，隔離結構300可例如是淺溝渠隔離（Shallow Trench Isolation，STI）結構，其材料包括絕緣材料，所述絕緣材料可以是氧化矽、氮化矽或其組合。
此外，如圖1所示，具有第一導電型的基底102與埋入層104可視為一種二極體101a。此二極體101a與金氧半場效電晶體100並聯。
圖2是依照本發明之第二實施例的一種半導體元件的剖面示意圖。
請參照圖2，本發明第二實施例之半導體元件20與第一實施例之半導體元件10相似，其不同之處在於：第二實施例之半導體元件20之隔離結構302貫穿埋入層，以將所述埋入層分隔成兩個埋入結構104a、104b。埋入結構104a位於金氧半場效電晶體100與基底102之間；埋入結構104b位於接面場效電晶體200與基底102之間。雖然圖2中所繪示的隔離結構302完全貫穿所述埋入層，以配置於埋入結構104a、104b之間。但本發明不以此為限，在其他實施例中，只要隔離結構302部分內埋在所述埋入層中（亦即隔離結構302可不貫穿所述埋入層），即為本發明的範疇。也就是說，隔離結構302的底面可低於埋入結構104a、104b的頂面，且隔離結構302的底面可高於、等於或是低於埋入結構104a、104b的底面。
另外，第二實施例之半導體元件20更包括具有第二導電型的摻雜區103位於隔離結構302的下方的基底102中。摻雜區103自隔離結構302的下方分別延伸至埋入結構104a、104b的下方，以與埋入結構104a、104b接觸。換言之，可經由包括第二磊晶層206、埋入結構104b、摻雜區103、埋入結構104b所形成的低電阻路徑將汲極電壓Vd施加至第一磊晶層106。在一實施例中，具有第一導電型的基底102與埋入結構104b、摻雜區103以及埋入結構104b亦可視為一種二極體101b。此二極體101b與金氧半場效電晶體100並聯。
綜上所述，本發明之金氧半場效電晶體藉由其下方的埋入層與接面場效電晶體串聯。接面場效電晶體其中之一位於汲極區與埋入層之間。而接面場效電晶體其中之另一位於源極區（或閘極結構）與埋入層之間。當汲極電壓低時，本發明之半導體元件的開啟狀態電阻即為接面場效電晶體的線性電阻。當汲極電壓高時，由於接面場效電晶體的夾止作用，分擔了大部分的壓降，藉此提高了本發明之半導體元件的崩潰電壓。因此，本發明之半導體元件不僅具有高崩潰電壓，同時可維持低的開啟狀態電阻。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。
10、20‧‧‧半導體元件
100‧‧‧金氧半場效電晶體
101a、101b‧‧‧二極體
102‧‧‧基底
103、112a、112b、114a、114b、208a、208b、210‧‧‧摻雜區
104‧‧‧埋入層
104a、104b‧‧‧埋入結構
105、200‧‧‧接面場效電晶體
106‧‧‧第一磊晶層
108a、108b‧‧‧基體區
110a、110b‧‧‧源極區
116a、116b、122、216‧‧‧接觸窗
120‧‧‧閘極結構
120a‧‧‧閘介電層
120b‧‧‧閘電極
206‧‧‧第二磊晶層
300、302‧‧‧隔離結構
D1、D2‧‧‧距離
Vd‧‧‧汲極電壓
Vg‧‧‧閘極電壓
Vs‧‧‧接地電壓
圖1是依照本發明之第一實施例的一種半導體元件的剖面示意圖。 圖2是依照本發明之第二實施例的一種半導體元件的剖面示意圖。
10‧‧‧半導體元件
100‧‧‧金氧半場效電晶體
101a‧‧‧二極體
102‧‧‧基底
104‧‧‧埋入層
105、200‧‧‧接面場效電晶體
106‧‧‧第一磊晶層
108a、108b‧‧‧基體區
110a、110b‧‧‧源極區
112a、112b、114a、114b、208a、208b、210‧‧‧摻雜區
116a、116b、122、216‧‧‧接觸窗
120‧‧‧閘極結構
120a‧‧‧閘介電層
120b‧‧‧閘電極
206‧‧‧第二磊晶層
300‧‧‧隔離結構
D1、D2‧‧‧距離
Vd‧‧‧汲極電壓
Vg‧‧‧閘極電壓
Vs‧‧‧接地電壓

Claims (9)

  1. 一種半導體元件，包括：具有一第一導電型的一基底；一金氧半場效電晶體，位於該基底上，具有一第二導電型的一第一磊晶層；一第一接面場效電晶體，位於該基底上，具有該第二導電型的一第二磊晶層；一隔離結構，位於該金氧半場效電晶體與該第一接面場效電晶體之間，以分隔該第一磊晶層與該第二磊晶層；以及具有該第二導電型的一埋入層，位於該金氧半場效電晶體與該基底之間，其中該埋入層自該金氧半場效電晶體的下方延伸至該隔離結構的下方以及該第一接面場效電晶體的下方，以電性連接該金氧半場效電晶體與該第一接面場效電晶體。
  2. 如申請專利範圍第1項所述的半導體元件，其中該金氧半場效電晶體包括：具有該第一導電型的至少兩個基體區，分別位於該第一磊晶層中；具有該第二導電型的至少兩個第一摻雜區，分別位於該些基體區中；以及一閘極結構，位於該些第一摻雜區之間的該第一磊晶層上。
  3. 如申請專利範圍第2項所述的半導體元件，其中該些基體區與該第一磊晶層形成一第二接面場效電晶體。
  4. 如申請專利範圍第2項所述的半導體元件，其中該些基體區之間具有一距離，該距離介於400nm至20000nm之間。
  5. 如申請專利範圍第1項所述的半導體元件，其中該第一接面場效電晶體包括：具有該第一導電型的至少兩個第二摻雜區，分別位於該第二磊晶層中。
  6. 如申請專利範圍第5項所述的半導體元件，更包括具有該第二導電型的一第三摻雜區，位於該些第二摻雜區之間的該第二磊晶層中，其中該些第二摻雜區與該第三摻雜區彼此不相連。
  7. 如申請專利範圍第1項所述的半導體元件，其中該基底與該埋入層形成一二極體，且該二極體與該金氧半場效電晶體並聯。
  8. 如申請專利範圍第1項所述的半導體元件，其中該隔離結構貫穿該埋入層，以將該埋入層分隔成兩個埋入結構，該些埋入結構分別位於該金氧半場效電晶體與該基底之間以及該第一接面場效電晶體與該基底之間。
  9. 如申請專利範圍第8項所述的半導體元件，更包括具有該第二導電型的一第四摻雜區，位於該隔離結構的下方的該基底中，其中該第四摻雜區與該些埋入結構接觸。
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