CN108258046B - 半导体元件 - Google Patents

半导体元件 Download PDF

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CN108258046B
CN108258046B CN201710205482.8A CN201710205482A CN108258046B CN 108258046 B CN108258046 B CN 108258046B CN 201710205482 A CN201710205482 A CN 201710205482A CN 108258046 B CN108258046 B CN 108258046B
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field effect
effect transistor
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CN108258046A (zh
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温文莹
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Nuvoton Technology Corp
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Abstract

本发明提供一种半导体元件，包括具有第一导电型的基底、金属氧化物半导体场效应晶体管、结型场效应晶体管、隔离结构以及具有第二导电型的埋入层。金属氧化物半导体场效应晶体管位于基底上。结型场效应晶体管位于基底上。隔离结构位于金属氧化物半导体场效应晶体管与结型场效应晶体管之间。埋入层位于金属氧化物半导体场效应晶体管与基底之间。埋入层自金属氧化物半导体场效应晶体管的下方延伸至隔离结构的下方以及结型场效应晶体管的下方。

Description

半导体元件
技术领域
本发明是有关于一种集成电路，且特别是有关于一种半导体元件。
背景技术
近年来，随着环保意识抬头，于是具有低功耗以及高效率能源转换的高压元件(high voltage device)愈来愈受到瞩目。一般而言，高压元件主要是应用在功率切换(power switch)元件，例如是开关式电源供应(switching mode power supply，SMPS)、照明、马达控制或等离体子显示器驱动器等各种领域。
扩散金属氧化物半导体导体(diffused metal-oxide semiconductor，DMOS)元件为一种典型的高压元件。一般而言，扩散金属氧化物半导体导体元件可分为横向扩散金属氧化物半导体导体(laterally diffused metal oxide semiconductor，LDMOS)元件与垂直扩散金属氧化物半导体导体(vertical diffused metal-oxide semiconductor，VDMOS)元件。与LDMOS元件相比，VDMOS元件具有较小的面积，其有利于微型化的科技趋势。VDMOS元件在操作时必须具有高击穿电压(breakdown voltage)以及低的开启状态电阻(on-stateresistance，Ron)。然而，设计者若要达成高击穿电压的规格要求，通常会牺牲开启状态电阻，反之亦然。因此，击穿电压与开启状态电阻处于一种权衡关系(trade-off)。
发明内容
本发明提供一种半导体元件，其将金属氧化物半导体场效应晶体管与结型场效应晶体管串联，使得所述半导体元件具有高击穿电压，同时维持低的开启状态电阻。
本发明提供一种半导体元件，包括具有第一导电型的基底、金属氧化物半导体场效应晶体管、第一结型场效应晶体管、隔离结构以及具有第二导电型的埋入层。金属氧化物半导体场效应晶体管位于基底上。第一结型场效应晶体管位于基底上。隔离结构位于金属氧化物半导体场效应晶体管与第一结型场效应晶体管之间。埋入层位于金属氧化物半导体场效应晶体管与基底之间。埋入层自金属氧化物半导体场效应晶体管的下方延伸至隔离结构的下方以及第一结型场效应晶体管的下方。
基于上述，本发明的金属氧化物半导体场效应晶体管藉由其下方的埋入层与结型场效应晶体管串联。结型场效应晶体管其中之一位于漏极区与埋入层之间。而结型场效应晶体管其中的另一位于源极区(或栅极结构)与埋入层之间。当漏极电压低时，本发明的半导体元件的开启状态电阻即为结型场效应晶体管的线性电阻。当漏极电压高时，由于结型场效应晶体管的夹止(pinch off)作用，分担了大部分的压降，藉此提高了本发明的半导体元件的击穿电压。因此，本发明的半导体元件不仅具有高击穿电压，同时可维持低的开启状态电阻。
为让本发明的上述特征和优点能更明显易懂，下文特举实施例，并配合所附图式作详细说明如下。
附图说明
图1是依照本发明的第一实施例的一种半导体元件的剖面示意图。
图2是依照本发明的第二实施例的一种半导体元件的剖面示意图。
符号说明：
10、20：半导体元件
100：金属氧化物半导体场效应晶体管
101a、101b：二极管
102：基底
103、112a、112b、114a、114b、208a、208b、210：掺杂区
104：埋入层
104a、104b：埋入结构
105、200：结型场效应晶体管
106：第一外延层
108a、108b：基体区
110a、110b：源极区
116a、116b、122、216：接触窗
120：栅极结构
120a：栅介电层
120b：栅电极
206：第二外延层
300、302：隔离结构
D1、D2：距离
Vd：漏极电压
Vg：栅极电压
Vs：接地电压
具体实施方式
参照本实施例的图式以更全面地阐述本发明。然而，本发明亦可以各种不同的形式体现，而不应限于本文中所述的实施例。图式中的层与区域的厚度会为了清楚起见而放大。相同或相似的标号表示相同或相似的元件，以下段落将不再一一赘述。
在以下的实施例中，第一导电型与第二导电型不同。在一实施例中，第一导电型为N型，第二导电型为P型。在另一实施例中，第一导电型为P型，第二导电型为N型。P型掺杂例如是硼；N型掺杂例如是磷或是砷。在本实施例中，是以第一导电型为P型，第二导电型为N型为例来说明，但本发明并不以此为限。
图1是依照本发明的第一实施例的一种半导体元件的剖面示意图。
请先参照图1，半导体元件10包括具有第一导电型的基底102、具有第二导电型的埋入层104、金属氧化物半导体场效应晶体管100、结型场效应晶体管200以及隔离结构300。
金属氧化物半导体场效应晶体管100与结型场效应晶体管200皆位于基底102上。在平行于基底102的顶面方向来看，隔离结构300位于金属氧化物半导体场效应晶体管100与结型场效应晶体管200之间。在垂直于基底102的顶面方向来看，埋入层104位于金属氧化物半导体场效应晶体管100与基底102之间。埋入层104自金属氧化物半导体场效应晶体管100的下方延伸至隔离结构300的下方以及结型场效应晶体管200的下方。如图1所示，金属氧化物半导体场效应晶体管100的底面、隔离结构300的底面以及结型场效应晶体管200的底面可实质上共平面。但本发明不以此为限，在其他实施例中，如图2所示，隔离结构302的底面亦可低于金属氧化物半导体场效应晶体管100与结型场效应晶体管200的底面。
值得注意的是，本实施例的金属氧化物半导体场效应晶体管100藉由埋入层104与结型场效应晶体管200电连接或串联。因此，当漏极电压低时，本实施例的半导体元件10的开启状态电阻即为金属氧化物半导体场效应晶体管100与结型场效应晶体管200的线性电阻。而当漏极电压高时，由于结型场效应晶体管200的夹止作用，分担了大部分的压降，藉此提高了本实施例的半导体元件10的击穿电压。如此一来，本实施例的半导体元件10不仅具有高击穿电压，同时可维持低的开启状态电阻。
详细地说，基底102可以是半导体基底、半导体化合物基底或是绝缘层上有半导体基底(Semiconductor Over Insulator，SOI)。半导体例如是IVA族的原子，例如硅或锗。半导体化合物例如是IVA族的原子所形成的半导体化合物，例如是碳化硅或是硅化锗，或是IIIA族原子与VA族原子所形成的半导体化合物，例如是砷化镓。
埋入层104位于基底102上。在一实施例中，埋入层104可例如是N型埋入层(N-buried layer)、N型外延层(N-epi layer)、N型深井区(deep N-well region)或其组合。埋入层104的掺杂浓度为1×1018/cm3至1×1021/cm3。埋入层104可提供一低电阻路径，以电连接金属氧化物半导体场效应晶体管100与结型场效应晶体管200。
金属氧化物半导体场效应晶体管100位于埋入层104上，使得埋入层104位于金属氧化物半导体场效应晶体管100与基底102之间。详细地说，金属氧化物半导体场效应晶体管100包括具有第二导电型的第一外延层106、具有第一导电型的基体区108a、108b、源极区110a、110b以及栅极结构120。
第一外延层106位于埋入层104上。在一实施例中，第一外延层106所注入的掺杂可例如是磷或是砷，其掺杂浓度可例如是1×1015/cm3至1×1017/cm3。在一实施例中，第一外延层106的掺杂浓度小于埋入层104的掺杂浓度。
基体区108a、108b位于第一外延层106中。基体区108a、108b彼此分离且不相连。在一实施例中，基体区108a、108b的掺杂浓度可分别是1×1016/cm3至1×1019/cm3。在一实施例中，基体区108a的掺杂浓度与基体区108b的掺杂浓度可以相同。在替代实施例中，基体区108a的掺杂浓度与基体区108b的掺杂浓度亦可以不同。
源极区110a位于基体区108a中；而源极区110b位于基体区108b中。源极区110a与源极区110b藉由内连线彼此连接。具体地说，源极区110a包括具有第二导电型的掺杂区112a以及具有第一导电型的掺杂区114a。源极区110b包括具有第二导电型的掺杂区112b以及具有第一导电型的掺杂区114b。掺杂区112a、112b靠近栅极结构120。在一实施例中，掺杂区114a、114b的掺杂浓度大于基体区108a、108b的掺杂浓度。掺杂区112a、112b的掺杂浓度大于第一外延层106的掺杂浓度。
栅极结构120包括栅介电层120a与栅电极120b。在平行于基底102的顶面方向来看，栅极结构120位于掺杂区112a、112b之间。在垂直于基底102的顶面方向来看，栅介电层120a位于第一外延层106(或基体区108a、108b)与栅电极120b之间。也就是说，栅极结构120覆盖第一外延层106的顶面、基体区108a的部分顶面以及基体区108b的部分顶面。栅介电层120a可以是由单材料层所构成。单材料层例如是低介电常数材料或是高介电常数材料。低介电常数材料是指介电常数低于4的介电材料，例如是氧化硅或氮氧化硅。高介电常数材料是指介电常数高于4的介电材料，例如是HfAlO、HfO2、Al2O3或Si3N4。栅介电层120a的厚度依不同介电材料的选择而有所不同，举例来说，若栅介电层120a为氧化硅的话，其厚度可为5nm至100nm。栅电极120b为导电材质，例如金属、多晶硅、掺杂多晶硅、多晶硅化金属或其组合而成的堆叠层。
在本实施例中，基体区108a、108b与第一外延层106可形成结型场效应晶体管105。也就是说，当漏极电压高时，本实施例的结型场效应晶体管105亦可空乏第一外延层106，以达到夹止作用并分担部分压降，更进一步地提高了本实施例的半导体元件10的击穿电压。值得注意的是，基体区108a、108b之间相距一距离D1。在一实施例中，距离D1可例如是400nm至20000nm。当此距离D1太短，则会增加本实施例的半导体元件10的开启状态电阻。反之，当此距离D1太长且漏极电压高时，栅介电层120a容易发生击穿，导致半导体元件10毁损。
另一方面，结型场效应晶体管200包括具有第二导电型的第二外延层206以及具有第一导电型的掺杂区208a、208b。
第二外延层206位于埋入层104上。在一实施例中，第二外延层206所注入的掺杂可例如是磷或是砷，其掺杂浓度可例如是1×1015/cm3至1×1017/cm3。在一实施例中，第二外延层206的掺杂浓度与第一外延层106的掺杂浓度可实质上相同。但本发明不以此为限，在其他实施例中，第二外延层206的掺杂浓度与第一外延层106的掺杂浓度亦可以不同。
掺杂区208a、208b分别位于第二外延层206中。在一实施例中，掺杂区208a、208b可彼此分离且不相连。在替代实施例中，掺杂区208a、208b亦可以是环状，彼此相连于另一剖面上。在一实施例中，掺杂区208a、208b的掺杂浓度可分别是1×1016/cm3至1×1019/cm3。掺杂区208a、208b的形成方法可例如是在形成第二外延层206之后，于第二外延层206上形成掩膜层(未绘示)。掩膜层(未绘示)暴露出欲形成掺杂区208a、208b的区域。之后，对第二外延层206进行一离子注入制造工艺，以于第二外延层206中分别形成掺杂区208a、208b。掺杂区208a、208b之间相距一距离D2。在一实施例中，距离D2可例如是5μm至20μm。但本发明不以此为限，在其他实施例中，可随着设计者的需求调整距离D2的长度。
本实施例的半导体元件10还包括具有第二导电型的掺杂区210位于掺杂区208a、208b之间的第二外延层206中。详细地说，掺杂区210位于第二外延层206的上部。掺杂区210的顶面与第二外延层206的顶面实质上共平面。掺杂区210与掺杂区208a、208b彼此分离且不相连。在一实施例中，掺杂区210的掺杂浓度为1×1019/cm3至1×1021/cm3。在一实施例中，掺杂区210可视为金属氧化物半导体场效应晶体管100的漏极区。
此外，半导体元件10还包括接触窗116a、116b、122、216。接触窗116a位于源极区110a上；接触窗116b位于源极区110b上；接触窗122位于栅极结构120上；而接触窗216位于掺杂区210(例如是漏极区)上。接触窗116a、116b、216分别为导电材质，例如金属、多晶硅、掺杂多晶硅、多晶硅化金属或其组合。
在一实施例中，金属氧化物半导体场效应晶体管100可视为一种扩散金属氧化物半导体导体元件；而结型场效应晶体管105与结型场效应晶体管200皆可视为一种垂直结型场效应晶体管(vertical JFET)。在操作电压下，当漏极电压Vd、栅极电压Vg以及接地电压Vs分别施加在接触窗216、接触窗122以及接触窗116a、116b时，可经由包括第二外延层206以及埋入层104所形成的低电阻路径将漏极电压Vd施加至第一外延层106。接着，一通道形成于栅极结构120下方的基体区108a、108b的顶面上，以开启金属氧化物半导体场效应晶体管100。因此，当开启金属氧化物半导体场效应晶体管100时(即漏极电压低)，半导体元件10的开启状态电阻可视为第一外延层106与第二外延层206的电阻总和。另一方面，当关闭金属氧化物半导体场效应晶体管100时(即漏极电压高)，由于结型场效应晶体管105、200的夹止作用，分担了大部分的压降，藉此提高了本实施例的半导体元件10的击穿电压。
另外，本实施例的半导体元件10包括隔离结构300位于金属氧化物半导体场效应晶体管100与结型场效应晶体管200之间。隔离结构300可用以分隔第一外延层106与掺杂区210(或第二外延层206)，藉此引导电流以垂直方向(亦即经由第二外延层206以及埋入层104的方向)流向第一外延层106，进而提升本实施例的半导体元件10的击穿电压。在一实施例中，隔离结构300可例如是浅沟渠隔离(Shallow Trench Isolation，STI)结构，其材料包括绝缘材料，所述绝缘材料可以是氧化硅、氮化硅或其组合。
此外，如图1所示，具有第一导电型的基底102与埋入层104可视为一种二极管101a。此二极管101a与金属氧化物半导体场效应晶体管100并联。
图2是依照本发明的第二实施例的一种半导体元件的剖面示意图。
请参照图2，本发明第二实施例的半导体元件20与第一实施例的半导体元件10相似，其不同之处在于：第二实施例的半导体元件20的隔离结构302贯穿埋入层，以将所述埋入层分隔成两个埋入结构104a、104b。埋入结构104a位于金属氧化物半导体场效应晶体管100与基底102之间；埋入结构104b位于结型场效应晶体管200与基底102之间。虽然图2中所绘示的隔离结构302完全贯穿所述埋入层，以配置于埋入结构104a、104b之间。但本发明不以此为限，在其他实施例中，只要隔离结构302部分内埋在所述埋入层中(亦即隔离结构302可不贯穿所述埋入层)，即为本发明的范畴。也就是说，隔离结构302的底面可低于埋入结构104a、104b的顶面，且隔离结构302的底面可高于、等于或是低于埋入结构104a、104b的底面。
另外，第二实施例的半导体元件20还包括具有第二导电型的掺杂区103位于隔离结构302的下方的基底102中。掺杂区103自隔离结构302的下方分别延伸至埋入结构104a、104b的下方，以与埋入结构104a、104b接触。换言之，可经由包括第二外延层206、埋入结构104b、掺杂区103、埋入结构104b所形成的低电阻路径将漏极电压Vd施加至第一外延层106。在一实施例中，具有第一导电型的基底102与埋入结构104b、掺杂区103以及埋入结构104b亦可视为一种二极管101b。此二极管101b与金属氧化物半导体场效应晶体管100并联。
综上所述，本发明的金属氧化物半导体场效应晶体管藉由其下方的埋入层与结型场效应晶体管串联。结型场效应晶体管其中之一位于漏极区与埋入层之间。而结型场效应晶体管其中的另一位于源极区(或栅极结构)与埋入层之间。当漏极电压低时，本发明的半导体元件的开启状态电阻即为结型场效应晶体管的线性电阻。当漏极电压高时，由于结型场效应晶体管的夹止作用，分担了大部分的压降，藉此提高了本发明的半导体元件的击穿电压。因此，本发明的半导体元件不仅具有高击穿电压，同时可维持低的开启状态电阻。
虽然本发明已以实施例揭露如上，然其并非用以限定本发明，任何本领域技术人员，在不脱离本发明的精神和范围内，当可作些许的更动与润饰，故本发明的保护范围当视所附的权利要求所界定者为准。

Claims (9)

1.一种半导体元件，其特征在于，包括：
具有一第一导电型的一基底；
一金属氧化物半导体场效应晶体管，位于该基底上；
一第一结型场效应晶体管，位于该基底上；
一隔离结构，位于该金属氧化物半导体场效应晶体管与该第一结型场效应晶体管之间；以及
具有一第二导电型的一埋入层，位于该金属氧化物半导体场效应晶体管与该基底之间，其中该埋入层自该金属氧化物半导体场效应晶体管的下方延伸至该隔离结构的下方以及该第一结型场效应晶体管的下方；
该隔离结构贯穿该埋入层，以将该埋入层分隔成两个埋入结构，所述埋入结构分别位于该金属氧化物半导体场效应晶体管与该基底之间以及该第一结型场效应晶体管与该基底之间。
2.如权利要求1所述的半导体元件，其特征在于，该金属氧化物半导体场效应晶体管藉由该埋入层与该第一结型场效应晶体管电连接。
3.如权利要求1所述的半导体元件，其特征在于，该金属氧化物半导体场效应晶体管包括：
具有该第二导电型的一第一外延层，位于该埋入层上；
具有该第一导电型的至少两个基体区，分别位于该第一外延层中；
具有该第二导电型的至少两个第一掺杂区，分别位于所述基体区中；以及
一栅极结构，位于所述第一掺杂区之间的该第一外延层上。
4.如权利要求3所述的半导体元件，其特征在于，所述基体区与该第一外延层形成一第二结型场效应晶体管。
5.如权利要求3所述的半导体元件，其特征在于，所述基体区之间具有一距离，该距离介于400nm至20000nm之间。
6.如权利要求1所述的半导体元件，其特征在于，该第一结型场效应晶体管包括：
具有该第二导电型的一第二外延层，位于该埋入层上；以及
具有该第一导电型的至少两个第二掺杂区，分别位于该第二外延层中。
7.如权利要求6所述的半导体元件，其特征在于，还包括具有该第二导电型的一第三掺杂区，位于所述第二掺杂区之间的该第二外延层中，其中所述第二掺杂区与该第三掺杂区彼此不相连。
8.如权利要求1所述的半导体元件，其特征在于，该基底与该埋入层形成一二极管，且该二极管与该金属氧化物半导体场效应晶体管并联。
9.如权利要求1所述的半导体元件，其特征在于，还包括具有该第二导电型的一第四掺杂区，位于该隔离结构的下方的该基底中，其中该第四掺杂区与所述埋入结构接触。
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