CN108257955B - 半导体元件 - Google Patents

半导体元件 Download PDF

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CN108257955B
CN108257955B CN201710196968.XA CN201710196968A CN108257955B CN 108257955 B CN108257955 B CN 108257955B CN 201710196968 A CN201710196968 A CN 201710196968A CN 108257955 B CN108257955 B CN 108257955B
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温文莹
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Nuvoton Technology Corp
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Abstract

本发明提供一种半导体元件，包括基底、金属氧化物半导体场效晶体管以及多个并联的接面场效晶体管，金属氧化物半导体场效晶体管配置于基底上，金属氧化物半导体场效晶体管包括源极区、漏极区以及配置在源极区与漏极区之间的栅极结构，接面场效晶体管与金属氧化物半导体场效晶体管串联，各接面场效晶体管于源极区与漏极区之间横向延伸。

Description

半导体元件
技术领域
本发明是有关于一种集成电路，且特别是有关于一种半导体元件。
背景技术
近年来，随着环保意识抬头，于是具有低功耗以及高效率能源转换的高压元件(high voltage device)愈来愈受到瞩目。一般而言，高压元件主要是应用在功率切换(power switch)元件，例如是开关式电源供应(switching mode power supply，SMPS)、照明、电机控制或等离子体显示器驱动器等各种领域。
横向扩散金属氧化物半导体(laterally diffused metal oxidesemiconductor，LDMOS)元件是一种典型的高压元件，其可与互补式金属氧化物半导体制造工艺整合，藉此在单一晶片上制造具有控制、逻辑以及电源开关功能的元件。LDMOS元件在操作时必须具有高击穿电压(breakdown voltage)以及低的开启状态电阻(on-stateresistance，Ron)。然而，设计者若要达成高击穿电压的规格要求，通常会牺牲开启状态电阻，反之亦然。因此，击穿电压与开启状态电阻处于一种权衡关系(trade-off)。
发明内容
本发明提供一种半导体元件，其将多个并联的接面场效晶体管与金属氧化物半导体场效晶体管串联，使得所述半导体元件具有高击穿电压，同时维持低的开启状态电阻。
本发明提供一种半导体元件，包括基底、金属氧化物半导体场效晶体管以及多个并联的接面场效晶体管。金属氧化物半导体场效晶体管配置于基底上。金属氧化物半导体场效晶体管包括源极区、漏极区以及配置在源极区与漏极区之间的栅极结构。接面场效晶体管与金属氧化物半导体场效晶体管串联。各接面场效晶体管于源极区与漏极区之间横向延伸。
本发明提供一种半导体元件，包括具有第一导电型的基底、具有第二导电型的源极区与漏极区、栅极结构、具有第二导电型的第一漂移区、多个第一隔离结构以及具有第一导电型的多个第一掺杂区。源极区与漏极区分别配置在基底上。栅极结构配置于源极区与漏极区之间的基底上。第一漂移区配置于基底与栅极结构之间。第一隔离结构分别配置于第一漂移区中，使得第一漂移区分隔为多个第二漂移区。各第二漂移区自源极区延伸至漏极区。第一掺杂区分别配置于第一隔离结构与第二漂移区之间。
基于上述，本发明将多个并联的接面场效晶体管与金属氧化物半导体场效晶体管串联。当漏极电压低时，本发明的半导体元件的开启状态电阻即为接面场效晶体管的并联电阻。当漏极电压高时，由于接面场效晶体管的夹止(pinch off)作用，分担了大部分的压降，藉此提高了本发明的半导体元件的击穿电压(breakdown voltage)。因此，本发明的半导体元件不仅具有高击穿电压，同时可维持低的开启状态电阻。
为让本发明的上述特征和优点能更明显易懂，下文特举实施例，并配合所附图式作详细说明如下。
附图说明
图1是依照本发明的一实施例的一种半导体元件的上视图。
图2是图1的A-A’线的第一实施例的剖面示意图。
图3A是图1的B-B’线的第一实施例的剖面示意图。
图3B是图1的B-B’线的第二实施例的剖面示意图。
附图标号
10、20：半导体元件
100：基底
102：第三掺杂区
104：第一隔离结构
106：接面场效晶体管
108：漂移区
110a、110b：第一掺杂区
110c：第二掺杂区
112：第二隔离结构
114：阱区
202：源极区
204：漏极区
206：第四掺杂区
208：栅极结构
208a：栅介电层
208b：栅电极
210：第三隔离结构
212、214：接触窗
D：距离
具体实施方式
参照本实施例的图式以更全面地阐述本发明。然而，本发明亦可以各种不同的形式体现，而不应限于本文中所述的实施例。图式中的层与区域的厚度会为了清楚起见而放大。相同或相似的标号表示相同或相似的元件，以下段落将不再一一赘述。
在以下的实施例中，第一导电型与第二导电型不同。在一实施例中，第一导电型为N型，第二导电型为P型。在另一实施例中，第一导电型为P型，第二导电型为N型。P型掺杂例如是硼；N型掺杂例如是磷或是砷。在本实施例中，是以第一导电型为P型，第二导电型为N型为例来说明，但本发明并不以此为限。
图1是依照本发明的一实施例的一种半导体元件的上视图。为图面清楚起见，在图1中仅绘示出源极区、漏极区、栅极结构、阱区、第一隔离结构以及接面场效晶体管。
请先参照图1，半导体元件10包括具有第二导电型的源极区202、具有第二导电型的漏极区204、栅极结构208、第一隔离结构104以及多个并联的接面场效晶体管106。
源极区202、漏极区204以及配置于源极区202与漏极区204之间的栅极结构208可构成一金属氧化物半导体场效晶体管。所述金属氧化物半导体场效晶体管与接面场效晶体管106串联。如图1所示，各接面场效晶体管106于源极区202(或栅极结构208)与漏极区204之间横向延伸。换言之，各接面场效晶体管106自源极区202(或栅极结构208)朝向漏极区204的方向(即A-A’线方向)延伸。详细地说，各接面场效晶体管106包括具有第一导电型的两个第一掺杂区110a、110b以及具有第二导电型的漂移区108。在垂直于源极区202(或栅极结构208)朝向漏极区204的方向(即B-B’线方向)上，漂移区108位于两个第一掺杂区110a、110b之间。第一隔离结构104分别配置于接面场效晶体管106之间。也就是说，各第一隔离结构104亦自源极区202(或栅极结构208)延伸至漏极区204，且第一隔离结构104与接面场效晶体管106沿着B-B’线方向交替排列。另外，虽然图1中仅绘示两个接面场效晶体管106，但本发明不以此为限。在其他实施例中，接面场效晶体管106的数量可依需求来调整。
在本实施例中，第一隔离结构104分隔彼此并联的接面场效晶体管106，使得源极区202与漏极区204之间的沟道变成了多沟道(亦即多个漂移区108)。因此，当漏极电压低时，本实施例的半导体元件10的开启状态电阻即为接面场效晶体管106的并联电阻。而当漏极电压高时，由于接面场效晶体管106的夹止作用，分担了大部分的压降，藉此提高了本实施例的半导体元件10的击穿电压。如此一来，本实施例的半导体元件10不仅具有高击穿电压，同时可维持低的开启状态电阻。
值得注意的是，在A-A’线方向上，本实施例的第一隔离结构104与栅极结构208相距一距离D。此距离D可使得栅极结构208中的栅介电层208a(如图2所示)与第一隔离结构104不会重叠，藉此避免时依性介电击穿(time-dependent dielectric breakdown，TDDB)效应，进而提升半导体元件10的可靠度。在一实施例中，距离D可例如是大于或等于0μm。但本发明不以此为限，在其他实施例中，第一隔离结构104与栅极结构208之间的距离可趋近于零，或是部分重叠。
此外，本实施例的半导体元件10更包括具有第一导电型的阱区114。阱区114位于栅极结构208远离接面场效晶体管106的一侧，使得源极区202位于阱区114与栅极结构208之间。另一方面来看，阱区114包围源极区202，并与部分栅极结构208相连。
图2是图1的A-A’线的第一实施例的剖面示意图。图3A是图1的B-B’线的第一实施例的剖面示意图。
请同时参照图1、图2与图3A，从剖面示意图的角度来看，半导体元件10包括具有第一导电型的基底100、具有第二导电型的第三掺杂区102、具有第一导电型的阱区114、具有第二导电型的源极区202、具有第二导电型的漏极区204、具有第一导电型的第四掺杂区206、栅极结构208、第一隔离结构104、第二隔离结构112以及多个并联的接面场效晶体管106。
基底100可以是半导体基底、半导体化合物基底或是绝缘层上有半导体基底(Semiconductor Over Insulator，SOI)。半导体例如是IVA族的原子，例如硅或锗。半导体化合物例如是IVA族的原子所形成的半导体化合物，例如是碳化硅或是硅化锗，或是IIIA族原子与VA族原子所形成的半导体化合物，例如是砷化镓。
第三掺杂区102位于基底100上。在一实施例中，第三掺杂区102可例如是N型外延层(N-epi)、N型深阱(deep N-well)或其组合。
阱区114位于第三掺杂区102中。源极区202与第四掺杂区206分别位于阱区114中。源极区202与第四掺杂区206之间更包括第三隔离结构210。第三隔离结构210例如是局部热氧化隔离结构，其材质为绝缘材料，例如是氧化硅。
栅极结构208包括栅介电层208a与栅电极208b。栅介电层208a位于阱区114(或第三掺杂区102)与栅电极208b之间。栅介电层208a可以是由单材料层所构成。单材料层例如是低介电常数材料或是高介电常数材料。低介电常数材料是指介电常数低于4的介电材料，例如是氧化硅或氮氧化硅。高介电常数材料是指介电常数高于4的介电材料，例如是HfAlO、HfO2、Al2O3或Si3N4。栅介电层208a的厚度依不同介电材料的选择而有所不同，举例来说，若栅介电层208a为氧化硅的话，其厚度可为5nm至100nm。栅电极208b为导电材质，例如金属、多晶硅、掺杂多晶硅、多晶硅化金属或其组合而成的堆叠层。
接面场效晶体管106位于第三掺杂区102中。另一方面，如图3A所示，第三掺杂区102位于接面场效晶体管106与基底100之间。各接面场效晶体管106包括具有第一导电型的两个第一掺杂区110a、110b以及具有第二导电型的漂移区108。如图3A所示，在B-B’线方向上，漂移区108位于两个第一掺杂区110a、110b之间。
如图3A所示，第一隔离结构104分别配置于接面场效晶体管106之间，以分隔接面场效晶体管106。在一实施例中，第一隔离结构104可例如是浅沟渠隔离(Shallow TrenchIsolation，STI)结构。具体来说，第一隔离结构104的形成方法可例如是先在第三掺杂区102中形成多个开口(未绘示)。接着，对所述开口进行一倾斜角度的离子注入制造工艺。通过调整所述倾斜角度，可于所述开口的两侧分别形成第一掺杂区110a、110b。在一实施例中，各第一掺杂区110a、110b的掺杂浓度为1×1017/cm3至1×1019/cm3。但本发明不以此为限，在其他实施例中，可随着设计者的需求调整第一掺杂区110a、110b的掺杂浓度。之后，于所述开口中填入绝缘材料。所述绝缘材料可例如是氧化硅。在一实施例中，第一隔离结构104的底面与漂移区108的底面齐平。但本发明不限于此，在其他实施例中，第一隔离结构104的底面与漂移区108的底面亦可为不同平面。
另外，第二隔离结构112配置于第一隔离结构104与接面场效晶体管106上。如图2所示，第二隔离结构112位于源极区202与漏极区204之间，且第二隔离结构112的一部分位于漂移区108中，第二隔离结构112的另一部分位于第三掺杂区102中。换言之，第二隔离结构112与接面场效晶体管106部分重叠。栅极结构208覆盖第二隔离结构112的部分顶面。通过栅极结构208覆盖部分第二隔离结构112的架构，可使源极区202与漏极区204之间所形成的电场中最大电场强度的位置往第二隔离结构112下方偏移，而非落在栅介电层208a下方，避免厚度较薄的栅介电层208a被过强的电场击穿。在一实施例中，第二隔离结构112例如是局部热氧化隔离结构，其材质为绝缘材料，例如是氧化硅。
在替代实施例中，如图3A所示，第一隔离结构104与第二隔离结构112的组合可视为是一种指叉型结构。第一隔离结构104分别埋入第三掺杂区102中，使得第三掺杂区102分隔为多个漂移区108。在此实施例中，第三掺杂区102的掺杂浓度可实质上等于漂移区108的掺杂浓度。
虽然图3A所绘示的第一隔离结构104与基底100之间具有第三掺杂区102，但本发明不以此为限。在其他实施例中，第一隔离结构104亦可与基底100相连或接触。也就是说，第一隔离结构104与基底100之间可不具有第三掺杂区102。
请回头参照图2，漏极区204位于漂移区108中。在一实施例中，漂移区108的掺杂浓度可高于第三掺杂区102的掺杂浓度；而漏极区204的掺杂浓度可高于漂移区108的掺杂浓度。但本发明不以此为限，在其他实施例中，可随着设计者的需求调整漂移区108的掺杂浓度，以降低本实施例的半导体元件10的开启状态电阻。
此外，半导体元件10更包括接触窗212配置于源极区202上；接触窗214配置于漏极区204上。接触窗212与接触窗214分别为导电材质，例如金属、多晶硅、掺杂多晶硅、多晶硅化金属或其组合。
图3B是图1的B-B’线的第二实施例的剖面示意图。
请参照图3B，本发明第二实施例的半导体元件20与第一实施例的半导体元件10相似，其不同之处在于：第二实施例的半导体元件20更包括具有第一导电型的多个第二掺杂区110c分别配置于第一隔离结构104的下方的第三掺杂区102中。详细地说，第二掺杂区110c的形成方法可例如是先在第三掺杂区102中形成多个开口(未绘示)。接着，对所述开口进行一倾斜角度的离子注入制造工艺。通过调整所述倾斜角度，可于所述开口的两侧分别形成第二掺杂区110a、110b，并同时在所述开口的底部形成第二掺杂区110c。在一实施例中，第一掺杂区110a、110b以及第二掺杂区110c的掺杂浓度可实质上相同。但本发明不以此为限，在其他实施例中，亦可分开形成第一掺杂区110a、110b以及第二掺杂区110c，使得第一掺杂区110a、110b以及第二掺杂区110c的掺杂浓度实质上不同。
值得注意的是，第二掺杂区110c、第三掺杂区102以及基底100可形成另一种接面场效晶体管。当漏极电压高时，由于第二掺杂区110c、第三掺杂区102以及基底100所构成的接面场效晶体管亦具有夹止作用，其可更进一步地提高了本实施例的半导体元件20的击穿电压。
综上所述，本发明将多个并联的接面场效晶体管与金属氧化物半导体场效晶体管串联。当漏极电压低时，本发明的半导体元件的开启状态电阻即为接面场效晶体管的并联电阻。当漏极电压高时，由于接面场效晶体管的夹止作用，分担了大部分的压降，藉此提高了本发明的半导体元件的击穿电压。因此，本发明的半导体元件不仅具有高击穿电压，同时可维持低的开启状态电阻。
虽然本发明已以实施例揭露如上，然其并非用以限定本发明，任何所属技术领域中具有通常知识者，在不脱离本发明的精神和范围内，当可作些许的更动与润饰，故本发明的保护范围当视后附的申请专利范围所界定者为准。

Claims (9)

1.一种半导体元件，其特征在于，所述半导体元件包括：
一金属氧化物半导体场效晶体管，配置于一基底上，其中所述金属氧化物半导体场效晶体管包括：一源极区、一漏极区以及配置在所述源极区与所述漏极区之间的一栅极结构；以及
多个并联的接面场效晶体管，与所述金属氧化物半导体场效晶体管串联，其中各所述多个接面场效晶体管于所述源极区与所述漏极区之间横向延伸；
所述半导体元件更包括多个第一隔离结构，分别配置于所述多个接面场效晶体管之间，其中各所述多个第一隔离结构自所述源极区延伸至所述漏极区。
2.根据权利要求1所述的半导体元件，其特征在于，各所述多个接面场效晶体管包括：
具有一第一导电型的两个第一掺杂区，位于所述基底上；以及
具有一第二导电型的一漂移区，配置在所述两个第一掺杂区之间。
3.根据权利要求2所述的半导体元件，其特征在于，所述半导体元件更包括具有所述第一导电型的多个第二掺杂区，分别配置在所述多个第一隔离结构的下方。
4.根据权利要求1所述的半导体元件，其特征在于，所述多个第一隔离结构与所述栅极结构相距一距离。
5.根据权利要求1所述的半导体元件，其特征在于，所述半导体元件更包括一第二隔离结构，配置于所述多个第一隔离结构与所述多个接面场效晶体管上，其中所述栅极结构部分覆盖所述第二隔离结构的顶面。
6.根据权利要求3所述的半导体元件，其特征在于，所述半导体元件更包括具有一第二导电型的一第三掺杂区，位于所述基底与所述多个接面场效晶体管之间。
7.一种半导体元件，其特征在于，所述半导体元件包括：
具有一第一导电型的一基底；
具有一第二导电型的一源极区与一漏极区，分别配置在所述基底上；
一栅极结构，配置于所述源极区与所述漏极区之间的所述基底上；
具有所述第二导电型的一第一漂移区，配置于所述基底与所述栅极结构之间；
多个第一隔离结构，分别配置于所述第一漂移区中，使得所述第一漂移区分隔为多个第二漂移区，其中各所述多个第二漂移区自所述源极区延伸至所述漏极区；以及
具有所述第一导电型的多个第一掺杂区，分别配置于所述多个第一隔离结构与所述多个第二漂移区之间。
8.根据权利要求7所述的半导体元件，其特征在于，所述半导体元件更包括具有所述第二导电型的一第三掺杂区位于所述基底与所述多个第一隔离结构之间。
9.根据权利要求8所述的半导体元件，其特征在于，所述半导体元件更包括具有所述第一导电型的多个第二掺杂区，分别配置于所述多个第一隔离结构的下方的所述第三掺杂区中。
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