TWI566410B - 半導體元件、終端結構及其製造方法 - Google Patents

半導體元件、終端結構及其製造方法 Download PDF

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TWI566410B
TWI566410B TW103143498A TW103143498A TWI566410B TW I566410 B TWI566410 B TW I566410B TW 103143498 A TW103143498 A TW 103143498A TW 103143498 A TW103143498 A TW 103143498A TW I566410 B TWI566410 B TW I566410B
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region
conductivity type
epitaxial layer
isolation structure
doped
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TW201622150A (zh
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何耕臺
馬士貴
李天鈞
陳錳宏
吳孝嘉
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漢磊科技股份有限公司
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Priority to CN201510096004.9A priority patent/CN105990400A/zh
Priority to US14/749,655 priority patent/US20160172436A1/en
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Description

半導體元件、終端結構及其製造方法
本發明是有關於一種半導體技術，且特別是有關於一種終端結構及其製造方法與包括此終端結構的半導體元件。
近年來，高壓金氧半導體元件已廣泛地應用在各種電源積體電路或智慧型電源積體電路上。高壓金氧半導體元件在使用上需具有高崩潰電壓(breakdown voltage)與低的開啟電阻(on-state resistance；Ron)，以提高元件之效能。
為了提升半導體元件的崩潰電壓，終端結構的設計就變得相當重要。隨著半導體元件之積集度的日益提升，半導體元件之尺寸亦隨之縮小。因此，如何在元件縮小的情形下，維持甚至是提升原本的崩潰電壓，已成為業者亟為重視的議題之一。
有鑒於此，本發明提出一種終端結構及其製造方法與包括此終端結構的半導體元件。於終端區中，於磊晶層上配置單一個塊狀隔離結構，且本發明的方法可有效控制單一個塊狀隔離結 構下方的摻雜區輪廓，藉以提高崩潰電壓。
本發明提出一種終端結構，其包括具有第一導電型的基底、具有第一導電型的磊晶層、單一個塊狀隔離結構以及具有第二導電型的塊狀摻雜區。磊晶層配置於基底上。單一個塊狀隔離結構，配置於磊晶層上。塊狀摻雜區配置於單一個塊狀隔離結構下方的磊晶層中，其中塊狀摻雜區的摻雜深度為漸變分布。
在本發明的一實施例中，上述塊狀摻雜區的摻雜深度隨著接近主動區而增加。
在本發明的一實施例中，上述單一個塊狀隔離結構的厚度為約100埃至10,000埃的範圍內。
在本發明的一實施例中，上述基底的材料包括矽、碳化矽或氮化鎵。
在本發明的一實施例中，上述單一個塊狀隔離結構為場氧化層。
在本發明的一實施例中，當上述第一導電型為N型，第二導電型為P型；或當第一導電型為P型，第二導電型為N型。
本發明另提出一種終端結構的製造方法，包括：於具有第一導電型的基底上形成具有第一導電型的磊晶層；於磊晶層上形成單一個塊狀隔離結構；於單一個塊狀隔離結構上形成光阻層，光阻層具有多數個寬度不同的開口；以光阻層為罩幕，進行離子植入製程，以於單一個塊狀隔離結構下的磊晶層中形成具有第二導電型的多數個摻雜區，其中這些摻雜區的摻雜深度為漸變 分布。
在本發明的一實施例中，上述摻雜區彼此分開，第(i)個摻雜區比第(i+1)個摻雜區更遠離主動區，且第(i)個摻雜區的摻雜深度小於第(i+1)個摻雜區的摻雜深度，且i為正整數。
在本發明的一實施例中，上述方法更包括進行回火製程，使摻雜區彼此連接以形成塊狀摻雜區。
在本發明的一實施例中，上述離子植入製程的植入能量在30KeV至1,000KeV的範圍內，植入劑量在約1×1012/cm2至100×1012/cm2的範圍內。
在本發明的一實施例中，上述光阻層的開口的寬度隨著接近主動區而增加。
在本發明的一實施例中，上述單一個塊狀隔離結構的厚度為約100埃至10,000埃的範圍內。
在本發明的一實施例中，上述單一個塊狀隔離結構為場氧化層。
在本發明的一實施例中，當上述第一導電型為N型，第二導電型為P型；或當第一導電型為P型第二導電型為N型。
本發明又提出一種半導體元件，包括具有第一導電型的基底、具有第一導電型的磊晶層、單一個塊狀隔離結構以及具有第二導電型的塊狀摻雜區。基底具有第一區與第二區。磊晶層配置於基底上。單一個塊狀隔離結構配置於第一區的磊晶層上。塊狀摻雜區配置於單一個塊狀隔離結構下方的磊晶層中，其中塊狀 摻雜區的摻雜深度隨著接近第二區而減少。
在本發明的一實施例中，上述單一個塊狀隔離結構的厚度為約100埃至10,000埃的範圍內。
在本發明的一實施例中，上述基底的材料包括矽、碳化矽或氮化鎵。
在本發明的一實施例中，上述單一個塊狀隔離結構為場氧化層。
在本發明的一實施例中，上述基底更包括第三區，且第一區位於第二區與第三區之間。
在本發明的一實施例中，上述第一區為終端區，第二區為密封環區，且第三區為主動區。
基於上述，在本發明的方法中，利用光阻層作為罩幕，離子穿過單一個塊狀隔離結構植入磊晶層中，而產生具有摻雜深度漸變的離子分布。由於光阻層的開口尺寸可以精準定義，故可有效控制摻雜區的形成輪廓，藉以提高崩潰電壓，且具有較大的製程裕度。
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
10‧‧‧第一區
20‧‧‧第二區
30‧‧‧第三區
100‧‧‧基底
102‧‧‧磊晶層
104‧‧‧隔離結構
106‧‧‧光阻層
107-1、107-2、107-3、107-4‧‧‧開口
108‧‧‧離子植入製程
105a、105b、110-1、110-2、110-3、110-4、118a、118b、120、126a、126b‧‧‧摻雜區
112‧‧‧塊狀摻雜區
114‧‧‧絕緣材料層
114a、114b‧‧‧絕緣層
116‧‧‧導體材料層
116a、116b‧‧‧導體層
122‧‧‧介電層
124a、124b‧‧‧開口
127a、127b‧‧‧導體插塞
128a、128b‧‧‧金屬層
W1、W2、W3、W4‧‧‧寬度
D1、D2、D3、D4‧‧‧摻雜深度
圖1A至圖1F是依照本發明一實施例所繪示的半導體元件的 剖面示意圖。
圖1A至圖1F是依照本發明一實施例所繪示的半導體元件的剖面示意圖。
請參照圖1A，於具有第一導電型的基底100上形成具有第一導電型的磊晶層102。基底100可為N型重摻雜的半導體基底，作為元件的汲極。基底100的材料包括矽、碳化矽或氮化鎵。磊晶層102可為N型輕摻雜的磊晶層，且其形成方法包括進行選擇性磊晶生長(selective epitaxy growth；SEG)製程。此外，基底100具有第一區10、第二區20以及第三區30。第一區10位於第二區20以及第三區30之間。在一實施例中，第一區為終端區(termination area)，第二區為密封環區(seal ring area)，且第三區為主動區(active area)，但本發明並不以此為限。主動區的元件包括橫向擴散金氧半導體(lateral diffused metal-oxide semiconductor；LDMOS)元件、垂直擴散金氧半導體(vertical diffused metal-oxide semiconductor；VDMOS)元件、絕緣閘極雙極電晶體(insulated gate bipolar transistor；IGBT)元件、二極體(diode)元件、雙極接面電晶體(bipolar junction transistor；BJT)元件、接面場效電晶體(junction field effect transistor；JFET)元件、其他半導體元件或其組合。在以下的實施例中，是以主動區的元件為VDMOS元件為例來說明之，但並不用以限定本發明。
接著，於第一區10的磊晶層102上形成單一個塊狀隔離結構104。更具體地說，第一區10中只有一個隔離結構，且此隔離結構為不具開口的塊狀結構或(從上視圖來看)單環結構。單一個塊狀隔離結構的材料包括氧化矽，且其厚度可為約100埃至10,000埃的範圍內，例如約1,000埃至9,000埃、2,000埃至8,000埃、3,000埃至7,000埃、4,000埃至6,000埃、或5,000埃至5,500埃的範圍內。在一實施例中，單一個塊狀隔離結構104包括場氧化層，且其形成方法包括：於磊晶層102上形成具有開口的罩幕層(未繪示)，所述開口裸露出部分磊晶層102；進行氧化製程，以於開口中成長出場氧化層；以及移除罩幕層。以此方式，第一區10中磊晶層102的表面會低於第二區20或第三區30中磊晶層102的表面。
然後，以單一個塊狀隔離結構104為罩幕，選擇性地進行毯覆式(blanket)離子植入製程，以於第二區20、第三區30的磊晶層102中分別形成具有第二導電型的摻雜區105a、105b。摻雜區105a、105b可為P型摻雜區。在一實施例中，摻雜區105a、105b可作為接面場效電晶體(JFET)摻雜區，用以降低元件的閘極下方的開啟電阻。
請參照圖1B，於單一個塊狀隔離結構104上形成光阻層106。光阻層106具有多數個寬度不同的開口107-1、107-2、107-3及107-4。在一實施例中，光阻層106的開口107-1、107-2、107-3及107-4的寬度W1、W2、W3、W4隨著接近第三區30(例如主 動區)而增加，但隨著接近第二區20(例如密封環區)而減少。更具體地說，開口107-1的寬度W1小於開口107-2的寬度W2，開口107-2的寬度W2小於開口107-3的寬度W3，開口107-3的寬度W3小於開口107-4的寬度W4。在此實施例中，是以光阻層106具有四個開口為例來說明之，但並不用以限定本發明。視製程需要，光阻層106也可具有三個開口或多於四個開口。
請參照圖1C，以光阻層106為罩幕，進行離子植入製程108，以於單一個塊狀隔離結構104下的磊晶層102中形成具有第二導電型的多數個摻雜區110-1、110-2、110-3及110-4。摻雜區110-1、110-2、110-3及110-4可為P型摻雜區。控制所述離子植入製程的植入能量與植入劑量，使摻質穿過光阻層106的開口及其下方的單一個塊狀隔離結構104，而植入單一個塊狀隔離結構104下方的磊晶層102中。在一實施例中，所述離子植入製程的植入能量在約30KeV至1,000KeV的範圍內，植入劑量在約1×1012/cm2至100×1012/cm2的範圍內。在此實施例中，由於光阻層106的開口寬度呈漸變分布，故這些摻雜區110-1、110-2、110-3及110-4的摻雜深度亦為漸變分布。在一實施例中，摻雜區110-1、110-2、110-3及110-4的摻雜深度D1、D2、D3、D4隨著接近第三區30(例如主動區)而增加，但隨著接近第二區20(例如密封環區)而減少。更具體地說，這些摻雜區110-1、110-2、110-3及110-4彼此分開，第(i)個摻雜區比第(i+1)個摻雜區更遠離主動區，且第(i)個摻雜區的摻雜深度小於第(i+1)個摻雜區的摻雜深度，且i為 正整數。換言之，摻雜區110-1的摻雜深度D1小於摻雜區110-2的摻雜深度D2，摻雜區110-2的摻雜深度D2小於摻雜區110-3的摻雜深度D3，摻雜區110-3的摻雜深度D3小於摻雜區110-4的摻雜深度D4。之後，移除光阻層106。
參照圖1D，進行回火製程，使這些摻雜區110-1、110-2、110-3及110-4彼此連接形成塊狀摻雜區112。塊狀摻雜區112與磊晶層102之間具有實質上平滑的接面。塊狀摻雜區112可作為橫向變摻雜(variation of lateral doping；VLD)區，以減緩平面接面曲率效應造成的PN接面擊穿，有效提高崩潰電壓。在一實施例中，回火製程可為氧化製程，以同時於第二區20以及第三區的磊晶層102上形成絕緣材料層114。換言之，不需要進行額外的回火製程，利用形成絕緣材料層114的氧化製程即可使摻雜區110-1、110-2、110-3及110-4彼此連接。
如圖1D所示，塊狀摻雜區112的摻雜深度為漸變分布，其沿水平方向多個位點的摻雜深度D1~D4隨著接近第三區30(例如主動區)而增加，但隨著接近第二區20(例如密封環區)而減少。至此，完成本發明之第一區10的終端結構的製作。
特別要注意的是，本發明的方法可有效控制光阻層的開口尺寸，進而有效控制摻雜區的形成輪廓，為相當有競爭力的方法。習知的作法為利用具有開口的場氧化層作為罩幕，但場氧化層的開口尺寸控制不易，例如濕蝕刻會側向蝕刻而難以精準定義，而乾蝕刻則會有高分子殘留問題。然而，本發明是利用光阻 層作為VLD罩幕，離子穿過單一個塊狀場氧化層植入磊晶層中，而產生VLD的離子分布。光阻層的開口尺寸可以精準定義，故有較大的製程裕度製作量產。
以下，將參照圖1D說明本發明之第一區10的終端結構。在本發明之終端結構中，磊晶層102配置於基底100上，單一個塊狀隔離結構104配置於磊晶層102上，且塊狀摻雜區112配置於單一個塊狀隔離結構104下方的磊晶層102中。在一實施例中，磊晶層102與基底100的導電類型相同，但與塊狀摻雜區112的導電類型相反。塊狀摻雜區112的摻雜深度為漸變分布，更具體地說，其摻雜深度隨著接近第三區30(例如主動區)而增加。
接下來，進行第二區20及第三區30的元件的製作。繼續參照圖1D，於第一區10、第二區20及第三區30的基底100上形成導體材料層116。導體材料層116的材料包括摻雜多晶矽，且其形成方法包括進行化學氣相沉積製程。
請參照圖1E，將絕緣材料層114以及導體材料層116圖案化，以於第二區20上形成絕緣層114a與導體層116a以及於第三區30上形成絕緣層114b與導體層116b。在一實施例中，導體層116a更延伸至部分的單一個塊狀隔離結構104上。
接著，以單一個塊狀隔離結構104以及導體層116a、116b為罩幕，進行毯覆式離子植入製程，以於第二區20、第三區30的磊晶層102中分別形成具有第二導電型的摻雜區118a、118b。摻雜區118a、118b可作為P型主體(P-type body；PB)摻雜區。 在一實施例中，由於塊狀摻雜區112與主體摻雜區118a/118b的摻雜濃度不同，故習知的做法需製作一個光罩，使形成的光阻層覆蓋終端區(即第一區10)，以避免主體摻雜區118a/118b的摻雜步驟影響塊狀摻雜區112的摻雜濃度/輪廓。然而，在本發明的方法中，終端區(即第一區10)已被單一個塊狀隔離結構104所覆蓋，故不需要額外的光罩以及光阻層，利用毯覆式離子植入製程則可形成P型主體摻雜區118a、118b。
之後，於第三區30的摻雜區118b中形成具有第一導電型的摻雜區120。摻雜區120可為N型重摻雜區，作為元件的源極。
請參照圖1F，於第一區10、第二區20及第三區30的基底100上形成介電層122。介電層122具有開口124a、124b。開口124a裸露出第二區20之部分摻雜區118a，且開口124b裸露出第三區30之部分摻雜區118b。
接著，進行毯覆式離子植入製程，以於開口124a、124b下方的摻雜區118a、118b中形成具有第二導電型的摻雜區126a、126b。摻雜區126a、126b可為P型重摻雜區，用以降低後續形成之導體插塞的歐姆電阻。
之後，於第二區20及第三區30的介電層122上分別形成金屬層128a、128b。金屬層128a、128b均延伸至第一區10的部分介電層122上。金屬層128a、128b分別填入開口124a、124b且構成導體插塞127a、127b。導體插塞127a、127b分別與摻雜區 126a、126b電性連接。以此方式，第二區20的密封環結構會短路連接至基底100。至此，完成本發明之半導體元件的製作。
以下，將參照圖1F說明本發明之半導體元件。在本發明的半導體元件中，基底100具有第一區10以及位於第一區10兩側的第二區20與第三區30。磊晶層102配置於基底100上。單一個塊狀隔離結構104配置於第一區10的磊晶層102上。塊狀摻雜區112配置於單一個塊狀隔離結構104正下方的磊晶層102中。在一實施例中，磊晶層102與基底100的導電類型相同，但與塊狀摻雜區112的導電類型相反。塊狀摻雜區112的摻雜深度隨著接近第二區20而減少但隨著接近第三區30而增加。
在上述實施例中，是以第一導電型為N型，第二導電型為P型為例來說明之，但並不用以限定本發明。在另一實施例中，當第一導電型為P型，第二導電型為N型。
綜上所述，在本發明的方法中，利用光阻層作為VLD罩幕，離子穿過單一個塊狀場氧化層植入磊晶層中，而產生VLD的離子分布。由於光阻層的開口尺寸可以精準定義，故有較大的製程裕度製作量產。本發明的方法可有效控制VLD的形成輪廓，故可有效提高崩潰電壓。若維持相同的崩潰電壓，則可以得到較短的終端區，有效降低元件尺寸。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍 當視後附的申請專利範圍所界定者為準。
10‧‧‧第一區
20‧‧‧第二區
30‧‧‧第三區
100‧‧‧基底
102‧‧‧磊晶層
104‧‧‧隔離結構
105a、105b‧‧‧摻雜區
112‧‧‧塊狀摻雜區
114‧‧‧絕緣材料層
116‧‧‧導體材料層
D1、D2、D3、D4‧‧‧摻雜深度

Claims (19)

  1. 一種終端結構，包括：具有一第一導電型的一基底；具有該第一導電型的一磊晶層，配置於該基底上；單一個塊狀隔離結構，配置於該磊晶層上；以及具有一第二導電型的一塊狀摻雜區，配置於該單一個塊狀隔離結構下方的該磊晶層中，其中該塊狀摻雜區的摻雜深度為漸變分布，其中該塊狀摻雜區的摻雜深度隨著接近主動區而增加。
  2. 如申請專利範圍第1項所述的終端結構，其中該單一個塊狀隔離結構的厚度為100埃至10,000埃的範圍內。
  3. 如申請專利範圍第1項所述的終端結構，其中該基底的材料包括矽、碳化矽或氮化鎵。
  4. 如申請專利範圍第1項所述的終端結構，其中該單一個塊狀隔離結構為場氧化層。
  5. 如申請專利範圍第1項所述的終端結構，其中當該第一導電型為N型，該第二導電型為P型；或當該第一導電型為P型，該第二導電型為N型。
  6. 一種終端結構的製造方法，包括：於具有一第一導電型的一基底上形成具有該第一導電型的一磊晶層；於該磊晶層上形成單一個塊狀隔離結構；於該單一個塊狀隔離結構上形成一光阻層，該光阻層具有多 數個寬度不同的開口；以該光阻層為罩幕，進行一離子植入製程，以於該單一個塊狀隔離結構下的該磊晶層中形成具有一第二導電型的多數個摻雜區，其中該些摻雜區的摻雜深度為漸變分布。
  7. 如申請專利範圍第6項所述的終端結構的製造方法，其中該些摻雜區彼此分開，第(i)個摻雜區比第(i+1)個摻雜區更遠離主動區，且第(i)個摻雜區的摻雜深度小於第(i+1)個摻雜區的摻雜深度，且i為正整數。
  8. 如申請專利範圍第7項所述的終端結構的製造方法，更包括進行一回火製程，使該些摻雜區彼此連接形成一塊狀摻雜區。
  9. 如申請專利範圍第6項所述的終端結構的製造方法，其中該離子植入製程的植入能量在30KeV至1,000KeV的範圍內，植入劑量在1×1012/cm2至100×1012/cm2的範圍內。
  10. 如申請專利範圍第6項所述的終端結構的製造方法，其中該光阻層的該些開口的寬度隨著接近主動區而增加。
  11. 如申請專利範圍第6項所述的終端結構的製造方法，其中該單一個塊狀隔離結構的厚度為100埃至10,000埃的範圍內。
  12. 如申請專利範圍第6項所述的終端結構的製造方法，其中該單一個塊狀隔離結構為場氧化層。
  13. 如申請專利範圍第6項所述的終端結構的製造方法，其中當該第一導電型為N型，該第二導電型為P型；或當該第一導電型為P型，該第二導電型為N型。
  14. 一種半導體元件，包括：具有一第一導電型的一基底，具有一第一區與一第二區；具有該第一導電型的一磊晶層，配置於該基底上；單一個塊狀隔離結構，配置於該第一區的該磊晶層上；具有一第二導電型的一塊狀摻雜區，配置於該單一個塊狀隔離結構下方的該磊晶層中，其中該塊狀摻雜區的摻雜深度隨著接近該第二區而減少。
  15. 如申請專利範圍第14項所述的半導體元件，其中該單一個塊狀隔離結構的厚度為100埃至10,000埃的範圍內。
  16. 如申請專利範圍第14項所述的半導體元件，其中該基底的材料包括矽、碳化矽或氮化鎵。
  17. 如申請專利範圍第14項所述的半導體元件，其中該單一個塊狀隔離結構為場氧化層。
  18. 如申請專利範圍第14項所述的半導體元件，其中該基底更包括一第三區，且該第一區位於該第二區與該第三區之間。
  19. 如申請專利範圍第18項所述的半導體元件，其中該第一區為終端區，該第二區為密封環區，且該第三區為主動區。
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