CN109216470B - 半导体结构及其形成方法 - Google Patents

半导体结构及其形成方法 Download PDF

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CN109216470B
CN109216470B CN201710533460.4A CN201710533460A CN109216470B CN 109216470 B CN109216470 B CN 109216470B CN 201710533460 A CN201710533460 A CN 201710533460A CN 109216470 B CN109216470 B CN 109216470B
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forming
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fin portion
doping
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CN109216470A (zh
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周飞
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Priority to CN202110519316.1A priority Critical patent/CN113257921B/zh
Priority to CN201710533460.4A priority patent/CN109216470B/zh
Priority to US16/025,576 priority patent/US10804260B2/en
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Abstract

本发明提供一种半导体结构及其形成方法，包括：提供衬底，所述衬底包括二极管区，所述二极管区衬底上具有第一鳍部；在所述第一鳍部中形成第一掺杂层，所述第一掺杂层中具有第一离子；在所述第一掺杂层表面形成第二掺杂层，所述第二掺杂层中具有第二离子，所述第二离子与所述第一离子的导电类型相反，所述第二掺杂层与所述第一鳍部宽度方向上的尺寸大于所述鳍部的宽度。所述第一掺杂层与第二掺杂层的接触面积较大，则所述二极管的p‑n结界面面积较大，从而能够降低所述第二掺杂层与所述第一掺杂层之间的接触电阻，改善所形成半导体结构的性能。

Description

半导体结构及其形成方法
技术领域
本发明涉及半导体制造技术领域，尤其涉及一种半导体结构及其形成方法。
背景技术
随着半导体技术的不断进步，半导体器件向着高集成度、高质量的方向发展，半导体器件的特征尺寸相应减小。半导体器件的特征尺寸的减小意味着在同一芯片上可以形成较多的半导体器件。
半导体二极管又称晶体二极管，简称二极管(diode)，是半导体领域常用的电子器件。在二极管内部有一个PN结，这种电子器件按照外加电压的方向，具备单向导电性。二极管中的PN结是由p型半导体和n型半导体形成的p-n结界面。在其界面的两侧形成空间电荷层，构成自建电场。当外加电压等于零时，由于p-n结两边载流子的浓度差引起扩散电流和由自建电场引起的漂移电流相等而处于电平衡状态。几乎在所有的电子电路中，都要用到半导体二极管，它在许多的电路中起着重要的作用，其应用也非常广泛。
随着半导体器件的特征尺寸的减小，使得二极管中p-n结界面的面积逐渐缩小，导致二极管的性能下降。
发明内容
本发明解决的问题是提供一种半导体结构及其形成方法，能够改善半导体结构性能。
为解决上述问题，本发明提供一种半导体结构的形成方法，包括：提供衬底，所述衬底包括二极管区，所述二极管区衬底上具有第一鳍部；在所述第一鳍部中形成第一掺杂层，所述第一掺杂层中具有第一离子；在所述第一掺杂层表面形成第二掺杂层，所述第二掺杂层中具有第二离子，所述第二离子与所述第一离子的导电类型相反，所述第二掺杂层与所述第一掺杂层的接触面在沿第一鳍部宽度方向上的尺寸大于所述第一鳍部的宽度。
可选的，形成所述第一掺杂层的步骤包括：在所述第一鳍部中形成第一外延层；对所述第一外延层进行第一掺杂，在所述第一外延层中掺入第一离子，形成第一掺杂层。
可选的，所述第一外延层的材料为硅、硅锗或碳化硅。
可选的，形成所述第一外延层的步骤包括：在所述第一鳍部中形成开口，所述开口在沿所述第一鳍部宽度方向上贯穿所述第一鳍部；通过第一外延生长工艺在所述开口中形成第一外延层。
可选的，形成所述第二掺杂层的步骤包括：在所述第一掺杂层表面形成第二外延层；对所述第二外延层进行第二掺杂，在所述第二外延层中掺入第二离子，形成第二掺杂层。
可选的，所述第二外延层的材料为硅、碳化硅或硅锗。
可选的，所述第一离子包括磷离子、砷离子或锑离子；所述第二离子包括硼离子或BF2 +离子；或者，所述第一离子包括硼离子或BF2 +离子；所述第二离子包括磷离子、砷离子或锑离子。
可选的，所述衬底还包括第一MOS管区，所述第一MOS管区衬底上具有第二鳍部；还包括：在所述第二鳍部中形成第一源漏掺杂层，所述第一源漏掺杂层中具有第一源漏离子，所述第一源漏离子与所述第一离子的导电类型相同。
可选的，形成所述第一掺杂层和第一源漏掺杂层的步骤包括：分别在所述第一鳍部和第二鳍部中形成第一外延层；对所述第一外延层进行第一掺杂，在所述第二极管区形成第一掺杂层，并在所述第一MOS管区形成第一源漏掺杂层。
可选的，形成所述第一掺杂层之前，还包括：在二极管区和第一MOS管区衬底上形成隔离层；去除部分厚度的二极管区隔离层，使所述二极管区隔离层表面低于所述第一MOS管区隔离层表面，形成隔离结构；形成所述隔离结构之后，去除部分第一鳍部，使所述第一鳍部顶部表面低于所述第二鳍部顶部表面。
可选的，所述衬底还包括第二MOS管区，所述第二MOS管区衬底上具有第三鳍部；所述形成方法还包括：在所述第三鳍部中形成第二源漏掺杂层，所述第二源漏掺杂层中具有第二源漏离子，所述第二源漏离子与所述第二离子的导电类型相同。
可选的，形成所述第二掺杂层和第二源漏掺杂层的步骤包括：在所述第一掺杂层表面和第三鳍部中形成第二外延层；对所述第二外延层进行第二掺杂，在所述第一掺杂层表面形成第二掺杂层，并在所述第三鳍部中形成第二源漏掺杂层。
可选的，形成所述第一掺杂层之前，还包括：在二极管区和第二MOS管区衬底上形成隔离层；去除部分厚度的二极管区隔离层，使所述二极管区隔离层表面低于所述第二MOS管区隔离层表面，形成隔离结构；形成所述隔离结构之后，去除部分第一鳍部，使所述第一鳍部顶部表面低于所述第三鳍部顶部表面。
相应的，本发明还提供一种半导体结构，包括：衬底，所述衬底包括二极管区，所述二极管区衬底上具有第一鳍部；位于所述第一鳍部中的第一掺杂层，所述第一掺杂层中具有第一离子；位于所述第一掺杂层表面的第二掺杂层，所述第二掺杂层中具有第二离子，所述第二离子与所述第一离子的导电类型相反，所述第二掺杂层与所述第一掺杂层的接触面在沿所述第一鳍部宽度方向上的尺寸大于所述第一鳍部的宽度。
可选的，所述第一掺杂层的材料为掺杂有第一离子的硅、硅锗或碳化硅；所述第二掺杂层的材料为掺杂有第二离子的硅、硅锗或碳化硅。
可选的，所述衬底还包括第一MOS管区，所述第一MOS管区衬底上具有第二鳍部；所述半导体结构还包括：位于所述第二鳍部中的第一源漏掺杂层，所述第一源漏掺杂层中具有第一源漏离子，所述第一源漏离子与所述第一离子的导电类型相同。
可选的，所述第一鳍部顶部表面低于所述第二鳍部顶部表面。
可选的，所述衬底还包括第二MOS管区，所述第二MOS管区衬底上具有第三鳍部；所述半导体结构还包括：位于所述第三鳍部中的第二源漏掺杂层，所述第二源漏掺杂层中具有第二源漏离子，所述第二源漏离子与所述第二离子的导电类型相同。
可选的，所述第一鳍部顶部表面低于所述第三鳍部顶部表面。
可选的，所述衬底还包括第一MOS管区，所述第一MOS管区衬底上具有第二鳍部；所述半导体结构还包括：位于所述第二鳍部中的第一源漏掺杂层，所述第一源漏掺杂层中具有第一源漏离子，所述第一源漏离子与所述第一离子的导电类型相同；所述半导体结构还包括：位于所述二极管区、第一MOS管区和第二MOS管区衬底上的隔离结构，所述二极管区隔离结构表面低于所述第一MOS管区隔离结构表面，且所述二极管区隔离结构表面低于所述第二MOS管区隔离结构表面。
与现有技术相比，本发明的技术方案具有以下优点：
本发明技术方案提供的半导体结构的形成方法中，所述第二掺杂层中具有第二离子，所述第二离子与所述第一离子的导电类型相反，则所述第二掺杂层与所述第一掺杂层形成二极管。所述第二掺杂层与所述第一掺杂层之间的接触面为所述二极管的p-n结界面。在所述第一掺杂层表面形成第二掺杂层，所述第二掺杂层与所述第一掺杂层的接触面在沿所述第一鳍部宽度方向上的尺寸大于所述第一鳍部的宽度，所述第一掺杂层与第二掺杂层的接触面积较大。所述第一掺杂层与第二掺杂层的接触面积较大，则所述二极管的p-n结界面面积较大，从而能够增加所述二极管的导通电流，改善所形成半导体结构的性能。
进一步，去除部分厚度的第一鳍部，使所述第一鳍部顶部表面低于所述第一鳍部顶部表面，能够降低后续形成的第二掺杂层顶部表面的高度，从而能够减小所述第二掺杂层的损耗。
本发明技术方案提供的半导体结构中，所述第一掺杂层与第二掺杂层的接触面积较大，则所述二极管的p-n结界面面积较大，从而能够增加所述二极管的导通电流，改善所形成半导体结构的性能。
附图说明
图1是一种半导体结构的结构示意图；
图2至图9是本发明半导体结构的形成方法一实施例各步骤的结构示意图。
具体实施方式
半导体结构的形成方法存在诸多问题，例如：所述半导体结构的性能较差。
现结合一种半导体结构的形成方法，分析所述半导体结构性能较差的原因：
图1是一种半导体结构的结构示意图。
请参考图1，所述半导体结构包括：衬底100，所述衬底100上具有鳍部102，所述鳍部102中具有掺杂区120，所述掺杂区120中具有第一掺杂离子；位于所述鳍部102中的掺杂层110，所述掺杂层110中具有第二掺杂离子，所述第二掺杂离子与所述第一掺杂离子的导电类型相反。
其中，所述掺杂区120与所述掺杂层110形成PN结，所述掺杂区120与掺杂层110的接触面为p-n结界面，所述p-n结界面在垂直于所述鳍部102延伸方向上的尺寸为所述鳍部102的宽度。由于所述鳍部102的宽度较小，所述p-n结界面在沿所述鳍部102宽度方向上的尺寸较小，所述p-n结界面的面积较小，从而导致所述掺杂区120与所述掺杂层110形成的二极管的导通电流较小，导致所述半导体结构的性能较差。
为解决所述技术问题，本发明提供了一种半导体结构的形成方法，包括：在所述第一掺杂层表面形成第二掺杂层，所述第二掺杂层与所述第一掺杂层的接触面在沿第一鳍部宽度方向上的尺寸大于所述第一鳍部的宽度，所述第一掺杂层与第二掺杂层的接触面积较大。所述第一掺杂层与第二掺杂层的接触面积较大，则所述二极管的p-n结界面面积较大，从而能够降低所述第二掺杂层与所述第一掺杂层之间的接触电阻，改善所形成半导体结构的性能。
为使本发明的上述目的、特征和优点能够更为明显易懂，下面结合附图对本发明的具体实施例做详细的说明。
图2至图9是本发明半导体结构的形成方法一实施例各步骤的结构示意图。
请参考图2，提供衬底200，所述衬底200包括二极管区A，所述二极管区A衬底200上具有第一鳍部251。
本实施例中，所述衬底200还包括第一MOS管区B和第二MOS管区C。在其他实施例中，所述衬底可以不包括所述第一MOS管区和第二MOS管区，或者所述衬底包括第一MOS管区和第二MOS管区中的一种。
所述二级管区A用于形成二极管，所述第一MOS管区B用于形成NMOS晶体管，所述第二MOS管区用于形成PMOS晶体管。
所述第一MOS管区衬底200上具有第二鳍部252，所述第二MOS管区衬底200上具有第三鳍部253。
本实施例中，所述衬底200、第一鳍部251、第二鳍部252和第三鳍部253的材料为硅。在其他实施例中，所述衬底、第一鳍部、第二鳍部和第三鳍部的材料包括锗或硅锗。
形成所述第一鳍部251、第二鳍部252、第三鳍部253和衬底200的步骤包括：提供初始衬底；对所述初始衬底进行第一图形化，形成衬底200和位于所述二级管区A衬底200上的第一鳍部251，位于所述第一MOS管区B衬底200上的第二鳍部252，位于所述第二MOS管区C衬底200上的第三鳍部253。
本实施例中，对所述初始衬底进行第一图形化之前，还包括：对所述初始衬底进行离子注入，在所述第一鳍部251中注入掺杂离子，形成掺杂区230。在其他实施例中，还可以在对所述初始衬底进行第一图形化之后，对所述第一鳍部进行离子注入，形成掺杂区。
本实施例中，所述掺杂离子为N型离子，例如磷离子、砷离子或锑离子。在其他实施例中，所述掺杂离子还可以为P型离子，例如硼离子或BF2 +离子。
本实施例中，所述形成方法还包括：在所述第一MOS管区B形成第一阱区231，所述第一阱区231中具有第一阱离子；在所述第二MOS管区C形成第二阱区232，所述第二阱区232中具有第二阱离子。
本实施例中，对所述初始衬底进行第一图形化之前，对所述第一MOS管区B初始衬底进行离子注入，在所述第一MOS管区B初始衬底中注入第一阱离子，形成第一阱区231。在其他实施例中，在对所述初始衬底进行第一图形化之后，对所述第二鳍部进行离子注入，形成所述第一阱区。
本实施例中，所述第一MOS管区B用于形成NMOS晶体管，所述第一阱离子为P型离子，例如硼离子或BF2 +离子。在其他实施例中，所述第一MOS管区用于形成PMOS晶体管，所述第一阱离子为N型离子，例如磷离子、砷离子或锑离子。
本实施例中，对所述初始衬底进行第一图形化之前，对所述第二MOS管区C初始衬底进行离子注入，在所述第二MOS管区C初始衬底中注入第二阱离子，形成第二阱区232。在其他实施例中，在对所述初始衬底进行第一图形化之后，对所述第三鳍部进行离子注入，形成所述第二阱区。
本实施例中，所述第二MOS管区C用于形成PMOS晶体管，所述第二阱离子为N型离子，例如磷离子、砷离子或锑离子。在其他实施例中，所述第二MOS管区用于形成NMOS晶体管，所述第二阱离子为P型离子，例如硼离子或BF2 +离子。
请参考图3，在所述二极管区A、第一MOS管区B和第二MOS管区C衬底200上形成隔离层202，所述隔离层202覆盖所述第一鳍部251、第二鳍部252和第三鳍部253部分侧壁，且所述隔离层202的顶部表面低于所述第一鳍部251、第二鳍部252和第三鳍部253的顶部表面。
所述隔离层202用于后续形成隔离结构，实现相邻第一鳍部251之间的电隔离。
本实施例中，所述隔离层202的材料为氧化硅。在其他实施例中，所述隔离层的材料包括氮化硅或氮氧化硅。
本实施例中，形成所述隔离层202的步骤包括：在所述二极管区A、第一MOS管区B和第二MOS管区C衬底200上形成初始隔离层；对所述初始隔离层进行刻蚀，使所述初始隔离层表面低于所述第一鳍部251、第二鳍部252和第三鳍部253顶部表面，形成隔离层202。
本实施例中，形成所述初始隔离层的工艺包括流体化学气相沉积工艺。在其他实施例中，形成所述初始隔离层的工艺包括物理气相沉积工艺或高深宽比沉积工艺。
本实施例中，对所述初始隔离层进行刻蚀的工艺包括干法刻蚀工艺或湿法刻蚀工艺。
本实施例中，所述二极管区A、第一MOS管区B和第二MOS管区C的隔离层202表面齐平。
请参考图4，去除部分厚度的二极管区A隔离层202(如图3所示)，使所述二极管区A隔离层202表面低于所述第一MOS管区B隔离层202表面，且低于所述第二MOS管区C隔离层202表面，形成隔离结构203。
去除部分厚度的二极管区A隔离层202，使所述二极管区A隔离层202表面低于所述第一MOS管区B隔离层202表面，且低于所述第二MOS管区C隔离层202表面，有利于后续去除部分第一鳍部251。
去除部分厚度的二极管区A隔离层202的工艺包括干法刻蚀工艺或湿法刻蚀工艺。
如果去除的所隔离层202的厚度过小，不利于后续去除部分第一鳍部251；如果去除的隔离层202的厚度过大，容易降低所述隔离结构203的隔离性能。具体的，去除的所隔离层202的厚度为150埃～400埃。
请参考图5，去除部分第一鳍部251，使所述第一鳍部251顶部表面低于所述第二鳍部252顶部表面，且低于所述第三鳍部253顶部表面。
去除部分第一鳍部251，使所述第一鳍部251顶部表面低于所述第二鳍部252和第三鳍部253顶部表面，能够降低后续形成的第二掺杂层222顶部表面的高度，从而能够防止后续对介质层进行平坦化处理过程中损伤第二掺杂层。
本实施例中，去除部分第一鳍部251的工艺包括干法刻蚀工艺或湿法刻蚀工艺。
如果去除的第一鳍部251的高度过小，不利于降低后续形成的第二掺杂层顶部表面的高度，从而不利于减小后续平坦化处理过程中第二掺杂层的损耗；如果去除的第一鳍部251的高度过大，容易使后续形成的二极管区A介质层中产生凹陷，从而降低所述介质层的绝缘性。具体的，去除的第一鳍部251的高度为500埃～1000埃。
请参考图6，图6是在图5沿切割线1-2的剖面图的后续步骤示意图，形成覆盖所述第二鳍部252的第一栅极结构210，所述第一栅极结构210覆盖所述第二鳍部252部分侧壁和顶部表面；形成覆盖所述第三鳍部253的第二栅极结构，所述第二栅极结构覆盖所述第三鳍部253部分侧壁和顶部表面。
本实施例中，形成所述第一栅极结构210和第二栅极结构的步骤包括：形成覆盖第一鳍部251、第二鳍部252和第三鳍部253顶部和侧壁表面的栅极层；对所述栅极层进行第二图形化，去除所述二极管区A的栅极层，并在所述第一MOS管区B形成第一栅极结构210，在所述第二MOS管区C形成第二栅极结构。
请参考图7和图8，图8是图7沿切割线3-4的剖面图，在所述第一鳍部251中形成第一掺杂层221，所述第一掺杂层221中具有第一离子。
本实施例中，所述形成方法还包括：在所述第二鳍部252中形成第一源漏掺杂层241，所述第一源漏掺杂层241中具有第一源漏离子，所述第一源漏离子与所述第一离子的导电类型相同。
在其他实施例中，所述衬底不包括所述第一MOS管区，则所述形成方法不包括形成所述第一源漏掺杂层的步骤。
本实施例中，所述第一源漏掺杂层241位于所述第一栅极结构210两侧的第二鳍部252中。
本实施例中，所述第一掺杂层221用于形成二级管的负极。在其他实施例中，所述第一掺杂层还可以用于形成二级管的正极。
所述第一离子与所述掺杂离子的导电类型相同。
具体的，本实施例中，所述掺杂离子为N型离子，所述第一离子为N型离子。在其他实施例中，所述掺杂离子为P型离子，所述第一离子为P型离子。
本实施例中，所述第一离子包括磷离子、砷离子或锑离子。
本实施例中，形成所述第一掺杂层221和第一源漏掺杂层241的步骤包括：在所述第一鳍部251和第二鳍部252中形成第一外延层；对所述第一外延层进行第一掺杂，在所述第二极管区A形成第一掺杂层221，并在所述第一MOS管区B形成第一源漏掺杂层241。
本实施例中，所述第一掺杂层221与所述第一源漏掺杂层241的材料相同。所述第一掺杂层221与所述第一源漏掺杂层241的材料相同，能够使第一掺杂层221与所述第一源漏掺杂层241在同一工艺中形成，从而能够简化工艺流程。在其他实施例中，所述第一掺杂层与所述第一源漏掺杂层的材料可以不相同。
形成所述第一外延层的步骤包括：在所述第一鳍部251中形成开口，所述开口在所述第一鳍部251宽度方向上贯穿所述第一鳍部251；通过第一外延生长工艺在所述开口中形成第一外延层。
本实施例中，所述第一MOS管区B用于形成NMOS晶体管，所述第一外延层的材料为硅或碳化硅。在其他实施例中，所述第一MOS管区用于形成NMOS晶体管，所述第一外延层的材料还可以为硅锗。
形成第一外延层的工艺包括外延生长工艺。
所述第一掺杂的步骤包括：在所述第一外延生长工艺过程中，对所述第一外延层进行原位掺杂。
在其他实施例中，所述第一掺杂的步骤包括：形成所述第一外延层之后，对所述第一外延层进行第一离子注入，形成所述第一掺杂层和第一源漏掺杂层。
本实施例中，所述第一掺杂层221中第一离子的浓度为1.0E20atoms/cm3～2.5E21atoms/cm3，所述第一源漏掺杂层241中第一源漏离子的浓度为1.0E20atoms/cm3～3.0E21atoms/cm3。
请参考图9，在所述第一掺杂层221表面形成第二掺杂层222，所述第二掺杂层222中具有第二离子，所述第二离子与所述第一离子的导电类型相反，所述第二掺杂层222与所述第一掺杂层221的接触面在沿所述第一鳍部251宽度方向大于所述第一鳍部251的宽度。
需要说明的是，所述第二掺杂层222中具有第二离子，所述第二离子与所述第一离子的导电类型相反，则所述第二掺杂层222与所述第一掺杂层221形成二极管。所述第二掺杂层222与所述第一掺杂层221之间的接触面为所述二极管的p-n结界面。所述第二掺杂层222与所述第一掺杂层221的接触面在沿所述第一鳍部251宽度方向上的尺寸大于所述第一鳍部251的宽度，所述第一掺杂层221与第二掺杂层222的接触面积较大。所述第一掺杂层221与第二掺杂层222的接触面积较大，则所述二极管的p-n结界面面积较大，从而能够增加所述二极管的导通电流，改善所形成半导体结构的性能。
本实施例中，所述形成方法还包括：在所述第三鳍部253中形成第二源漏掺杂层242，所述第二源漏掺杂层242中具有第二源漏离子，所述第二源漏离子与所述第二离子的导电类型相同。
在其他实施例中，所述衬底不包括所述第二MOS管区，则所述形成方法不包括形成所述第二源漏掺杂层的步骤。
本实施例中，所述第二源漏掺杂层242位于所述第二栅极结构两侧的第三鳍部253中。
本实施例中，所述第二掺杂层222用于形成二级管的正极。在其他实施例中，所述第一掺杂层用于形成二极管的正极，所述第二掺杂层还可以用于形成二级管的负极。
所述第二离子与所述第一离子的导电类型相反。
具体的，本实施例中，所述第一离子为N型离子，所述第二离子为P型离子。在其他实施例中，所述第一离子为P型离子，所述第二离子为N型离子。
本实施例中，所述第二离子为硼离子或BF2 +离子。
本实施例中，形成所述第二掺杂层222和第二源漏掺杂层242的步骤包括：在所述第一掺杂层221表面和第三鳍部253中形成第二外延层；对所述第二外延层进行第二掺杂，在所述第一掺杂层221表面形成第二掺杂层222，并在所述第三鳍部253中形成第二源漏掺杂层242。
本实施例中，所述第二掺杂层222与所述第二源漏掺杂层242的材料相同。所述第二掺杂层222与所述第二源漏掺杂层242的材料相同，能够使第二掺杂层222与所述第二源漏掺杂层242在同一工艺中形成，从而能够简化工艺流程。在其他实施例中，所述第二掺杂层与所述第二源漏掺杂层的材料可以不相同。
本实施例中，所述第二MOS管区C用于形成PMOS晶体管，所述第二外延层的材料为硅锗或硅。在其他实施例中，所述第二MOS管区用于形成NMOS晶体管，所述第二外延层的材料还可以为碳化硅。
形成所述第二掺杂的步骤包括：在所述第二外延生长工艺过程中，对所述第二外延层进行原位掺杂。
在其他实施例中，所述第二掺杂的步骤包括：形成所述第二外延层之后，对所述第二外延层进行第二离子注入，形成所述第二掺杂层和第二源漏掺杂层。
本实施例中，所述第二掺杂层222中第二离子的浓度为1.0E21atoms/cm3～2.5E21atoms/cm3，例如1.2E21atoms/cm3；所述第二源漏掺杂层242中第二源漏离子的浓度为7.0E20atoms/cm3～9.0E20atoms/cm3，例如：8.0E20atoms/cm3。
本实施例中，还包括：在所述二极管区A、第一MOS管区B和第二MOS管区C衬底200上形成初始介质层，所述初始介质层覆盖所述第二掺杂层222、第一源漏掺杂层241和第二源漏掺杂层242；对所述初始介质层进行平坦化处理，形成介质层。
继续参考图9，本发明实施例还提供一种半导体结构，包括：衬底200，所述衬底200包括二极管区A，所述二极管区A衬底200上具有第一鳍部251；位于所述第一鳍部251中的第一掺杂层221，所述第一掺杂层221中具有第一离子；位于所述第一掺杂层221表面的第二掺杂层222，所述第二掺杂层222中具有第二离子，所述第二离子与所述第一离子的导电类型相反，所述第二掺杂层222与所述第一掺杂层221的接触面在沿所述第一鳍部251宽度方向上的尺寸大于所述第一鳍部251的宽度。
所述第一掺杂层221的材料为掺杂有第一离子的硅、硅锗或碳化硅；所述第二掺杂层222的材料为掺杂有第二离子的硅、硅锗或碳化硅。
本实施例中，所述衬底200还包括第一MOS管区B，所述第一MOS管区B衬底200上具有第二鳍部252。
所述半导体结构还包括：位于所述第二鳍部252中的第一源漏掺杂层241，所述第一源漏掺杂层241中具有第一源漏离子，所述第一源漏离子与所述第一离子的导电类型相同。在其他实施例中，所述衬底可以不包括第一MOS管区。
本实施例中，所述第一鳍部251顶部表面低于所述第二鳍部252顶部表面。在其他实施例中，所述第一鳍部顶部表面可以齐平于所述第二鳍部顶部表面。
本实施例中，所述衬底200还包括第二MOS管区C，所述第二MOS管区C衬底200上具有第三鳍部253。
所述半导体结构还包括：位于所述第三鳍部253中的第二源漏掺杂层242，所述第二源漏掺杂层242中具有第二源漏离子，所述第二源漏离子与所述第二离子的导电类型相同。在其他实施例中，所述衬底可以不包括第二MOS管区。
本实施例中，所述第一鳍部251顶部表面低于所述第三鳍部253顶部表面。在其他实施例中，所述第一鳍部顶部表面可以齐平于所述第三鳍部顶部表面。
所述半导体结构还包括：位于所述二极管区A、第一MOS管区B和第二MOS管区C衬底200上的隔离结构203。
本实施例中，所述二极管区A的隔离结构203表面低于所述第一MOS管区B隔离结构203表面。在其他实施例中，所述二极管区的隔离结构表面还可以齐平于所述第一MOS管区隔离结构表面。
本实施例中，所述二极管区A的隔离结构203表面低于所述第二MOS管区C隔离结构203表面。在其他实施例中，所述二极管区的隔离结构表面可以齐平于所述第二MOS管区隔离结构表面。
虽然本发明披露如上，但本发明并非限定于此。任何本领域技术人员，在不脱离本发明的精神和范围内，均可作各种更动与修改，因此本发明的保护范围应当以权利要求所限定的范围为准。

Claims (11)

1.一种半导体结构的形成方法，其特征在于，包括：
提供衬底，所述衬底包括二极管区，所述二极管区衬底上具有第一鳍部；
在所述第一鳍部中形成第一掺杂层，所述第一掺杂层中具有第一离子；
在所述第一掺杂层表面形成第二掺杂层，所述第二掺杂层中具有第二离子，所述第二离子与所述第一离子的导电类型相反，所述第二掺杂层与所述第一掺杂层的接触面在沿第一鳍部宽度方向上的尺寸大于所述第一鳍部的宽度；
形成所述第一掺杂层的步骤包括：在所述第一鳍部中形成第一外延层；对所述第一外延层进行第一掺杂，在所述第一外延层中掺入第一离子，形成第一掺杂层；
形成所述第一外延层的步骤包括：在所述第一鳍部中形成开口，所述开口在沿所述第一鳍部宽度方向上贯穿所述第一鳍部；通过第一外延生长工艺在所述开口中形成第一外延层。
2.如权利要求1所述的半导体结构的形成方法，其特征在于，所述第一外延层的材料为硅、硅锗或碳化硅。
3.如权利要求1所述的半导体结构的形成方法，其特征在于，形成所述第二掺杂层的步骤包括：在所述第一掺杂层表面形成第二外延层；对所述第二外延层进行第二掺杂，在所述第二外延层中掺入第二离子，形成第二掺杂层。
4.如权利要求3所述的半导体结构的形成方法，其特征在于，所述第二外延层的材料为硅、碳化硅或硅锗。
5.如权利要求1所述的半导体结构的形成方法，其特征在于，所述第一离子包括磷离子、砷离子或锑离子；所述第二离子包括硼离子或BF2 +离子；
或者，所述第一离子包括硼离子或BF2 +离子；所述第二离子包括磷离子、砷离子或锑离子。
6.如权利要求1所述的半导体结构的形成方法，其特征在于，所述衬底还包括第一MOS管区，所述第一MOS管区衬底上具有第二鳍部；
还包括：在所述第二鳍部中形成第一源漏掺杂层，所述第一源漏掺杂层中具有第一源漏离子，所述第一源漏离子与所述第一离子的导电类型相同。
7.如权利要求6所述的半导体结构的形成方法，其特征在于，形成所述第一掺杂层和第一源漏掺杂层的步骤包括：分别在所述第一鳍部和第二鳍部中形成第一外延层；对所述第一外延层进行第一掺杂，在所述二极管区形成第一掺杂层，并在所述第一MOS管区形成第一源漏掺杂层。
8.如权利要求6所述的半导体结构的形成方法，其特征在于，形成所述第一掺杂层之前，还包括：在二极管区和第一MOS管区衬底上形成隔离层；去除部分厚度的二极管区隔离层，使所述二极管区隔离层表面低于所述第一MOS管区隔离层表面，形成隔离结构；形成所述隔离结构之后，去除部分第一鳍部，使所述第一鳍部顶部表面低于所述第二鳍部顶部表面。
9.如权利要求1所述的半导体结构的形成方法，其特征在于，所述衬底还包括第二MOS管区，所述第二MOS管区衬底上具有第三鳍部；所述形成方法还包括：在所述第三鳍部中形成第二源漏掺杂层，所述第二源漏掺杂层中具有第二源漏离子，所述第二源漏离子与所述第二离子的导电类型相同。
10.如权利要求9所述的半导体结构的形成方法，其特征在于，形成所述第二掺杂层和第二源漏掺杂层的步骤包括：在所述第一掺杂层表面和第三鳍部中形成第二外延层；对所述第二外延层进行第二掺杂，在所述第一掺杂层表面形成第二掺杂层，并在所述第三鳍部中形成第二源漏掺杂层。
11.如权利要求9所述的半导体结构的形成方法，其特征在于，形成所述第一掺杂层之前，还包括：在二极管区和第二MOS管区衬底上形成隔离层；去除部分厚度的二极管区隔离层，使所述二极管区隔离层表面低于所述第二MOS管区隔离层表面，形成隔离结构；形成所述隔离结构之后，去除部分第一鳍部，使所述第一鳍部顶部表面低于所述第三鳍部顶部表面。
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Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111863933B (zh) * 2019-04-29 2023-07-14 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
CN112151606B (zh) * 2019-06-28 2023-09-12 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
US11462648B2 (en) * 2019-12-05 2022-10-04 Globalfoundries U.S. Inc. Fin-based Schottky diode for integrated circuit (IC) products and methods of making such a Schottky diode
US11145550B2 (en) * 2020-03-05 2021-10-12 International Business Machines Corporation Dummy fin template to form a self-aligned metal contact for output of vertical transport field effect transistor
TWI769683B (zh) * 2020-04-29 2022-07-01 台灣積體電路製造股份有限公司 半導體結構與其製造方法
CN113035957A (zh) * 2021-03-01 2021-06-25 泉芯集成电路制造(济南)有限公司 一种鳍式场效应晶体管及半导体器件

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101236995A (zh) * 2007-02-01 2008-08-06 国际商业机器公司 Pin二极管及用于制造pin二极管和形成半导体鳍结构的方法
CN103489863A (zh) * 2012-06-12 2014-01-01 台湾积体电路制造股份有限公司 采用鳍式场效应晶体管工艺的同质结二极管结构
CN103915486A (zh) * 2012-12-31 2014-07-09 台湾积体电路制造股份有限公司 高效率FinFET二极管
CN104253046A (zh) * 2013-06-26 2014-12-31 中芯国际集成电路制造(上海)有限公司 鳍式场效应晶体管及其形成方法
CN106558622A (zh) * 2015-09-24 2017-04-05 中芯国际集成电路制造(上海)有限公司 一种用于esd防护的sti二极管

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8310027B2 (en) * 2008-06-12 2012-11-13 Infineon Technologies Ag Electronic device and manufacturing method thereof
US7700449B2 (en) * 2008-06-20 2010-04-20 Taiwan Semiconductor Manufacturing Company, Ltd. Forming ESD diodes and BJTs using FinFET compatible processes
US9368500B2 (en) * 2013-11-05 2016-06-14 United Microelectronics Corp. Complementary metal-oxide-semiconductor device
US9543438B2 (en) * 2014-10-15 2017-01-10 Taiwan Semiconductor Manufacturing Company, Ltd. Contact resistance reduction technique
CN105826257B (zh) * 2015-01-06 2019-03-12 中芯国际集成电路制造(上海)有限公司 鳍式场效应晶体管及其形成方法
CN106158831B (zh) * 2015-03-24 2018-12-21 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制作方法和电子装置
CN106486378B (zh) * 2015-09-02 2019-07-02 中芯国际集成电路制造(上海)有限公司 鳍式场效应管的形成方法
CN106571359B (zh) * 2015-10-10 2019-08-27 中芯国际集成电路制造(北京)有限公司 静电放电保护结构及其形成方法
US9520392B1 (en) * 2015-11-30 2016-12-13 International Business Machines Corporation Semiconductor device including finFET and fin varactor
CN107026126B (zh) * 2016-02-02 2021-01-26 联华电子股份有限公司 半导体元件及其制作方法
US9613949B1 (en) * 2016-06-27 2017-04-04 United Microelectronics Corp. Bipolar junction transistor and diode
CN107731808B (zh) * 2016-08-12 2020-02-07 中芯国际集成电路制造(上海)有限公司 静电放电保护结构及其形成方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101236995A (zh) * 2007-02-01 2008-08-06 国际商业机器公司 Pin二极管及用于制造pin二极管和形成半导体鳍结构的方法
CN103489863A (zh) * 2012-06-12 2014-01-01 台湾积体电路制造股份有限公司 采用鳍式场效应晶体管工艺的同质结二极管结构
CN103915486A (zh) * 2012-12-31 2014-07-09 台湾积体电路制造股份有限公司 高效率FinFET二极管
CN104253046A (zh) * 2013-06-26 2014-12-31 中芯国际集成电路制造(上海)有限公司 鳍式场效应晶体管及其形成方法
CN106558622A (zh) * 2015-09-24 2017-04-05 中芯国际集成电路制造(上海)有限公司 一种用于esd防护的sti二极管

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