CN112510081B - 一种星用抗辐射沟槽型mos管的加固结构和制备方法 - Google Patents

一种星用抗辐射沟槽型mos管的加固结构和制备方法 Download PDF

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CN112510081B
CN112510081B CN202011380487.2A CN202011380487A CN112510081B CN 112510081 B CN112510081 B CN 112510081B CN 202011380487 A CN202011380487 A CN 202011380487A CN 112510081 B CN112510081 B CN 112510081B
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王晨杰
王英民
刘存生
薛智民
孙有民
王小荷
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Xian Microelectronics Technology Institute
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Abstract

本发明公开了一种星用抗辐射沟槽型MOS场效应晶体管的加固结构和制备方法,结构包括依次堆叠的衬底、缓变外延层、层间介质层和金属层;缓变外延层的表面上依次设置有P+体掺杂区和N+源掺杂区,缓变外延层上设置栅极沟槽;栅极沟槽内部从下至上依次层叠有第一栅氧、浮空多晶栅、第二栅氧和控制多晶栅形成双层屏蔽栅极结构;层间介质层上设置有源极浅沟槽,源极浅沟槽对称分布在栅极沟槽的两侧,源极浅沟槽依次穿过层间介质层、N+源掺杂区和P+体掺杂区,源极浅沟槽的深度不超过栅极沟槽中控制多晶栅的纵向多晶厚度;源极浅沟槽内通过离子注入形成P+深源,P+深源与P+体掺杂区相连接;金属层设置在层间介质层上,并填充源极浅沟槽。

Description

一种星用抗辐射沟槽型MOS管的加固结构和制备方法
技术领域
本发明属于电子技术领域,具体属于一种星用抗辐射沟槽型MOS管的加固结构和制备方法。
背景技术
沟槽型MOS场效应晶体管使用沟槽侧壁形成器件栅极结构,有效减小器件JFET电阻和漏端电阻,并提高栅极结构的单元密度;较平面栅MOS场效应晶体管有更低的导通电阻、更优异的品质因数、更快的开关速率和较低的驱动损耗,更适合卫星、空间飞行器中新型分布式电源系统低功耗、大电流的设计要求,更高的单元密度有利于电源功率模块集成和系统小型化。
但是现有沟槽型MOS场效应晶体管的抗辐射能力不足。沟槽内栅氧厚度和质量不均匀,电场强度高的沟道和漏端交叠处临近沟槽底部栅氧薄弱区域,加厚沟槽底部氧化层虽然解决了器件击穿耐受的可靠性问题,然而辐射环境中沟槽底部的厚栅氧会电离感生大量电荷,引起严重的总剂量效应造成器件电特性退化;此外空间环境重离子入射过程会激活大量空穴并向沟槽底部漂移和扩散,较差的栅氧质量造成沟槽底部易发生单粒子栅穿。对非辐射加固的沟槽型MOS场效应晶体管,有文献报告:30V沟槽型MOS场效应晶体管在栅源偏置5V条件进行γ射线电离辐照试验,总剂量100k rad(Si)时阈值电压变动幅度超过5.5V,严重偏移正常工作允许范围;40V沟槽型MOS场效应晶体管在栅源零偏条件进行LET37MeV•cm2/mg的单粒子试验,直至工作电压降额62.5%时,单粒子栅穿效应才消失。现有技术中存在沟槽型MOS场效应晶体管抗辐射能力不足的缺点。
发明内容
为了解决现有技术中存在的问题,本发明提供一种星用抗辐射沟槽型MOS管的加固结构和制备方法,通过抗辐射工艺制作栅极和源极双沟槽MOS场效应晶体管,其具有较好的抵御电离总剂量效应和单粒子效应的能力。
为实现上述目的,本发明提供如下技术方案:
一种星用抗辐射沟槽型MOS管的加固结构,包括依次堆叠的衬底、缓变外延层、层间介质层和金属层;
所述缓变外延层的表面上依次设置有P+体掺杂区和N+源掺杂区,缓变外延层上设置栅极沟槽;所述栅极沟槽内部从下至上依次层叠有第一栅氧、浮空多晶栅、第二栅氧和控制多晶栅形成双层屏蔽栅极结构;
所述层间介质层上设置有源极浅沟槽,所述源极浅沟槽对称分布在栅极沟槽的两侧,源极浅沟槽依次穿过层间介质层、N+源掺杂区和P+体掺杂区,所述源极浅沟槽的深度不超过栅极沟槽中控制多晶栅的纵向多晶厚度;源极浅沟槽内通过离子注入形成P+深源掺杂区,P+深源掺杂区与P+体掺杂区相连接;金属层设置在层间介质层上,并填充源极浅沟槽。
优选的,所述栅极沟槽深度不小于1.5μm;第一栅氧的厚度不小于100nm;浮空多晶栅的厚度不超过栅极沟槽深度的50%;第二栅氧的厚度不小于100nm;控制多晶栅的厚度不超过栅极沟槽深度的40%。
一种星用抗辐射沟槽型MOS管的加固结构的制备方法,包括以下过程,
步骤1,在衬底上依次进行三次外延层的生长形成缓变外延层;
步骤2,在缓变外延层上通过离子注入形成P+体掺杂区;
步骤3,在含有P+体掺杂区的缓变外延层上通过刻蚀工艺形成栅极沟槽;
步骤4,在栅极沟槽内依次生长第一栅氧、浮空多晶栅、第二栅氧和控制多晶栅10形成双层屏蔽栅极结构;
步骤5,在双层屏蔽栅极结构上通过离子注入形成N+源掺杂区;
步骤6,在N+源掺杂区上通过高密度等离子化学气相淀积形成层间介质层;
步骤7,在层间介质层上通过刻蚀形成源极浅沟槽,源极浅沟槽深度不超过栅极沟槽内控制多晶栅的纵向深度,再通过离子注入形成P+深源掺杂区,P+深源掺杂区与P+体掺杂区相连接;
步骤8,在源极浅沟槽上淀积金属层,形成双沟槽的抗辐射加固单元结构。
优选的,依据单粒子栅穿的临界电场借由半导体器件工艺仿真获得缓变外延层结构的掺杂浓度和外延厚度等参数,使辐射过程中外延结构的最大电压降小于单粒子栅击穿临界电压,实现抗单粒子栅穿加固。
优选的,步骤2中,在缓变外延层通过不低于200KeV能量的硼离子注入形成P+体掺杂区,注入剂量不超过1.5×1013cm-2
优选的,步骤3中,通过极紫外曝光工艺定义栅极沟槽图形,采用TEOS氧化膜作为刻蚀掩蔽层,通过刻蚀形成栅极沟槽,并通过100KeV磷离子注入增强沟槽隔离,离子注入剂量不低于1.0×1012cm-2
优选的,步骤4,在栅极沟槽内通过最高温度不低于850℃的氧化和温度900℃的HTO生长第一栅氧,然后淀积磷掺杂多晶,并通过等离子刻蚀去除表面和沟槽内多余多晶,形成浮空多晶栅,再进行PWL硼离子注入,通过最高温度不低于850℃的氧化和温度900℃的HTO生长第二栅氧,淀积磷掺杂多晶形成控制多晶栅。
优选的,步骤5,通过120KeV砷离子注入形成N+源掺杂区,N+源掺杂区深度不超过0.2μm。
优选的,步骤6中,通过高密度等离子化学气相淀积USG和BPSG形成层间介质层,在层间介质层上采用LTO工艺依次淀积氮化硅膜和氧化硅膜做为源极浅沟槽刻蚀的掩蔽层。
优选的,步骤7,通过DUV曝光定义器件有源区源极浅沟槽和走线栅极孔的图形,通过等离子刻蚀形成源极浅沟槽,源极浅沟槽深度不超过P+体掺杂区的深度;随后分别由能量不低于150KeV的硼离子和能量不超过50KeV的BF2离子注入形成P+深源掺杂区,P+深源掺杂区与P+体掺杂区相连接。
与现有技术相比,本发明具有以下有益的技术效果:
本发明提供一种星用抗辐射沟槽型MOS管的加固结构,通过在栅极沟槽的两侧设置源极沟槽作为源端来调节电场分布,双沟槽MOS场效应晶体管的沟道与漏端交叠于控制栅与中间过渡层交界处,减小了沟槽底部厚栅氧的影响;源极浅沟槽可实现对P+体掺杂区浓度分布精准控制,一方面提高了器件单粒子烧毁的触发电压,另一方面削弱了沟槽底部的电场集中,结合缓变外延层和双层屏蔽栅极结构,使器件能够抵御单粒子栅穿的产生,同时当器件工作电压降为额定电压80%时单粒子栅穿现象消失,器件具备抗单粒子效应的能力。P+深源掺杂区并与P+体掺杂区相连,起到调整体区杂质形貌和浓度分布的作用,并一定程度改善沟道与漏端交叠处电场集中的问题。
本发明提供一种星用抗辐射沟槽型MOS管的加固结构的制备方法,栅极沟槽使用深沟槽屏蔽栅双层结构和低温沟槽栅氧化工艺方法进行电离总剂量效应加固;源极沟槽使用浅沟槽结构和P+体掺杂区扩展工艺方法进行单粒子烧毁加固,提高单粒子烧毁的触发阈值;并通过对屏蔽栅双层结构底层浮空栅的栅氧加固工艺方法和缓变层外延结构,提高抗单粒子栅穿效应的能力。通过采用三层浓度递增的外延层最终形成的缓变外延层,以及沟槽底部栅氧加厚的浮空栅,并通过优化制造流程步骤中高温热过程减少栅氧质量损失,获得较优的抗单粒子栅穿效应能力。
进一步的,在双层屏蔽栅极结构形成过程中通过低温栅氧化和HTO工艺对沟槽底部栅氧厚度T1、浮空栅栅氧厚度W1、控制栅栅氧厚度W2和中间过渡层栅氧厚度T2进行控制,并采用抗辐射氧化方法对栅氧进行辐射加固以减小电离辐射过程的电荷累积。
进一步的,通过源极采用浅槽结构,在栅极沟槽形成前、源极沟槽形成后能量高于150KeV硼离子注入和栅极沟槽形成后能量低于80KeV的硼离子注入,通过高温推结激活杂质,调整P+体掺杂区的杂质分布,以提高单粒子烧毁效应的触发电压。
附图说明
图1为本发明实施例的双沟槽MOS场效应晶体管的单元结构;
图2为本发明实施例步骤1所述的缓变外延层生长;
图3为本发明实施例步骤4所述的P+体掺杂区注入;
图4为本发明实施例步骤5所述的栅极沟槽形成;
图5为本发明实施例步骤6所述的第一栅氧和浮空多晶栅形成;
图6为本发明实施例步骤7所述的第二栅氧形成;
图7为本发明实施例步骤8所述的控制多晶栅淀积;
图8为本发明实施例步骤9所述的控制多晶栅回刻和N+源掺杂区注入;
图9为本发明实施例制作步骤10所述的层间介质层形成以及源极浅沟槽刻蚀所需氮化硅和氧化硅膜掩蔽层的淀积;
图10为本发明实施例制作步骤11所述的源极浅沟槽形成及P+深源掺杂区注入;
图11为本发明实施例制作步骤12所述的金属层形成;
附图中:1为氮化硅膜;2为氧化硅膜;3为钛和氮化钛金属过渡层;4为衬底;5为缓变外延层;6为p+体掺杂区;7为第一栅氧;8为浮空多晶栅;9为第二栅氧;10为控制多晶栅;11为N+源掺杂区;12为层间介质层;13为金属层;14为P+深源掺杂区。
具体实施方式
下面结合具体的实施例对本发明做进一步的详细说明,所述是对本发明的解释而不是限定。
本发明涉及一种星用抗辐射沟槽型MOS管的加固结构和制备方法,通过抗辐射工艺制作栅极和源极双沟槽MOS场效应晶体管,其具有较好的抵御电离总剂量效应和单粒子效应的能力。本发明的星用抗辐射沟槽型MOS场效应晶体管的加固结构针对星用沟槽型MOS场效应晶体管的抗辐射能力需求,提出一种双沟槽的抗辐射加固单元结构,包括栅极沟槽和源极沟槽,其中栅极沟槽使用深沟槽屏蔽栅双层结构和低温沟槽栅氧化工艺方法进行电离总剂量效应加固;源极沟槽使用浅沟槽结构和P+体掺杂区扩展工艺方法进行单粒子烧毁加固,提高单粒子烧毁的触发阈值;并通过对屏蔽栅双层结构底层浮空栅的栅氧加固工艺方法和缓变层外延结构,提高抗单粒子栅穿效应的能力。
本发明提出的沟槽型MOS场效应晶体管结构,在保持器件较小的通态比导通电阻RDS(on)同时获得较好的源区过电流能力,屏蔽栅双层结构栅氧加固有效减小栅电容Cgd能够获得优良的品质因素。
本发明一种星用抗辐射的低导通沟槽型MOS场效应晶体管的加固结构,通过半导体制造工艺方法堆叠N型掺杂衬底4、三层结构缓变外延层5、层间介质层12和金属层13;
在所述的缓变外延层5的表面形成栅极沟槽和源极浅沟槽结构,栅极沟槽内部从下至上依次设置第一栅氧化层7、浮空多晶栅8、第二栅氧化层9和控制多晶栅10,形成屏蔽栅双层结构;源极浅沟槽内部从下至上依次设置P+深源掺杂区14、P+体掺杂区6和N+源区11等离子掺杂区,形成掺杂浓度倒置分布的沟槽型MOS体区结构;
源极浅沟槽在层间介质层12形成后设置,其对称分布于栅极沟槽的左右两侧,源极浅沟槽依次穿过层间介质层12、N+源掺杂区11、P+体掺杂区6,其刻蚀深度不超过栅极沟槽结构控制多晶栅10的多晶厚度;P+深源掺杂区通过源极沟槽底部的离子注入形成并于P+体掺杂区6相连接;金属层13设置于层间介质层12上方,并填充源极浅沟槽。
针对沟槽型MOS场效应晶体管的抗辐射能力较弱的问题,本发明辐射加固的N型双沟槽MOS场效应晶体管单元结构,工作电压不超过100V,采用包含浮空栅和控制栅的双层屏蔽栅极结构,在实施过程中通过低温栅氧化和HTO工艺对沟槽底部栅氧厚度T1、浮空栅栅氧厚度W1、控制栅栅氧厚度W2和中间过渡层栅氧厚度T2进行控制,并采用抗辐射氧化方法对栅氧进行辐射加固以减小电离辐射过程的电荷累积;源极采用浅槽结构,通过栅极沟槽形成前、源极沟槽形成后能量高于150KeV硼离子注入和栅极沟槽形成后能量低于80KeV的硼离子注入,通过高温推结激活杂质,调整P+体掺杂区的杂质分布,以提高单粒子烧毁效应的触发电压;采用三层浓度递增的外延层最终形成的缓变外延结构,以及沟槽底部栅氧加厚的浮空栅,并通过优化制造流程步骤中高温热过程减少栅氧质量损失,获得较优的抗单粒子栅穿效应能力。
实现MOS场效应晶体管双沟槽单元结构的工艺加固制作流程如下:
步骤1. 在电阻率(0.002~0.005)Ω•cm的N型硅衬底4上依次进行三次磷掺杂外延层的生长形成缓变外延层5,根据如下公式(1)得到单粒子栅穿的临界电压,通过工艺仿真调节三层外延层的掺杂浓度和厚度在特定的辐射线性能量传递值下,使三层缓变外延结构最大电压降小于临界电压。
Figure SMS_1
(1)
式中,LET为线性能量传递值;EOX_BR击穿电场,TOX氧化层厚度。
缓变外延层5结构中顶层外延的浓度和电阻率仍需要满足MOS场效应晶体管的额定漏源击穿电压的设计要求。
步骤2. 通过场氧化、光刻定义、刻蚀和离子注入形成MOS场效应晶体管的终端场限环结构。
步骤3. 通过场氧化、光刻定义、刻蚀形成MOS场效应晶体管的走线和器件有源区;走线沿场氧分布,场氧厚度不小于500nm。
步骤4. 在缓变外延层5表面生长厚度不大于70nm的垫氧层,对整个器件有源区进行硼离子注入形成P+体掺杂区6,硼离子注入能量不低于200KeV。
步骤5. 在形成P+体掺杂区6的缓变外延层5上通过DUV曝光定义器件有源区栅极沟槽图形,采用低压化学气相淀积的TEOS氧化膜作为掩蔽层,刻蚀形成深度不小于1.5μm栅极沟槽,通过整个器件有源区的磷离子注入实现沟槽隔离,注入能量不超过100KeV;随后通过湿法腐蚀去除TEOS氧化膜。
步骤6. 通过最高温度不低于1000℃氧化在栅极沟槽内形成牺牲氧化层以修复刻蚀过程对硅材料的损伤,并通过湿法腐蚀去除牺牲氧化层;清洗后通过最高温度不低于850℃的氧化和温度900℃的HTO生长第一栅氧7,沟槽底部栅氧厚度T1不小于100nm;栅极沟槽内淀积磷掺杂多晶,并通过等离子刻蚀去除表面和沟槽内多余多晶,形成浮空多晶栅8,浮空多晶栅8的厚度不超过栅极沟槽深度的50%。
步骤7. 器件有源区PWL硼离子注入,注入能量不超过80KeV;清洗后通过最高温度不低于850℃的氧化和温度900℃的HTO生长第二栅氧9,并进行最高温度不低于850℃的N2O退火,中间过渡层栅氧厚度T2不小于100nm。
步骤8. 栅极沟槽内淀积磷掺杂多晶形成控制多晶栅10,淀积后器件有源区和走线场氧表面多晶厚度不小于550nm。
步骤9. 通过DUV曝光定义走线多晶图形,随后由等离子刻蚀去除器件有源区表面和栅极沟槽表面的掺杂多晶,栅极沟槽内多晶回刻深度0.22μm,控制多晶栅10的厚度不超过栅极沟槽深度的40%;随后由能量120 KeV砷离子注入形成N+源掺杂区11;通过900℃的RTO快速热氧化退火激活磷掺杂多晶和N+源掺杂区11杂质。
步骤10. 通过高密度等离子化学气相淀积USG和BPSG形成层间介质层12,介质膜厚度不超过600nm。随后在层间介质层12上采用低温的LTO工艺依次淀积氮化硅膜1和氧化硅膜2做为后续源极浅沟槽刻蚀的掩蔽层,氮化硅膜厚度不超过80nm,氧化膜不超过200nm。
步骤11. 通过DUV曝光定义器件有源区源极浅沟槽和走线栅极孔的图形,等离子刻蚀形成源极浅沟槽,源极浅沟槽深度不超过控制多晶栅10的纵向厚度;随后进行P+深源掺杂区14注入,分别由能量不低于150KeV的硼离子和能量不超过50KeV的BF2离子注入,形成P+深源掺杂区并与P+体掺杂区6相连,起到调整体区杂质形貌和浓度分布的作用,并一定程度改善沟道与漏端交叠处电场集中的问题;随后通过湿法腐蚀去除氮化硅膜1和氧化硅膜2掩蔽层,清洗后通过最高温度不超过900℃的推结工艺激活P+深源掺杂区杂质并对层间介质层12进行致密。
步骤12. 清洗后在源极浅沟槽中淀积厚度不超过90nm的钛和氮化钛金属过渡层3,并通过850℃的RTA快速热退火形成欧姆接触;随后淀积铝硅铜合金,并由光刻定义、湿法腐蚀和等离子刻蚀形成栅极和源极金属图形;并进行420℃的合金退火。介质层表面金属厚度不小于4μm。
后续步骤与传统功率MOS场效应晶体管制造方法相同。
本发明提出的一种双沟槽单元结构的MOS场效应晶体管,其栅极结构由双层屏蔽栅构成,而源极浅沟槽结构设计更适合对P+体掺杂区浓度分布进行调整,该单元结构是对常规沟槽型功率MOS场效应晶体管的改进,使其具备较好的抗辐射能力。双沟槽MOS场效应晶体管的沟道与漏端交叠于控制栅与中间过渡层交界处,减小了沟槽底部厚栅氧的影响,通过γ射线辐射验证其抗电离总剂量能力达到100k rad(Si);源区浅槽可实现对P+体掺杂区浓度分布精准控制,一方面提高了器件单粒子烧毁的触发电压,另一方面削弱了沟槽底部的电场集中,结合缓变外延结构和厚栅氧浮空栅设计,使器件能够抵御单粒子栅穿的产生,通过地面重离子辐照试验证实,在入射粒子LET值达到66.5MeV•cm2/mg时抗单粒子烧毁,同时当器件工作电压降为额定电压80%时单粒子栅穿现象消失,器件具备抗单粒子效应的能力。此外,因双沟槽单元结构MOS场效应晶体管的单元密度较高,与对标的抗辐射平面栅MOS场效应晶体管相比,栅电容相同时其通态比导通电阻RDS(on)减小了75%。
本发明使用的低温栅氧化、P+体掺杂区扩展等工艺加固方法和辐射加固工艺流程是基于0.25μm硅基MOS工艺实施的,与抗辐射平面栅MOS场效应晶体管的制造工艺有良好的兼容性,研制单位能够迅速开展抗辐射沟槽型功率MOS场效应晶体管的设计制造。
本发明针对星用MOS场效应晶体管应用,提出一种双沟槽辐射加固的MOS场效应晶体管单元结构,包括栅极沟槽和源极浅沟槽;其中栅极沟槽使用屏蔽栅双层结构和低温沟槽栅氧化工艺方法进行电离总剂量效应加固;源极浅沟槽使用浅槽结构和P+体掺杂区扩展工艺方法进行单粒子烧毁加固,提高单粒子烧毁的触发阈值;并通过对屏蔽栅双层结构底层浮空栅的栅氧加固工艺方法和缓变外延层结构提高抗单粒子栅穿效应的能力。此外,本发明提出的沟槽型MOS场效应晶体管结构,在保持器件较小的通态比导通电阻RDS(on)的同时具有较好的源极过电流能力,屏蔽栅双层结构栅氧加固有效减小了栅电容Cgd具备优良的品质因数。
实施例
本实施例是采用本发明所述双沟槽MOS场效应晶体管单元结构,制作N型100V功率MOS场效应晶体管器件,其具体工艺步骤如下:
步骤1. 如图2所示,采用电阻率(0.002~0.003)Ω•cm的N<100>硅片作为衬底4材料,三层外延淀积要求为:
外延层 厚度(μm) 电阻率(Ω·cm)
外延1 18.0±2.0 0.15±0.01
外延2 3.0±0.3 1.5±0.1
外延3 10.0±0.8 2.50±0.3
步骤2. 终端采用场限环和场板结合的结构,设计耐压120V,光刻定义并使用700nm的场氧1作为掩蔽层,80KeV硼离子注入形成场限环,峰值浓度3.0×1015cm-3
步骤3. 去除场氧1后再氧化形成300nm的场氧2做为器件有源区隔离场氧,走线沿场氧进行分布。
步骤4. 如图3所示,器件有源区裸硅表面生长50nm垫氧膜后通过200KeV硼离子注入形成P+体掺杂区,注入剂量不超过1.5×1013cm-2
步骤5. 双沟槽单元尺寸不小于2.5μm,其中栅极沟槽宽度不小于1.0μm,沟槽间距不小于1.5μm。如图4所示,通过DUV曝光工艺定义栅极沟槽图形,TEOS氧化膜作为刻蚀掩蔽层,沟槽深度不小于2.5μm;通过100KeV磷离子注入增强沟槽隔离,注入剂量不低于1.0×1012cm-2
步骤6. 如图5~图8所示,浮空栅和控制栅均由950℃湿氧氧化化和900℃HTO氧化工艺形成,并进行950℃的N2O退火,沟槽底部栅氧厚度不小于110nm,中间过渡层栅氧厚度不小于100nm,浮空栅栅氧厚度80nm,多晶厚度不超过0.8μm;控制栅栅氧厚度50nm,多晶厚度不超0.6μm。浮空栅形成后通过60KeV硼离子注入第一次调整P+体掺杂区浓度分布,注入剂量不低于5.0×1012cm-2
步骤7. 如图8所示,通过120KeV砷离子注入形成N+源掺杂区,源区深度不超过0.2μm,其峰值浓度分布在外延层表面不小于1.0×1014cm-3;通过900℃的RTO快速热氧化退火激活掺杂多晶和N+源。
步骤8. 如图9和图10所示,层间介质层由USG和BPSG构成,经过900℃推结致密后厚度为550nm;源极浅沟槽宽度不超过1.5μm,其深度不超过1.0μm,通过浅槽内160KeV硼离子和40KeV BF2离子注入对P+体掺杂区浓度分布进行第二次调整,形成倒置梯形的P+体掺杂区杂质分布形貌,杂质峰值浓度不小于1.2×1015cm-3分布在P+深源掺杂区。
步骤9. 如图11所示,淀积90nm钛和氮化钛过渡层,并淀积介质层表面金属最小厚度超过4.0μm的铝硅铜合金;通过光刻定义,湿法腐蚀和等离子刻蚀形成栅极和源极金属图形;并进行420℃的合金退火。
后续步骤与传统功率MOS场效应晶体管制造方法相同。
通过本实施例制作的N型100V双沟槽MOS场效应晶体管,具有110V的额定雪崩击穿电压,其栅氧耐压超过40V,阈值电压辐射过程前后均在1.5V~4.5V范围内,漏源漏电流小于10μA,通态比导通电阻为120mΩ•mm-2,输出电流达75A;具备抗辐射能力:抗电离总剂量达到100k rad(Si),;入射粒子LET 51.3MeV·cm2/mg、器件栅源零偏置时抗单粒子烧毁,工作电压降额至80%额定击穿时抗单粒子栅穿。

Claims (6)

1.一种星用抗辐射沟槽型MOS管的加固结构,其特征在于,包括依次堆叠的衬底(4)、缓变外延层(5)、层间介质层(12)和金属层(13);
所述缓变外延层(5)的表面上依次设置有P+体掺杂区(6)和N+源掺杂区(11),缓变外延层(5)上设置栅极沟槽;所述栅极沟槽内部从下至上依次层叠有第一栅氧(7)、浮空多晶栅(8)、第二栅氧(9)和控制多晶栅(10)形成双层屏蔽栅极结构;
所述层间介质层(12)上设置有源极浅沟槽,所述源极浅沟槽对称分布在栅极沟槽的两侧,源极浅沟槽依次穿过层间介质层(12)、N+源掺杂区(11)和P+体掺杂区(6),所述源极浅沟槽的深度不超过栅极沟槽中控制多晶栅(10)的纵向多晶厚度;源极浅沟槽内通过离子注入形成P+深源掺杂区(14),P+深源掺杂区(14)与P+体掺杂区(6)相连接;金属层(13)设置在层间介质层(12)上,并填充源极浅沟槽;
所述栅极沟槽深度不小于1.5μm;第一栅氧(7)的厚度不小于100nm;浮空多晶栅(8)的厚度不超过栅极沟槽深度的50%;第二栅氧(9)的厚度不小于100nm;控制多晶栅(10)的厚度不超过栅极沟槽深度的40%。
2.一种星用抗辐射沟槽型MOS管的加固结构的制备方法,其特征在于,包括以下过程,
步骤1,在衬底(4)上依次进行三次外延层的生长形成缓变外延层(5);
步骤2,在缓变外延层(5)上通过离子注入形成P+体掺杂区(6);
步骤3,在含有P+体掺杂区(6)的缓变外延层(5)上通过刻蚀工艺形成栅极沟槽;通过极紫外曝光工艺定义栅极沟槽图形,采用TEOS氧化膜作为刻蚀掩蔽层,通过刻蚀形成栅极沟槽,并通过100KeV磷离子注入增强沟槽隔离,离子注入剂量不低于1.0×1012cm-2
步骤4,在栅极沟槽内依次生长第一栅氧(7)、浮空多晶栅(8)、第二栅氧(9)和控制多晶栅10形成双层屏蔽栅极结构;在栅极沟槽内通过最高温度不低于850℃的氧化和温度900℃的HTO生长第一栅氧(7),然后淀积磷掺杂多晶,并通过等离子刻蚀去除表面和沟槽内多余多晶,形成浮空多晶栅(8),再进行PWL硼离子注入,通过最高温度不低于850℃的氧化和温度900℃的HTO生长第二栅氧(9),淀积磷掺杂多晶形成控制多晶栅(10);
步骤5,在双层屏蔽栅极结构上通过离子注入形成N+源掺杂区(11);
步骤6,在N+源掺杂区(11)上通过高密度等离子化学气相淀积形成层间介质层(12);
步骤7,在层间介质层(12)上通过刻蚀形成源极浅沟槽,源极浅沟槽深度不超过栅极沟槽内控制多晶栅(10)的纵向深度,再通过离子注入形成P+深源掺杂区(14), P+深源掺杂区(14)与P+体掺杂区(6)相连接;
步骤8,在源极浅沟槽上淀积金属层(13),形成双沟槽的抗辐射加固单元结构;
依据单粒子栅穿的临界电场借由半导体器件工艺仿真获得缓变外延层结构的掺杂浓度和外延厚度参数,使辐射过程中外延结构的最大电压降小于单粒子栅击穿临界电压,实现抗单粒子栅穿加固。
3.根据权利要求2所述的一种星用抗辐射沟槽型MOS管的加固结构的制备方法,其特征在于,步骤2中,在缓变外延层(5)通过不低于200KeV能量的硼离子注入形成P+体掺杂区(6),注入剂量不超过1.5×1013cm-2
4.根据权利要求2所述的一种星用抗辐射沟槽型MOS管的加固结构的制备方法,其特征在于,步骤5,通过120KeV砷离子注入形成N+源掺杂区(11),N+源掺杂区(11)深度不超过0.2μm。
5.根据权利要求2所述的一种星用抗辐射沟槽型MOS管的加固结构的制备方法,其特征在于,步骤6中,通过高密度等离子化学气相淀积USG和BPSG形成层间介质层(12),在层间介质层(12)上采用LTO工艺依次淀积氮化硅膜(1)和氧化硅膜(2)做为源极浅沟槽刻蚀的掩蔽层。
6.根据权利要求2所述的一种星用抗辐射沟槽型MOS管的加固结构的制备方法,其特征在于,步骤7,通过DUV曝光定义器件有源区源极浅沟槽和走线栅极孔的图形,通过等离子刻蚀形成源极浅沟槽,源极浅沟槽深度不超过P+体掺杂区(6)的深度;随后分别由能量不低于150KeV的硼离子和能量不超过50KeV的BF2离子注入形成P+深源掺杂区(14),P+深源掺杂区(14)与P+体掺杂区(6)相连接。
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101385148A (zh) * 2006-03-10 2009-03-11 万国半导体股份有限公司 用肖特基源极触点实施的隔离栅极沟槽式金属氧化物半导体场效应晶体管记忆胞
CN101536163A (zh) * 2005-06-10 2009-09-16 飞兆半导体公司 电荷平衡场效应晶体管
CN103904119A (zh) * 2014-03-28 2014-07-02 中国科学院微电子研究所 一种具有纵向屏蔽栅的Trench MOSFET及其加工方法
CN108305900A (zh) * 2017-12-29 2018-07-20 重庆中科渝芯电子有限公司 一种功率mosfet的缓变掺杂材料片及其制造方法
CN110429077A (zh) * 2019-08-23 2019-11-08 杭州电子科技大学 一种适用于功率半导体器件的抗单粒子烧毁结构

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120037983A1 (en) * 2010-08-10 2012-02-16 Force Mos Technology Co., Ltd. Trench mosfet with integrated schottky rectifier in same cell
US20120080748A1 (en) * 2010-09-30 2012-04-05 Force Mos Technology Co., Ltd. Trench mosfet with super pinch-off regions
CN109166918A (zh) * 2018-08-30 2019-01-08 中国科学院微电子研究所 一种绝缘栅双极晶体管及其制作方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101536163A (zh) * 2005-06-10 2009-09-16 飞兆半导体公司 电荷平衡场效应晶体管
CN101385148A (zh) * 2006-03-10 2009-03-11 万国半导体股份有限公司 用肖特基源极触点实施的隔离栅极沟槽式金属氧化物半导体场效应晶体管记忆胞
CN103904119A (zh) * 2014-03-28 2014-07-02 中国科学院微电子研究所 一种具有纵向屏蔽栅的Trench MOSFET及其加工方法
CN108305900A (zh) * 2017-12-29 2018-07-20 重庆中科渝芯电子有限公司 一种功率mosfet的缓变掺杂材料片及其制造方法
CN110429077A (zh) * 2019-08-23 2019-11-08 杭州电子科技大学 一种适用于功率半导体器件的抗单粒子烧毁结构

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