JPWO2019123601A1 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JPWO2019123601A1 JPWO2019123601A1 JP2019559958A JP2019559958A JPWO2019123601A1 JP WO2019123601 A1 JPWO2019123601 A1 JP WO2019123601A1 JP 2019559958 A JP2019559958 A JP 2019559958A JP 2019559958 A JP2019559958 A JP 2019559958A JP WO2019123601 A1 JPWO2019123601 A1 JP WO2019123601A1
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Abstract
Description
(構成)
図1は、本実施の形態1に係るMOSFET501(半導体装置)のユニットセルUCにおける半導体層(図2および図3におけるエピタキシャル層70)の構成を概略的に示す上面図である。なお、図1、および、後述する他の上面図において、図を見やすくするために、ウェルコンタクト領域25にはドット模様が付されている。図2および図3のそれぞれは、MOSFET501の構成を、図1の線II−IIおよび線III−IIIに沿う断面で概略的に示す断面図である。MOSFET501の能動領域には、マトリクス状に配置された複数のユニットセルUCが設けられており、図1は、そのうちのひとつを示している。図1においてはユニットセルUCが四角形の形状を有しているが、ユニットセルの形状は他の形状であってもよく、例えば六角形、八角形または円形でもよい。能動領域の外側には、終端領域(図示せず)が設けられている。
図4は、図1の変形例のMOSFET501S1(半導体装置)を示す上面図である。MOSFET501S1は、ストライプ形状(櫛形形状)で配置された複数のユニットセルUCが設けられた構造を有している。図4は、複数のユニットセルUCのうちのひとつを示している。各ユニットセルUCはストライプ形状が延びる方向(図中、縦方向)に延在している。複数のユニットセルUCは、この延在方向に交差する方向(図4における横方向)に配列されている。
次に、MOSFET501の製造方法の例について、図9〜図13の断面図を参照しつつ、以下に説明する。なお、図9〜図11および図13の視野は図2の視野に対応しており、図12の視野は図3の視野に対応している。
図14は、本実施の形態2に係るMOSFET502(半導体装置)の構成を、図2と同様の視野で概略的に示す断面図である。MOSFET502においては、ソース抵抗領域15は、ウェル領域20上に配置された高濃度部分15H(第1の部分)と、高濃度部分15H上に配置された低濃度部分15L(第2の部分)とを有している。高濃度部分15Hは低濃度部分15Lとウェル領域20との間に位置している。高濃度部分15Hの抵抗率は低濃度部分15Lの抵抗率よりも低い。これらの抵抗率を得るためには、高濃度部分15Hの不純物濃度が低濃度部分15Lの不純物濃度よりも高くされればよい。
図15は、本実施の形態3に係るMOSFET503(半導体装置)のユニットセルUCにおける半導体層(図16および図17におけるエピタキシャル層70)の構成を概略的に示す上面図である。図16および図17のそれぞれは、MOSFET503の構成を、図15の線XVI−XVIおよび線XVII−XVIIに沿う断面で概略的に示す断面図である。
(構成)
図19は、本実施の形態4に係るMOSFET504(半導体装置)のユニットセルUCにおける半導体層(図20および図21におけるエピタキシャル層70)の構成を概略的に示す上面図である。図20および図21のそれぞれは、MOSFET504の構成を、図19の線XX−XXおよび線XXI−XXIに沿う断面で概略的に示す断面図である。
MOSFET504の製造方法について、以下に説明する。
図25は、本実施の形態5に係るMOSFET505(半導体装置)のユニットセルUCにおける半導体層(図26および図27におけるエピタキシャル層70)の構成を概略的に示す上面図である。図26および図27のそれぞれは、MOSFET505の構成を、図25の線XXVI−XXVIおよび線XXVII−XXVIIに沿う断面で概略的に示す断面図である。
図29は、本実施の形態6に係るMOSFET506(半導体装置)の構成を、図26と同様の視野で概略的に示す断面図である。MOSFET506は、トレンチTRの底部に設けられp型を有するトレンチ底部保護領域21を有している。これにより、トレンチTRの底部へ印加される電界が抑制される。よってゲート絶縁膜30のリーク電流が低減する。よってMOSFETの信頼性を高めることができる。
Claims (15)
- チャネル(CH)を有する半導体装置(501、501S1、501S2、501R、501W、501T、502、503、503D、504、504U、505、505S、506、506D、506D1〜506D5)であって、
第1の主面(M1)と、前記第1の主面(M1)と反対の第2の主面(M2)とを有し、前記第2の主面(M2)に平行な面内方向を有する半導体基板(1a、1b)と、
前記半導体基板(1a、1b)の前記第1の主面(M1)上に設けられたドレイン電極(50)と
前記半導体基板(1a、1b)の前記第2の主面(M2)上に設けられ、第1の導電型を有するドリフト層(2)と、
前記ドリフト層(2)上に設けられ、前記第1の導電型と異なる第2の導電型を有し、前記半導体装置(501、501S1、501S2、501R、501W、501T、502、503、503D、504、504U、505、505S、506、506D、506D1〜506D5)の前記チャネル(CH)をなす部分を有するウェル領域(20)と、
前記ウェル領域(20)上に設けられ、前記第2の導電型を有し、前記ウェル領域(20)の抵抗率よりも低い抵抗率を有するウェルコンタクト領域(25)と、
前記ウェル領域(20)によって前記ドリフト層(2)から隔てられて前記ウェル領域(20)上に設けられ、前記第1の導電型を有するソースコンタクト領域(12)と、
前記ウェル領域(20)によって前記ドリフト層(2)から隔てられて前記ウェル領域(20)上に設けられ、前記面内方向において前記ソースコンタクト領域(12)に隣接し、前記第1の導電型を有し、前記ソースコンタクト領域(12)のシート抵抗に比して高いシート抵抗を有するソース抵抗領域(15)と、
前記ウェル領域(20)の前記チャネル(CH)を覆うゲート絶縁膜(30)と、
前記ゲート絶縁膜(30)上に設けられたゲート電極(35)と、
ソースコンタクト領域(12)とウェルコンタクト領域(25)とソース抵抗領域(15)とに接し、前記チャネル(CH)へ少なくとも前記ソース抵抗領域(15)を介してつながるソース電極(40)と、
を備える、半導体装置(501、501S1、501S2、501R、501W、501T、502、503、503D、504、504U、505、505S、506、506D、506D1〜506D5)。 - 前記半導体装置(501、501S1、501S2、501R、501W、501T、502、503、503D、504、504U、505、505S、506、506D、506D1〜506D5)は、前記ゲート絶縁膜(30)を含む絶縁層(IL)を有しており、前記絶縁層(IL)には、前記ソース電極(40)が埋め込まれたコンタクトホール(SC)が設けられており、前記コンタクトホール(SC)は、前記ソース抵抗領域(15)を横切る外周を有している、請求項1に記載の半導体装置(501、501S1、501S2、501R、501W、501T、502、503、503D、504、504U、505、505S、506、506D、506D1〜506D5)。
- 前記チャネル(CH)は前記面内方向に沿って延びていることを特徴とする、請求項1または2に記載の半導体装置(501、501S1、501S2、501R、501W、501T、502、503、503D)。
- 前記ウェル領域(20)を貫通して前記ドリフト層(2)に達する側壁を有するトレンチ(TR)が設けられており、前記チャネル(CH)は前記側壁上に配置されていることを特徴とする、請求項1または2に記載の半導体装置(504、504U、505、505S、506、506D、506D1〜506D5)。
- 前記トレンチ(TR)の底部に設けられ、前記第2の導電型を有するトレンチ底部保護領域(21)と、
前記トレンチ(TR)の前記側壁の一部に設けられ、前記トレンチ底部保護領域(21)と前記ウェル領域(20)とに接し、前記第2の導電型を有するトレンチ側壁保護領域(22)と、
をさらに備える、請求項4に記載の半導体装置(506D、506D1〜506D5)。 - 平面視において、前記トレンチ側壁保護領域(22)の少なくとも一部は、前記ウェルコンタクト領域(25)と隣接するかまたは重なるように配置されていることを特徴とする、請求項5に記載の半導体装置(506D、506D1〜506D5)。
- 前記ソース抵抗領域(15)に隣接し、前記ソースコンタクト領域(12)から離れ、前記ウェル領域(20)によって前記ドリフト層(2)から隔てられ、前記第1の導電型を有するソースエクステンション領域(13)をさらに備え、前記ソース抵抗領域(15)は前記ソースエクステンション領域(13)を介して前記チャネル(CH)へつながっていることを特徴とする、請求項1から6のいずれか1項に記載の半導体装置(501、501S1、501S2、501R、501W、501T、502、504、504U)。
- 前記ソース抵抗領域(15)および前記ウェルコンタクト領域(25)の各々は、面内方向において、前記ソースコンタクト領域(12)と前記ソースエクステンション領域(13)との間に配置されていることを特徴とする、請求項7に記載の半導体装置(501、501S1、501S2、501R、501W、501T、502、504、504U)。
- 前記面内方向において前記ソース抵抗領域(15)は前記ウェルコンタクト領域(25)に隣接していることを特徴とする、請求項1から8のいずれか1項に記載の半導体装置(501、501S1、501S2、501R、501W、501T、502、503、503D、504、504U、505、505S、506、506D、506D1〜506D5)。
- 前記ソース抵抗領域(15)は、前記ウェル領域(20)上に配置された第1の部分(15b)と、前記第1の部分(15b)上に配置された第2の部分(15)とを有しており、前記第1の部分(15b)の抵抗率は前記第2の部分(15)の抵抗率よりも低いことを特徴とする、請求項1から9のいずれか1項に記載の半導体装置(502)。
- 前記ソース抵抗領域(15)上に設けられ、前記ソース抵抗領域(15)と前記ソース電極(40)との間を隔て、前記第2の導電型を有する離間層(15R)をさらに備える、請求項1から10のいずれか1項に記載の半導体装置(501R)。
- 前記ウェルコンタクト領域(25)は、前記ゲート絶縁膜(30)のみを介して前記ゲート電極(35)に接する部分を有しないように配置されていることを特徴とする、請求項1から11のいずれか1項に記載の半導体装置(501、501S1、501S2、501R、501W、501T、502、503D、504、504U、505、505S、506、506D、506D1〜506D5)。
- 前記ソース電極(40)と前記ソース抵抗領域(15)との間のコンタクト抵抗は、前記ソース電極(40)と前記ソースコンタクト領域(12)との間のコンタクト抵抗より、10倍以上大きいことを特徴とする、請求項1から12のいずれか1項に記載の半導体装置(501、501S1、501S2、501R、501W、501T、502、503、503D、504、504U、505、505S、506、506D、506D1〜506D5)。
- 前記半導体装置(501S2、506D3〜506D5)は、ストライプ形状で配置された複数のユニットセル(UC)を有し、
前記ウェルコンタクト領域(25)は、前記ストライプ形状が延びる方向に交差する方向において前記ソースコンタクト領域(12)を介して互いに対向する部分を有し、前記対向する部分の中心は前記ストライプ形状が延びる方向においてずらされている、請求項1から13のいずれか1項に記載の半導体装置(501S2、506D3〜506D5)。 - 前記半導体基板(1a、1b)、前記ドリフト層(2)、および前記ウェル領域(20)は、炭化珪素からなる、請求項1から14のいずれか1項に記載の半導体装置(501、501S1、501S2、501R、501W、501T、502、503、503D、504、504U、505、505S、506、506D、506D1〜506D5)。
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JP6728097B2 (ja) * | 2017-04-24 | 2020-07-22 | 株式会社東芝 | 半導体装置、半導体装置の製造方法、インバータ回路、駆動装置、車両、及び、昇降機 |
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- 2017-12-21 DE DE112017008299.4T patent/DE112017008299T5/de active Pending
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JPH09321290A (ja) * | 1996-05-30 | 1997-12-12 | Fuji Electric Co Ltd | 絶縁ゲートバイポーラトランジスタを備えた半導体装置 |
WO2013172079A1 (ja) * | 2012-05-15 | 2013-11-21 | 三菱電機株式会社 | 半導体装置及びその製造方法 |
WO2016063644A1 (ja) * | 2014-10-20 | 2016-04-28 | 三菱電機株式会社 | 半導体装置 |
JP2017112161A (ja) * | 2015-12-15 | 2017-06-22 | 三菱電機株式会社 | 半導体装置 |
WO2017126472A1 (ja) * | 2016-01-20 | 2017-07-27 | ローム株式会社 | 半導体装置 |
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WO2019123601A1 (ja) | 2019-06-27 |
US11309416B2 (en) | 2022-04-19 |
CN111512448A (zh) | 2020-08-07 |
CN111512448B (zh) | 2023-04-28 |
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