JPWO2019069580A1 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JPWO2019069580A1 JPWO2019069580A1 JP2019546568A JP2019546568A JPWO2019069580A1 JP WO2019069580 A1 JPWO2019069580 A1 JP WO2019069580A1 JP 2019546568 A JP2019546568 A JP 2019546568A JP 2019546568 A JP2019546568 A JP 2019546568A JP WO2019069580 A1 JPWO2019069580 A1 JP WO2019069580A1
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Abstract
Description
実施の形態1にかかる半導体装置は、シリコン(Si)よりもバンドギャップが広い半導体(ワイドバンドギャップ半導体とする)を用いて構成される。この実施の形態1にかかる半導体装置の構造について、ワイドバンドギャップ半導体として例えば炭化珪素(SiC)を用いた場合を例に説明する。図1は、実施の形態1にかかる半導体装置を半導体基板のおもて面側から見たレイアウトを示す平面図である。図1には、半導体基板(半導体チップ)10に配置された各素子の電極パッドのレイアウトを示す。
次に、実施の形態2にかかる半導体装置の構造について説明する。図9は、実施の形態2にかかる半導体装置を半導体基板のおもて面側から見たレイアウトを示す平面図である。実施の形態2にかかる半導体装置が実施の形態1にかかる半導体装置と異なる点は、高機能領域3に配置した電極パッド21b,22,23a,23b,24間にも引き抜き電極25’(ハッチング部分)を配置した点である。図9では、OVパッドを図示省略するが、OVパッドは実施の形態1と同様に高機能領域3に配置され、OVパッドと他の電極パッドとの間に引き抜き電極25’が配置される。
次に、実施の形態3にかかる半導体装置の構造について説明する。図10は、実施の形態3にかかる半導体装置を半導体基板のおもて面側から見たレイアウトを示す平面図である。実施の形態3にかかる半導体装置が実施の形態1にかかる半導体装置と異なる点は、すべての電極パッド21a,21b,22,23a,23bが活性領域1’の有効領域1a’に配置されており、活性領域1’の、電極パッド21a,21b,22,23a,23bの直下以外の部分にメイン半導体素子11の主電流が流れる点である。実施の形態3においては、引き抜き電極は設けられていない。図10では、OVパッドを図示省略するが、OVパッドも活性領域1’の有効領域1a’に配置される。
1a,1a’ 活性領域の有効領域
1b 活性領域の無効領域
1c 電極パッドとエッジ終端領域との間
1d 電極パッド間
2 エッジ終端領域
3 高機能領域
3a〜3f 略矩形状の平面形状の高機能領域の辺
3e,3f 略矩形状の平面形状の高機能領域の頂点
10 半導体基板
11 メイン半導体素子
12 電流センス部
13 温度センス部
14 過電圧保護部
21a ソースパッド(電極パッド)
21b ゲートパッド(電極パッド)
22 OCパッド(電極パッド)
23a アノードパッド(電極パッド)
23b カソードパッド(電極パッド)
24 OVパッド(電極パッド)
25,25’,25a,25b,25a’,25b’ 引き抜き電極
26,26’ ゲートコンタクトメタル領域
31 n+型出発基板
32 n-型ドリフト領域
32a n-型領域
33a,33b n型電流拡散領域
34a,34b p型ベース領域
35a,35b n+型ソース領域
36a〜36c p++型コンタクト領域
37a,37b トレンチ
38a,38b ゲート絶縁膜
39a,39b ゲート電極
40 層間絶縁膜
40a,40b 層間絶縁膜のコンタクトホール
41a,41b NiSi膜
42a,42b 第1TiN膜
43a,43b 第1Ti膜
44a,44b 第2TiN膜
45a,45b 第2Ti膜
46a,46b Al合金膜
47a〜47d めっき膜
48a〜48d 端子ピン
49a〜49d 第1保護膜
50a〜50d 第2保護膜
53a〜53d はんだ層
51 ドレイン電極
52 ドレインパッド
61a,61b 第1p+型領域
62a〜62c 第2p+型領域
71 n-型炭化珪素層
71a n-型炭化珪素層の厚さを増した部分
72 p型炭化珪素層
80 フィールド絶縁膜
81 p型ポリシリコン層
82 n型ポリシリコン層
83 層間絶縁層
84 アノード電極
85 カソード電極
91,93 p+型部分領域
92,94 n型部分領域
d1,d1’ 電極パッドとエッジ終端領域と間の間隔
d2 電極パッド間の間隔
d11 第1p+型領域およびp+型部分領域の深さ
d12 隣り合う第1p+型領域とp+型部分領域との間の距離
d13 n型部分領域の深さ
t1 n-型炭化珪素層の厚さ
t2 n-型炭化珪素層を増した部分の厚さ
t3 p型炭化珪素層の厚さ
w1 エッジ終端領域の幅
w11 引き抜き電極の幅
w12 ゲートコンタクトメタル領域の幅
X,Y 半導体基板のおもて面に平行な方向(第1方向)
Z 深さ方向
Claims (9)
- シリコンよりもバンドギャップの広い半導体からなる第1導電型の半導体基板に設けられた、主電流が流れる活性領域と、
前記活性領域の周囲を囲む終端領域と、
前記活性領域において、前記半導体基板の第1主面側の表面層に設けられた第1の第2導電型領域と、
前記活性領域において、前記半導体基板の第1主面側の表面層に、前記第1の第2導電型領域と離して設けられた第2の第2導電型領域と、
前記第1の第2導電型領域をベース領域とする第1絶縁ゲート型電界効果トランジスタと、
前記第2の第2導電型領域に設けられた、前記第1絶縁ゲート型電界効果トランジスタを保護または制御するための1つ以上の回路部と、
前記半導体基板の第1主面に設けられ、前記第1の第2導電型領域に電気的に接続された、前記第1絶縁ゲート型電界効果トランジスタのソースパッドと、
前記半導体基板の第1主面に、前記終端領域と離して設けられた、前記回路部の1つ以上の電極パッドと、
を備え、
前記第2の第2導電型領域は、
前記電極パッドと前記終端領域との間に設けられ、
かつ前記ソースパッドの電位に固定されていることを特徴とする半導体装置。 - 前記半導体基板の第1主面において前記電極パッドと前記終端領域との間に、前記電極パッドと離して設けられ、前記ソースパッドの電位に固定された第1電極をさらに備え、
前記第2の第2導電型領域は、前記第1電極を介して前記ソースパッドの電位に固定されていることを特徴とする請求項1に記載の半導体装置。 - 前記電極パッドは、2つ以上設けられ、
前記第2の第2導電型領域および前記第1電極は、隣り合う前記電極パッド間に設けられていることを特徴とする請求項2に記載の半導体装置。 - 前記活性領域の、前記終端領域との境界に設けられ、前記回路部および前記電極パッドが配置された高機能領域をさらに備え、
前記第2の第2導電型領域は、前記高機能領域において、前記半導体基板の第1主面側の表面層の全域に設けられていることを特徴とする請求項1〜3のいずれか一つに記載の半導体装置。 - 前記第1絶縁ゲート型電界効果トランジスタは、
前記第1の第2導電型領域と、
前記半導体基板の、前記第1の第2導電型領域および前記第2の第2導電型領域以外の部分である第1導電型領域と、
前記第1の第2導電型領域を深さ方向に貫通して前記第1導電型領域に達する第1トレンチと、
前記第1トレンチの内部に第1ゲート絶縁膜を介して設けられた第1ゲート電極と、
前記第1導電型領域および前記第1の第2導電型領域に電気的に接続された前記ソースパッドと、
前記半導体基板の第2主面に設けられた第2電極と、を有し、
前記第2の第2導電型領域を深さ方向に貫通して前記第1導電型領域に達する第2トレンチと、
前記第2トレンチの内部に第2ゲート絶縁膜を介して設けられた第2ゲート電極と、
をさらに備え、
前記第2トレンチ、前記第2ゲート絶縁膜および前記第2ゲート電極は、それぞれ前記第1トレンチ、前記第1ゲート絶縁膜および前記第1ゲート電極と同じ構成を有することを特徴とする請求項4に記載の半導体装置。 - 前記電極パッドは、2つ以上設けられ、
前記第1の第2導電型領域は、隣り合う前記電極パッド間に設けられていることを特徴とする請求項1に記載の半導体装置。 - 前記回路部は、前記第1絶縁ゲート型電界効果トランジスタに流れる過電流を検出する第2絶縁ゲート型電界効果トランジスタであり、前記第1絶縁ゲート型電界効果トランジスタと同じ構成を有することを特徴とする請求項1〜6のいずれか一つに記載の半導体装置。
- 前記回路部は、前記第1絶縁ゲート型電界効果トランジスタの温度を検出するダイオードであることを特徴とする請求項1〜6のいずれか一つに記載の半導体装置。
- 前記回路部は、過電圧から前記第1絶縁ゲート型電界効果トランジスタを保護するダイオードであることを特徴とする請求項1〜6のいずれか一つに記載の半導体装置。
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