JP7135445B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP7135445B2 JP7135445B2 JP2018102844A JP2018102844A JP7135445B2 JP 7135445 B2 JP7135445 B2 JP 7135445B2 JP 2018102844 A JP2018102844 A JP 2018102844A JP 2018102844 A JP2018102844 A JP 2018102844A JP 7135445 B2 JP7135445 B2 JP 7135445B2
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- polysilicon layer
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Description
実施の形態1にかかる半導体装置は、シリコン(Si)よりもバンドギャップが広い半導体(以下、ワイドバンドギャップ半導体とする)を半導体材料として用いて構成される。この実施の形態1にかかる半導体装置の構造について、ワイドバンドギャップ半導体として例えば炭化珪素(SiC)を用いた場合を例に説明する。図1,2は、実施の形態1にかかる半導体装置を半導体基板のおもて面側から見たレイアウトの一例を示す平面図である。図1,2には、それぞれ、半導体基板(半導体チップ)10に配置された各素子の電極パッドのレイアウトの異なる一例を示す。
次に、実施の形態2にかかる半導体装置の構造について説明する。図11は、実施の形態2にかかる半導体装置の構造を示す断面図である。図12は、実施の形態2にかかる半導体装置の等価回路を示す回路図である。実施の形態2にかかる半導体装置が実施の形態1にかかる半導体装置と異なる点は、メイン半導体素子11のソースパッド21aと温度センス部13のカソードパッド23b’とが直に接する点である。すなわち、メイン半導体素子11のソースと接地点GNDとの間に、温度センス部13のカソードが接続されている(図12参照)。
次に、実施の形態3にかかる半導体装置の構造について説明する。図13は、実施の形態3にかかる半導体装置の構造を示す断面図である。図14は、図13の一部を拡大して示す平面図である。図14には、図13の第4コンタクトホール83bを拡大して示す。実施の形態3にかかる半導体装置が実施の形態2にかかる半導体装置と異なる点は、温度センス部13のn型ポリシリコン層82とカソードパッド23b’との間にバリアメタル44cが設けられている点である。温度センス部13のp型ポリシリコン層81とアノードパッド23aとの間にはバリアメタルは設けられておらず、p型ポリシリコン層81とアノードパッド23aとは、実施の形態1と同様に直に接している。
2 エッジ終端領域
10 半導体基板
11 メイン半導体素子
12 電流センス部
13 温度センス部
14 過電圧保護部
15 抵抗体
21a ソースパッド
21b ゲートパッド
22 OCパッド
23a アノードパッド
23b,23b' カソードパッド
24 OVパッド
31 n+型出発基板
32 n-型ドリフト領域
32a n-型領域
33a,33b n型電流拡散領域
34a,34b p型ベース領域
34c p型領域
35a,35b n+型ソース領域
36a,36b p++型コンタクト領域
37a,37b トレンチ
38a,38b ゲート絶縁膜
39a,39b ゲート電極
40,83 層間絶縁膜
40a,40b,83a,83b コンタクトホール
41a,41b NiSi膜
42a~42c Ti膜
43a~43c TiN膜
44a~44c バリアメタル
47a~47d めっき膜
48a~48d 端子ピン
49a~49c 第1保護膜
50a~50c 第2保護膜
51 ドレイン電極
61a,61b 第1p+型領域
62a,62b 第2p+型領域
62c 第3p+型領域
71 n-型炭化珪素層
71a n-型炭化珪素層の厚さを増した部分
72 p型炭化珪素層
80 フィールド絶縁膜
81 p型ポリシリコン層
82 n型ポリシリコン層
91,93 p+型部分領域
92,94 n型部分領域
d1 第1p+型領域およびp+型部分領域の深さ
d2 隣り合う第1p+型領域とp+型部分領域との間の距離
d3 n型部分領域の深さ
t1 n-型炭化珪素層の厚さ
t2 n-型炭化珪素層を増した部分の厚さ
t3 p型炭化珪素層の厚さ
GND 接地点
X 半導体基板のおもて面に平行な方向(第1方向)
Y 半導体基板のおもて面に平行な方向で、かつ第1方向と直交する方向(第2方向)
Z 深さ方向
Claims (9)
- シリコンよりもバンドギャップの広い半導体からなる第1導電型の半導体基板の第1主面の表面層に設けられた第2導電型領域と、
前記第2導電型領域をベース領域とする絶縁ゲート型電界効果トランジスタと、
前記半導体基板の第1主面に、絶縁層を介して設けられた第2導電型ポリシリコン層と、
前記半導体基板の第1主面に、前記絶縁層を介して設けられ、前記第2導電型ポリシリコン層に接する第1導電型ポリシリコン層と、
前記第2導電型ポリシリコン層と前記第1導電型ポリシリコン層とのpn接合で形成されたダイオードと、
前記第2導電型領域に電気的に接続された、前記絶縁ゲート型電界効果トランジスタのソースパッドと、
前記第2導電型ポリシリコン層に電気的に接続された、前記ダイオードのアノードパッドと、
前記第1導電型ポリシリコン層に電気的に接続された、前記ダイオードのカソードパッドと、
を備え、
前記ソースパッドは、
アルミニウムを主成分とする金属膜であり、バリアメタルを介して前記第2導電型領域に電気的に接続され、
かつ前記第1導電型ポリシリコン層に直に接して前記カソードパッドを構成し、
前記アノードパッドは、アルミニウムを主成分とする金属膜であり、前記第2導電型ポリシリコン層に直に接することを特徴とする半導体装置。 - シリコンよりもバンドギャップの広い半導体からなる第1導電型の半導体基板の第1主面の表面層に設けられた第2導電型領域と、
前記第2導電型領域をベース領域とする絶縁ゲート型電界効果トランジスタと、
前記半導体基板の第1主面に、絶縁層を介して設けられた第2導電型ポリシリコン層と、
前記半導体基板の第1主面に、前記絶縁層を介して設けられ、前記第2導電型ポリシリコン層に接する第1導電型ポリシリコン層と、
前記第2導電型ポリシリコン層と前記第1導電型ポリシリコン層とのpn接合で形成されたダイオードと、
前記第2導電型領域に電気的に接続された、前記絶縁ゲート型電界効果トランジスタのソースパッドと、
前記第2導電型ポリシリコン層に電気的に接続された、前記ダイオードのアノードパッドと、
前記第1導電型ポリシリコン層に電気的に接続された、前記ダイオードのカソードパッドと、
を備え、
前記ソースパッドは、
アルミニウムを主成分とする金属膜であり、バリアメタルを介して前記第2導電型領域に電気的に接続され、
かつ前記バリアメタルを介して前記第1導電型ポリシリコン層に接続され前記カソードパッドを構成し、
前記アノードパッドは、アルミニウムを主成分とする金属膜であり、前記第2導電型ポリシリコン層に直に接することを特徴とする半導体装置。 - シリコンよりもバンドギャップの広い半導体からなる第1導電型の半導体基板の第1主面の表面層に設けられた第2導電型領域と、
前記第2導電型領域をベース領域とする絶縁ゲート型電界効果トランジスタと、
前記半導体基板の第1主面に、絶縁層を介して設けられた第2導電型ポリシリコン層と、
前記半導体基板の第1主面に、前記絶縁層を介して設けられ、前記第2導電型ポリシリコン層に接する第1導電型ポリシリコン層と、
前記第2導電型ポリシリコン層と前記第1導電型ポリシリコン層とのpn接合で形成されたダイオードと、
前記第2導電型領域に電気的に接続された、前記絶縁ゲート型電界効果トランジスタのソースパッドと、
前記第2導電型ポリシリコン層に電気的に接続された、前記ダイオードのアノードパッドと、
前記第1導電型ポリシリコン層に電気的に接続された、前記ダイオードのカソードパッドと、
を備え、
前記ソースパッドは、アルミニウムを主成分とする金属膜であり、バリアメタルを介して前記第2導電型領域に電気的に接続され、
前記アノードパッドは、アルミニウムを主成分とする金属膜であり、前記第2導電型ポリシリコン層に直に接し、
前記ダイオードは、前記絶縁ゲート型電界効果トランジスタと電気的に絶縁されていることを特徴とする半導体装置。 - 前記カソードパッドは、アルミニウムを主成分とする金属膜であり、前記第1導電型ポリシリコン層に直に接することを特徴とする請求項3に記載の半導体装置。
- 前記カソードパッドと前記第1導電型ポリシリコン層との間に部分的に前記バリアメタルが配置され、
前記カソードパッドと前記第1導電型ポリシリコン層とは、一部で前記バリアメタルを介して接続され、残りの部分で直に接することを特徴とする請求項2に記載の半導体装置。 - 前記バリアメタルは、チタン膜または窒化チタン膜、もしくはチタン膜および窒化チタン膜の積層膜であることを特徴とする請求項1~5のいずれか一つに記載の半導体装置。
- 前記カソードパッドは接地され、
前記ダイオードに常に順方向電圧が印加され、
前記ダイオードの温度特性を利用して、前記絶縁ゲート型電界効果トランジスタの温度を検出することを特徴とする請求項1~6のいずれか一つに記載の半導体装置。 - シリコンよりもバンドギャップの広い半導体からなる第1導電型の半導体基板の第1主面の表面層に設けられた第2導電型領域と、
前記第2導電型領域をベース領域とする絶縁ゲート型電界効果トランジスタと、
前記半導体基板に設けられた、前記絶縁ゲート型電界効果トランジスタを保護または制御するための1つ以上の回路部と、
前記半導体基板の第1主面に、絶縁層を介して設けられ、前記回路部を構成するポリシリコン層と、
前記第2導電型領域に電気的に接続された、前記絶縁ゲート型電界効果トランジスタのソースパッドと、
前記ポリシリコン層に電気的に接続された電極パッドと、
を備え、
前記ソースパッドは、アルミニウムを主成分とする金属膜であり、バリアメタルを介して前記第2導電型領域に電気的に接続され、
前記電極パッドは、アルミニウムを主成分とする金属膜であり、前記ポリシリコン層に直に接し、
前記回路部は、前記絶縁ゲート型電界効果トランジスタと電気的に絶縁されていることを特徴とする半導体装置。 - 前記回路部は、前記ポリシリコン層の内部にpn接合を有し、
前記回路部の前記pn接合に常に順方向電圧が印加され、
前記回路部の前記順方向電圧の温度特性を利用して、前記絶縁ゲート型電界効果トランジスタの温度を検出することを特徴とする請求項8に記載の半導体装置。
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