JP7017733B2 - 半導体装置および半導体装置の製造方法 - Google Patents
半導体装置および半導体装置の製造方法 Download PDFInfo
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- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 40
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- 108091006146 Channels Proteins 0.000 description 23
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Description
実施の形態1にかかる半導体装置は、シリコンよりもバンドギャップが広い半導体(ワイドバンドギャップ半導体とする)を用いて構成される。この実施の形態1にかかる半導体装置の構造について、ワイドバンドギャップ半導体として例えば炭化珪素(SiC)を用いた場合を例に説明する。図1は、実施の形態1にかかる半導体装置の構造を示す断面図である。図2は、実施の形態1にかかる半導体装置の耐圧特性を示すシミュレーション結果である。耐圧とは、半導体装置が誤動作や破壊を起こさない限界の電圧である。図1には、1つの単位セル(素子の構成単位)と、この単位セルの両隣に隣接する単位セルの1/2を示す。
次に、実施の形態2にかかる半導体装置の構造について説明する。図10は、実施の形態2にかかる半導体装置の構造を示す断面図である。図11は、実施の形態2にかかる半導体装置の製造途中の状態を示す断面図である。実施の形態2にかかる半導体装置が実施の形態1にかかる半導体装置と異なる点は、第3p+型領域23とp++型コンタクト領域6とを連結するように、第4p+型領域(第6の第2導電型半導体領域)24を設けた点である。
2 n-型ドリフト領域
3 n型電流拡散領域
3a,3b n型部分領域
4 p型ベース領域
4a チャネル領域
5 n+型ソース領域
6 p++型コンタクト領域
7 トレンチ
8 ゲート絶縁膜
9 ゲート電極
10 半導体基板
11 層間絶縁膜
12 ソース電極
13 ドレイン電極
21 第1p+型領域
22 第2p+型領域
22a,22b p+型部分領域
23 第3p+型領域
24 第4p+型領域
31 n-型炭化珪素層
31a n-型炭化珪素層の厚さを増した部分
32 p型炭化珪素層
41 酸化膜
42,43 斜めイオン注入
44 レジスト膜
45 イオン注入
A 第1,2p+型領域の間の距離
B 第3p+型領域から第2p+型領域までの最短距離
d1 第3p+型領域の、p型ベース領域とn+型ソース領域との界面からの深さ
d2 第4p+型領域の、p型ベース領域とn+型ソース領域との界面からの深さ
L チャネル長
t1 第3p+型領域からトレンチの側壁までの距離
t2 チャネル領域の厚さ
w1 第2p+型領域の、p型ベース領域とn型電流拡散領域との界面における幅
w2 p++型コンタクト領域の、p型ベース領域とn型電流拡散領域との界面における幅
w3 第3p+型領域の幅
θ1,θ2 斜めイオン注入の注入角度
Claims (7)
- シリコンよりもバンドギャップの広い半導体からなる半導体基板と、
前記半導体基板のおもて面に設けられた、シリコンよりもバンドギャップの広い半導体からなる第1導電型の第1半導体層と、
前記第1半導体層の、前記半導体基板側に対して反対側に設けられた、シリコンよりもバンドギャップの広い半導体からなる第2導電型の第2半導体層と、
前記第2半導体層を深さ方向に貫通して前記第1半導体層に達するトレンチと、
前記トレンチの内部にゲート絶縁膜を介して設けられたゲート電極と、
前記第1半導体層の内部に、前記第2半導体層と離して選択的に設けられ、前記トレンチの底面を覆う第1の第2導電型半導体領域と、
隣り合う前記トレンチの間において前記第1半導体層の内部に、前記第2半導体層に接して、かつ前記第1の第2導電型半導体領域と離して選択的に設けられた第2の第2導電型半導体領域と、
前記第2半導体層の内部に選択的に設けられ、前記トレンチの側壁において前記ゲート絶縁膜を介して前記ゲート電極と対向する第1の第1導電型半導体領域と、
前記第2半導体層の内部に、前記第1の第1導電型半導体領域と接して選択的に設けられ、前記第2の第2導電型半導体領域に深さ方向に対向する第3の第2導電型半導体領域と、
前記第2半導体層の、前記第1の第1導電型半導体領域および前記第3の第2導電型半導体領域以外の部分である第4の第2導電型半導体領域と、
前記第2半導体層の内部の、前記第1の第1導電型半導体領域よりも前記第1半導体層側に、前記第1の第1導電型半導体領域に接し、かつ前記トレンチの側壁および前記第1半導体層から離して選択的に設けられた、前記第2半導体層よりも不純物濃度の高い第5の第2導電型半導体領域と、
前記第1の第1導電型半導体領域および前記第3の第2導電型半導体領域に接する第1電極と、
前記半導体基板の裏面に設けられた第2電極と、
を備え、
前記第5の第2導電型半導体領域から前記第2の第2導電型半導体領域までの最短距離、または、前記第5の第2導電型半導体領域から前記第3の第2導電型半導体領域までの最短距離、のうちの短いほうの最短距離は、前記第1の第2導電型半導体領域と前記第2の第2導電型半導体領域との間の距離以下であることを特徴とする半導体装置。 - 前記第5の第2導電型半導体領域から前記第2の第2導電型半導体領域までの最短距離、または、前記第5の第2導電型半導体領域から前記第3の第2導電型半導体領域までの最短距離、のうちの短いほうの最短距離は、前記第1の第2導電型半導体領域と前記第2の第2導電型半導体領域との間の距離の0.7倍以上であることを特徴とする請求項1に記載の半導体装置。
- 前記第4の第2導電型半導体領域の不純物濃度は、8×10 16 /cm 3 以上1.3×10 17 /cm 3 以下であることを特徴とする請求項1または2に記載の半導体装置。
- 前記第2半導体層の内部に、前記第1の第1導電型半導体領域、前記第3の第2導電型半導体領域および前記第5の第2導電型半導体領域に接して選択的に設けられ、前記第3の第2導電型半導体領域と前記第5の第2導電型半導体領域とを連結する第6の第2導電型半導体領域をさらに備えることを特徴とする請求項1~3のいずれか一つに記載の半導体装置。
- 前記第1半導体層の内部に、前記第2半導体層に接して、かつ当該第2半導体層との界面から前記トレンチの底面よりも前記第2電極側に深い位置に達する、前記第1半導体層よりも不純物濃度の高い第2の第1導電型半導体領域をさらに備えることを特徴とする請求項1~4のいずれか一つに記載の半導体装置。
- トレンチの内部にゲート絶縁膜を介してゲート電極を埋め込んだゲート構造を備えた半導体装置の製造方法であって、
シリコンよりもバンドギャップの広い半導体からなる半導体基板の表面に、第1導電型の第1半導体層をエピタキシャル成長させる第1工程と、
前記第1半導体層の表面よりも深い位置から第1所定深さに達する第1の第2導電型半導体領域を、前記第1半導体層の内部に選択的に形成する第2工程と、
前記第1半導体層の表面から第2所定深さに達する第2の第2導電型半導体領域を、前記第1半導体層の内部に、前記第1の第2導電型半導体領域と離して選択的に形成する第3工程と、
前記第1半導体層の表面に、前記第1の第2導電型半導体領域および前記第2の第2導電型半導体領域に対向する第2導電型の第2半導体層をエピタキシャル成長させる第4工程と、
前記第2半導体層の内部に、第1の第1導電型半導体領域を選択的に形成する第5工程と、
前記第2半導体層の内部に、前記第1の第1導電型半導体領域に接して第3の第2導電型半導体領域を選択的に形成し、前記第2半導体層の、前記第1の第1導電型半導体領域および前記第3の第2導電型半導体領域以外の部分を第4の第2導電型半導体領域とする第6工程と、
前記第2半導体層の表面から前記第1の第1導電型半導体領域および前記第4の第2導電型半導体領域を貫通して前記第1半導体層に達し、前記第1の第2導電型半導体領域の内部で終端する前記トレンチを形成する第7工程と、
前記第2半導体層の表面に対して斜めの方向から所定の注入角度で前記トレンチの側壁に第2導電型不純物をイオン注入して、前記第2半導体層の内部に、前記第2半導体層よりも不純物濃度の高い第5の第2導電型半導体領域を選択的に形成する第8工程と、
を含み、
前記第8工程では、前記第2半導体層の内部の、前記第1の第1導電型半導体領域よりも前記第1半導体層側に、前記第1の第1導電型半導体領域に接し、かつ前記トレンチの側壁および前記第1半導体層から離して前記第5の第2導電型半導体領域を形成することを特徴とする半導体装置の製造方法。 - 前記第2半導体層の表面に対して垂直方向から第2導電型不純物を選択的にイオン注入して、前記第2半導体層の内部において前記第3の第2導電型半導体領域と前記第5の第2導電型半導体領域とを連結する、前記第2半導体層よりも不純物濃度の高い第6の第2導電型半導体領域を選択的に形成する第9工程をさらに含み、
前記第9工程では、前記第2半導体層の内部の、前記第1の第1導電型半導体領域よりも前記第1半導体層側に、前記第1の第1導電型半導体領域、前記第3の第2導電型半導体領域および前記第5の第2導電型半導体領域に接する前記第6の第2導電型半導体領域を形成することを特徴とする請求項6に記載の半導体装置の製造方法。
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