JP2011134947A - Lateral semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enhance the breakdown voltage of a lateral semiconductor device by making thin a silicon semiconductor layer of an SOI substrate, and to prevent the time up to thermal breakage of the silicon semiconductor layer during supply of a large current from becoming short. <P>SOLUTION: An IGBT 1 is constituted by forming a support substrate 11, a buried silicon oxide layer 12, a silicon semiconductor layer 13, and an insulating layer 23 in order. The silicon semiconductor layer 13 includes an emitter region 14 in contact with an emitter electrode 20, a collector region 15 in contact with a collector electrode 21, and a center semiconductor region composed of a body region 17, a part of a buffer region 19, and a drift region 16. A part of the insulating layer 23 is a highly thermally conductive layer 27 which is formed on a material having higher thermal conductivity than silicon oxide, and spreads right over the drift region 16. <P>COPYRIGHT: (C)2011,JPO&amp;INPIT

Description

  The present invention relates to a lateral semiconductor device using an SOI substrate.

  As described in Non-Patent Document 1, a lateral IGBT (Insulated Gate Bipolar Transistor) using an SOI substrate is known. The inverter circuit is switched by this IGBT to control the amount of current supplied to an electric device such as a motor. When a short circuit phenomenon occurs in an electrical device, a large current flows through the IGBT. The IGBT described in Non-Patent Document 1 is reported to be resistant to thermal breakdown for 8 μsec when a current that is eight times the rated current flows. Therefore, the IGBT can be protected from thermal destruction by providing a protection circuit that forcibly turns off the gate voltage when a current larger than the rated current flows in the IGBT. If the time until thermal breakdown is about 8 μsec, the gate voltage can be forcibly turned off by the protection circuit before that.

  It is known that the breakdown voltage of the semiconductor structure formed in the silicon semiconductor layer can be improved by reducing the thickness of the silicon semiconductor layer of the SOI substrate. Non-Patent Document 2 discloses that the breakdown voltage of a semiconductor structure formed in a silicon semiconductor layer is reduced to 700 V by reducing the thickness of a silicon semiconductor layer of an SOI substrate having a buried silicon oxide layer having a thickness of 4 μm to 1 μm. It is disclosed that it can rise. Further, according to experiments by the present inventors, a semiconductor formed in a silicon semiconductor layer by reducing the thickness of a silicon semiconductor layer of an SOI substrate including a buried silicon oxide layer having a thickness of 4 μm to 1.5 μm. The result is that the breakdown voltage of the structure can be increased to 700V.

Akio Nakagawa et al, “Improvement in Lateral IGBT Design for 500V 3A One Chip Inverter ICs, ISPSD 1999, pp. 321-224. S. Merchan et al, “Realization of High Breakdown Voltage (> 700V) in Thin SOI Devices” ISPSD1991, pp.31-35

  As described above, the breakdown voltage of the semiconductor structure formed in the silicon semiconductor layer can be increased by reducing the thickness of the silicon semiconductor layer of the SOI substrate. However, if the thickness of the silicon semiconductor layer is reduced, when a current exceeding the rated current flows through the semiconductor layer, a phenomenon occurs in which the temperature rises locally at a rapid rate within the semiconductor layer, thereby shortening the time until thermal breakdown. Problem arises.

  A buried silicon oxide layer is disposed under the silicon semiconductor layer. A silicon oxide layer that insulates the wiring from the semiconductor structure is also disposed on the silicon semiconductor layer. When a semiconductor structure is formed in the silicon semiconductor layer of the SOI substrate, a structure in which silicon oxide layers are stacked on the upper and lower surfaces of the semiconductor structure is obtained. The silicon oxide layer has a lower thermal conductivity than the silicon semiconductor layer. When a semiconductor structure is formed in the silicon semiconductor layer of the SOI substrate, a structure in which low thermal conductive layers are stacked on the upper and lower surfaces of the silicon semiconductor layer is obtained.

  When the silicon semiconductor layer is thinned in a structure in which low thermal conductive layers are stacked on the upper and lower surfaces of the silicon semiconductor layer, when heat is generated in a local part of the silicon semiconductor layer, the ability to transfer the heat to the surroundings is reduced. A phenomenon occurs in which the temperature rises rapidly at the local area.

If the thickness of the silicon semiconductor layer is reduced in order to increase the breakdown voltage of the semiconductor structure, the phenomenon that the temperature rises locally at a rapid rate in the semiconductor structure when a current exceeding the rated current flows through the semiconductor structure of the silicon semiconductor layer. Occurs, and the time until thermal destruction is shortened. Therefore, the operation time of the protection circuit that forcibly turns off the gate voltage is not in time, and the semiconductor structure is likely to be thermally destroyed before the protection circuit is activated.
A phenomenon in which a large current flows through a semiconductor structure of a silicon semiconductor layer and is thermally destroyed can occur not only in an IGBT but also in a semiconductor device such as an LDMOS (Laterally Diffused MOS) or a diode.

  The invention disclosed in the present specification has been made in view of such circumstances, and by increasing the breakdown voltage of a horizontal semiconductor device by thinning the silicon semiconductor layer of the SOI substrate, the silicon semiconductor can be used when a large current is applied. The object is to prevent the time until the semiconductor structure of the layer is thermally destroyed from becoming shorter.

  In the lateral semiconductor device disclosed in this specification, a support substrate, a buried silicon oxide layer, a silicon semiconductor layer, and an insulating layer are sequentially formed, and are in contact with the silicon semiconductor layer in a range where the insulating layer is not formed. A first main electrode and a second main electrode are provided. The silicon semiconductor layer exists between the first semiconductor region in contact with the first main electrode, the second semiconductor region in contact with the second main electrode, and the first semiconductor region and the second semiconductor region. And a central semiconductor region. In addition, at least a part of the insulating layer is formed of a material having higher thermal conductivity than silicon oxide, and is a high thermal conductive layer spreading right above the central semiconductor region.

In the above configuration, a high breakdown voltage can be realized by thinning the silicon semiconductor layer.
When a short circuit occurs in a circuit to which the horizontal semiconductor device having the above configuration is connected, a current equal to or higher than the rated current flows through the silicon semiconductor layer, so that the central semiconductor region generates heat. In the above configuration, since the high thermal conductive layer spreads right above the central semiconductor region, this heat is conducted to the surroundings by the high thermal conductive layer, and a part of the central semiconductor region is prevented from being locally heated. Can do. As a result, it takes time for the semiconductor structure formed in the silicon semiconductor layer to rise to a temperature at which it is thermally destroyed. Therefore, measures can be taken with a safety device or the like in the meantime to protect the semiconductor device.

  In the lateral semiconductor device disclosed in this specification, the high thermal conductive layer is preferably formed on the surface of the silicon semiconductor layer with a silicon oxide layer interposed therebetween.

  When the high thermal conductive layer is directly formed on the surface of the silicon semiconductor layer, depending on the material constituting the high thermal conductive layer, an electric charge may be generated at the interface between the silicon semiconductor layer and the high thermal conductive layer, thereby causing a leakage current. there is a possibility. In this respect, in the above configuration, since the silicon oxide layer is interposed between the silicon semiconductor layer and the high thermal conductive layer, the generation of electric charges at the interface between the silicon semiconductor layer and the insulating layer is suppressed, and the leakage current is reduced. It is possible to suppress the occurrence.

  One of the lateral semiconductor devices disclosed in this specification includes a p-type body region surrounding a first semiconductor region and facing a gate electrode through a gate insulating film in a central semiconductor region, An n-type drift region that is adjacent to the body region and extends to the vicinity of the second semiconductor region. In this lateral semiconductor device, it is preferable that the high thermal conductive layer is formed immediately above the drift region.

  When a short circuit operation occurs in a circuit to which the horizontal semiconductor device having the above configuration is connected, a current exceeding the rated current flows through the silicon semiconductor layer, and heat is generated intensively in the vicinity of the interface between the drift region and the body region. In the above configuration, since the high heat conductive layer spreads right above the drift region, this heat is efficiently conducted to the surroundings by the high heat conductive layer, and it takes time until the heat generating portion reaches a high temperature. As a result, it takes time until the p / n junction between the body region and the drift region thermally disappears and a large current continues to flow through the semiconductor structure of the silicon semiconductor layer. Therefore, the semiconductor structure of the silicon semiconductor layer can be prevented from being thermally destroyed.

  In this lateral semiconductor device, the gate insulating film is formed of a silicon oxide layer, and the high thermal conductive layer is formed on the surface of the silicon semiconductor layer through a silicon oxide layer having a thickness equal to or less than the thickness of the gate insulating film. It is preferable.

  In the above configuration, since the silicon oxide layer is interposed between the silicon semiconductor layer and the high thermal conductive layer, it is possible to suppress the generation of electric charges at the interface between the silicon semiconductor layer and the insulating layer and to generate a leakage current. Can be suppressed.

  In addition, the thickness of the silicon oxide layer interposed between the silicon semiconductor layer and the high thermal conductive layer is equal to or smaller than the gate insulating film, and is formed thin. Therefore, when heat is generated in the silicon semiconductor layer, the silicon oxide layer does not become a very large barrier when this heat is conducted to the high thermal conductive layer. Therefore, the heat generated in the silicon semiconductor layer can be appropriately conducted to the surroundings by the high thermal conductive layer, and the semiconductor structure of the silicon semiconductor layer can be prevented from being thermally destroyed.

  In one lateral semiconductor device disclosed in this specification, the first semiconductor region is an anode region, and the second semiconductor region is a cathode region. A p / n junction interface exists in the central semiconductor region. This semiconductor device functions as a diode.

  When a short circuit operation occurs in a circuit to which the horizontal semiconductor device having the above configuration is connected, a current exceeding the rated current flows through the silicon semiconductor layer, and heat is generated near the interface of the p / n junction. In the above configuration, since the high thermal conductive layer spreads right above the central semiconductor region where the interface exists, the heat is efficiently conducted to the surroundings by the high thermal conductive layer, and the heat generating portion becomes locally hot. It takes time until. As a result, it takes time until the p / n junction between the anode region and the cathode region thermally disappears and a large current continues to flow through the semiconductor structure of the silicon semiconductor layer. Therefore, the semiconductor structure of the silicon semiconductor layer can be prevented from being thermally destroyed.

  In the lateral semiconductor device disclosed in this specification, the high thermal conductivity material is preferably silicon nitride or aluminum nitride.

  Since these materials have higher thermal conductivity than silicon oxide, they can be used as materials for the high thermal conductive layer. In addition, by using these materials, it is possible to realize a withstand voltage characteristic required for the lateral semiconductor device.

  In the lateral semiconductor device disclosed in this specification, the breakdown voltage can be increased by reducing the thickness of the silicon semiconductor layer of the SOI substrate, and the semiconductor structure of the silicon semiconductor layer is thermally destroyed when energized with a large current. Can prevent time from being shortened

FIG. 3 is a cross-sectional view illustrating a main part of the IGBT according to the first embodiment. 6 is a timing chart showing a temperature change of a heat generation spot after a short-circuit phenomenon occurs in the inverter circuit to which the IGBT of Example 1 is connected. 6 is a graph showing the relationship between the thickness of the high thermal conductive layer of Example 1 and the maximum temperature of the heat generation spot. Sectional drawing which shows the principal part of IGBT of Example 2. FIG. Sectional drawing which shows the principal part of LDMOS of Example 3. FIG. Sectional drawing which shows the principal part of the PIN diode of Example 4. Sectional drawing which shows the principal part of the ESD protection diode of Example 5. FIG. Sectional drawing which shows the principal part of the conventional IGBT.

The features of the embodiments of the present invention will be described below.
(Feature 1) The high thermal conductive layer is made of a material having a higher heat capacity than silicon oxide. Even when heat is generated in the silicon semiconductor layer, the high thermal conductive layer is not easily heated, and thus does not reach a high temperature in a short time. This also prevents the central semiconductor region of the silicon semiconductor layer from becoming high temperature, and it takes time to increase the temperature to a temperature at which the semiconductor structure is thermally destroyed.
(Feature 2) In IGBT and LDMOS, a front side silicon oxide layer interposed between a silicon semiconductor layer and a high thermal conductive layer is formed integrally with a silicon oxide layer of a gate insulating film. Since it is not necessary to separately form the gate insulating film and the front side silicon oxide layer, the manufacturing process can be simplified.

The horizontal semiconductor device according to the first embodiment is an IGBT that switches an inverter circuit. The IGBT according to the first embodiment will be described with reference to FIGS. 1 to 3 and FIG.
In FIG. 1, the principal part sectional drawing of IGBT1 is shown typically. In the IGBT 1, a support substrate 11, a buried silicon oxide layer 12, and a silicon semiconductor layer 13 are formed in order. The main material of the support substrate 11 is silicon and is fixed to the ground potential. The buried silicon oxide layer 12 has a thickness of about 4 μm, and the silicon semiconductor layer 13 has a thickness of about 1.5 μm. In the IGBT 1, a high breakdown voltage can be realized by thinning the silicon semiconductor layer 13. Most of the surface of the silicon semiconductor layer 13 is covered with an insulating layer 23.

The silicon semiconductor layer 13 includes an n ⁺ -type emitter region 14 as a first semiconductor region and a p ⁺ -type collector region 15 as a second semiconductor region. An n ⁻ type drift region 16 is provided between the emitter region 14 and the collector region 15.

The emitter region 14 is provided on a part of the surface of the silicon semiconductor layer 13. The emitter region 14 is surrounded by a p-type body region 17. The body region 17 is formed in a range from the front surface to the back surface of the silicon semiconductor layer 13. A p ⁺ -type body contact region 18 is provided in the body region 17 on the surface of the silicon semiconductor layer 13. The collector region 15 is provided on another part of the surface of the silicon semiconductor layer 13. The collector region 15 is surrounded by an n-type buffer region 19. The buffer region 19 is formed in a range from the front surface to the back surface of the silicon semiconductor layer 13.

  One end of the drift region 16 is in contact with the body region 17, and the other end is in contact with the buffer region 19. The drift region 16 is separated from the emitter region 14 by the body region 17 and separated from the collector region 15 by the buffer region 19. In the present embodiment, in the silicon semiconductor layer 13, the drift region 16 is located between the emitter region 14 and the collector region 15, that is, a part of the body region 17 and the buffer region 19 on the side adjacent to the drift region 16. Constitutes the central semiconductor region.

  Part of the surface of the emitter region 14 and the body contact region 18 is not formed with the insulating layer 23 and is in contact with the emitter electrode 20 as the first main electrode. That is, the emitter region 14 and the body contact region 18 are electrically connected to the emitter electrode 20. In addition, a part of the surface of the collector region 15 is not formed with the insulating layer 23 and is in contact with the collector electrode 21 as the second main electrode. That is, the collector region 15 is electrically connected to the collector electrode 21. A gate electrode 24 is opposed to the surface of the body region 17 via a gate insulating film 22 made of silicon oxide. A gate wiring 25 is connected to the gate electrode 24.

  The insulating layer 23 includes a front side silicon oxide layer 26, a high thermal conductive layer 27, and an interlayer insulating film layer 28. The insulating layer 23 insulates the emitter electrode 20, the collector electrode 21, and the gate electrode 24. Although not shown, an interlayer insulating film is also formed on the surface of the insulating layer 23, and the wirings connected to the electrodes 20, 21, and 24 are insulated from each other.

  The front side silicon oxide layer 26 is formed on the surface of the silicon semiconductor layer 13 so as to cover the drift region 16 and the portion of the buffer region 19 on the drift region 16 side. The front side silicon oxide layer 26 is formed continuously and integrally with the gate insulating film 22. That is, in this embodiment, for convenience, a portion between the body region 17 and the gate electrode 24 is referred to as a gate insulating film 22, and the other portion is referred to as a front side silicon oxide layer 26. It is a silicon oxide layer formed integrally on the surface. Therefore, the thickness of the front side silicon oxide layer 26 is the same as that of the gate oxide film. Note that the thickness of the front side silicon oxide layer 26 may be smaller than the thickness of the gate insulating film 22, in other words, the thickness of the front side silicon oxide layer 26 may be equal to or less than the thickness of the gate insulating film 22.

  The high thermal conductive layer 27 is formed so as to cover most of the surface of the front side silicon oxide layer 26. That is, the high thermal conductive layer 27 is formed on the surface of the drift region 16 of the silicon semiconductor layer 13 via the front side silicon oxide layer 26 and extends right above the drift region 16. In this embodiment, since the front-side silicon oxide layer 26 is interposed between the silicon semiconductor layer 13 and the high thermal conductive layer 27, the silicon semiconductor layer 13 is insulated from the silicon semiconductor layer 13 regardless of the material for forming the high thermal conductive layer 27. It is possible to suppress the generation of electric charges at the interface of the layer 23 and suppress the generation of a leak current.

In this embodiment, the high thermal conductive layer 27 is made of silicon nitride and has a thickness of 1.3 μm. The high thermal conductive layer 27 may be formed of a material having higher thermal conductivity than silicon oxide, and aluminum nitride may be used, but the material is not particularly limited. Table 1 shows the thermal conductivity and heat capacity of silicon, silicon oxide, silicon nitride, and aluminum nitride.

  As shown in Table 1, the thermal conductivity of silicon is 138 W / m · K, which is about 100 times the thermal conductivity of silicon oxide of 1.4 W / m · K. The thermal conductivity of silicon nitride is 19 W / m · K, which is about 14 times the thermal conductivity of silicon oxide. The thermal conductivity of aluminum nitride is 285 W / m · K, which is about 200 times the thermal conductivity of silicon oxide. Therefore, when heat is generated in the silicon semiconductor layer 13 when a part of the insulating layer 23 is formed of high thermal conductivity silicon nitride or aluminum nitride rather than forming all of the insulating layer 23 of silicon oxide, this heat is generated. The insulating layer 23 facilitates conduction to the surroundings, and the temperature rise of the silicon semiconductor layer 13 can be suppressed. In addition, by using silicon nitride or aluminum nitride as a material having high thermal conductivity, it is possible to realize a withstand voltage characteristic required for the IGBT 1.

Further, as shown in Table 1, the heat capacity of silicon oxide is 1.63 × 10 ⁶ J / m ³ · K, which is substantially the same value as the heat capacity of silicon 1.67 × 10 ⁶ J / m ³ · K. is there. The heat capacity of silicon nitride is 2.78 × 10 ⁶ J / m ³ · K, and the heat capacity of aluminum nitride is 1.94 × 10 ⁶ J / m ³ · K. Greater than heat capacity. Therefore, when all of the insulating layer 23 is formed of silicon oxide or aluminum nitride having a higher heat capacity than when all of the insulating layer 23 is formed of silicon oxide, the insulating layer 23 is formed when heat is generated in the silicon semiconductor layer 13. It is difficult for the temperature to rise, and this also can suppress the temperature rise of the silicon semiconductor layer 13. Therefore, in this embodiment, a part of the insulating layer 23 is a high thermal conductive layer 27 made of silicon nitride.
Further, the interlayer insulating film layer 28 is formed around and above the high thermal conductive layer 27 and is made of silicon oxide.

  The operation in the case where a short circuit phenomenon occurs in an electric device that is energized and controlled by an inverter circuit that uses the IGBT 1 of this embodiment will be described with reference to FIGS. 1 to 3 and FIG. 8. FIG. 8 shows a conventional IGBT 90. In the conventional IGBT 90, the insulating layer 91 is composed only of a silicon oxide layer, and no high thermal conductive layer is formed. Since the other structure of the conventional IGBT 90 is the same as that of the present embodiment, the same reference numerals are given.

  In the inverter circuit, when a short circuit phenomenon occurs in the electrical device, the protection circuit forcibly turns off the voltage applied to the gate electrode 24 (hereinafter referred to as the gate voltage) 4 μsec after the occurrence of the short circuit phenomenon. Yes. When the short circuit phenomenon occurs, a current having a value larger than the rated current flows in the IGBT 1 or the IGBT 90. Therefore, in the silicon semiconductor layer 13, heat is generated at a portion indicated by a point A on the body region 17 side in the drift region 16 in FIGS. 1 and 8 (hereinafter referred to as a heat generation spot), and this heat generation is conducted to the surroundings.

  FIG. 2 shows the temperature change of the heat generation spot A after the occurrence of the short circuit phenomenon, the solid line A shows the IGBT 1 of this embodiment, and the broken line B shows the conventional IGBT 90. As shown by the solid line A and the broken line B in FIG. 2, when the short circuit phenomenon occurs, the temperature of the heat generation spot A gradually increases. Even if the gate voltage is turned off 4 μsec after the occurrence of the short-circuit phenomenon, the temperature of the heat generation spot A does not decrease immediately, and the temperature rises for about 1 μsec thereafter. Thereafter, the temperature of the heat generation spot A gradually decreases. As shown in FIG. 2, about 1 μsec after the gate voltage is turned off, that is, about 5 μsec after the occurrence of the short circuit phenomenon, the heat generation spot A of the IGBT 1 and the IGBT 90 becomes the highest temperature. The broken lines E to G in FIG. 1 and the broken lines B to G in FIG. 8 indicate the isotherm at this time, that is, the isotherm after 5 μsec has elapsed since the occurrence of the short circuit phenomenon. Dashed lines B, C, D, E, F, and G indicate isotherms of 1100K, 1000K, 900K, 800K, 700K, and 600K, respectively.

  As shown by a broken line B in FIG. 2, in the conventional IGBT 90, the maximum temperature of the heat generation spot A is 1170K. As shown in FIG. 8, in the conventional IGBT 90, the temperature in the vicinity of the interface of the p / n junction between the body region 17 and the drift region 16 becomes about 800 K as indicated by the broken line E after 5 μsec has elapsed since the occurrence of the short circuit phenomenon. . In the IGBT 90, the silicon semiconductor layer 13 is covered with thick silicon oxide layers 12 and 91 on the upper and lower sides thereof. Since silicon oxide has a low thermal conductivity as shown in Table 1, the heat generated at the generated spot A is not easily conducted to the surroundings through the upper and lower silicon oxide layers 12 and 91. As shown in FIG. The silicon semiconductor layer 13 is mainly spread in the lateral direction. Accordingly, the heat generation spot A rises to 1170 K, and the temperature near the p / n junction between the body region 17 and the drift region 16 also becomes high. In this state, when the temperature rises even a little, the p / n junction is thermally lost, a large current flows, and the semiconductor structure formed in the silicon semiconductor layer 13 may be thermally destroyed.

  On the other hand, as shown by a solid line A in FIG. 2, in the IGBT 1 of this embodiment, the maximum temperature of the heat generation spot A is 870K. As shown in FIG. 1, the IGBT 1 becomes about 650 K in the vicinity of the interface of the p / n junction between the body region 17 and the drift region 16 after 5 μsec has elapsed since the occurrence of the short-circuit phenomenon. In the IGBT 1, a high thermal conductivity layer 27 is formed on the surface of the drift region 16 via a front side silicon oxide layer 26. As shown in Table 1, the thermal conductivity of the silicon nitride constituting the high thermal conductivity layer 27 is oxidized. Higher than silicon. Therefore, the heat generated at the generated spot A is efficiently conducted to the surroundings through the high thermal conductive layer 27. Although the front-side silicon oxide layer 26 is interposed between the drift region 16 of the silicon semiconductor layer 13 and the high thermal conductive layer 27, this thickness is the same as the thickness of the gate insulating film 22 and is formed thin. Has been. Therefore, when heat is generated at the heat generation spot A in the drift region 16, the front-side silicon oxide layer 26 does not become a very large barrier when this heat is conducted to the high thermal conductive layer 27. Therefore, the heat generated in the drift region 16 can be appropriately conducted to the surroundings by the high thermal conductive layer, and it is possible to suppress the local increase in temperature at the heat generation spot A.

  Further, as shown in Table 1, the heat capacity of silicon nitride constituting the high thermal conductive layer 27 is higher than the heat capacity of silicon oxide. Therefore, even if the high heat conductive layer 27 absorbs heat generated at the heat generation spot A, the temperature does not easily rise, and thus does not reach a high temperature in a short time. Therefore, the temperature rise of the silicon semiconductor layer 13 can be further suppressed even when the high thermal conductive layer 27 of the present embodiment has a high heat capacity.

  The thickness of the high thermal conductive layer 27 is set as follows. FIG. 3 shows the maximum temperature of the heat generation spot A with respect to the thickness of the high thermal conductive layer 27. As shown in FIG. 3, as the thickness of the high heat conductive layer 27 is increased, the heat generated in the heat generating spot A is more easily conducted to the surroundings through the high heat conductive layer 27, so that the maximum temperature of the heat generating spot A is decreased. . When the thickness of the high thermal conductive layer 27 is 4 μm or more, the effect of reducing the maximum temperature of the heat generation spot A is almost constant. Therefore, the thickness of the high thermal conductive layer 27 is preferably set to 1 to 4 μm. In this embodiment, since the thickness of the high thermal conductive layer 27 is about 1.3 μm, the maximum temperature of the heat generation spot A is suppressed to 870K.

  As described above, the IGBT 1 of the present embodiment has a part of the insulating layer 23 that is the high thermal conductive layer 27, so even if a short-circuit phenomenon occurs in the circuit, compared to the conventional IGBT 90, The temperature of the p / n junction between the body region 17 and the drift region 16 can be suppressed to a low temperature. Therefore, even if the temperature of this p / n junction further rises, there is some time margin before it thermally disappears. As a result, the semiconductor circuit formed in the silicon semiconductor layer can be protected from thermal destruction by taking a measure that the gate voltage is turned off in 4 μsec from the occurrence of the short circuit phenomenon by the protection circuit.

The IGBT 2 according to the second embodiment will be described with reference to FIG. In FIG. 4, the principal part sectional drawing of IGBT2 of a present Example is typically shown.
The second embodiment is different from the first embodiment in the configuration of the drift region 29. Since other configurations are the same as those in the first embodiment, the same reference numerals are used and description thereof is omitted.

  As shown in FIG. 4, the drift region 29 of the IGBT 2 includes a first layer 29a having a low impurity concentration and a second layer 29b having a high impurity concentration and extending in the lateral direction. In the second layer 29b, the impurity concentration increases in order toward the collector region 15 side. In the present embodiment, the impurity concentration of the second layer 29b increases discontinuously (stepwise) toward the collector region 15 side, but the impurity concentration of the second layer 29b increases toward the collector region 15 side. May increase continuously.

  In the present embodiment, since the second layer 29b is provided, an equipotential line indicating the electric field strength is present in the drift region 29 when a voltage is applied to the collector electrode 21 and the gate voltage is turned off. It becomes uniform over the entire lateral direction. That is, the concentration of the electric field locally in the drift region 29 is suppressed, and the breakdown voltage of the IGBT 2 can be further increased. Further, when the gate voltage is turned on in this state, conductivity modulation is likely to occur in the shortest path (the first layer 29a on the surface side of the drift region 29) connecting the emitter region 14 and the collector region 15. Compared with the case where the two layers 29b are formed on the surface side, the carrier movement resistance becomes smaller.

  Also in the IGBT 2 of this embodiment, a part of the insulating layer 23 is the high thermal conductive layer 27. Accordingly, even when a short circuit occurs in the circuit to which the IGBT 2 is connected, the temperature of the p / n junction between the body region 17 and the drift region 16 can be suppressed to a low temperature. It becomes possible to protect the semiconductor structure formed in the layer from thermal destruction. Other functions and effects are the same as those of the first embodiment.

The lateral semiconductor device according to the third embodiment is an LDMOS that switches an inverter circuit. An LDMOS according to Example 3 will be described with reference to FIG.
As shown in FIG. 5, in the LDMOS 30, a support substrate 31, a buried silicon oxide layer 32, and a silicon semiconductor layer 33 are formed in this order. The main material of the support substrate 31 is silicon and is fixed to the ground potential. The buried silicon oxide layer 32 has a thickness of about 4 μm, and the silicon semiconductor layer 33 has a thickness of about 1.5 μm. In the LDMOS 30, a high breakdown voltage can be realized by thinning the silicon semiconductor layer 33. Most of the surface of the silicon semiconductor layer 33 is covered with an insulating layer 43.

The silicon semiconductor layer 33 includes an n ⁺ type source region 34 as a first semiconductor region and an n ⁺ type drain region 35 as a second semiconductor region. An n ⁻ -type drift region 36 is provided between the source region 34 and the drain region 35.

The source region 34 is provided on a part of the surface of the silicon semiconductor layer 33. This source region 34 is surrounded by a p-type body region 37. The body region 37 is formed in a range from the front surface to the back surface of the silicon semiconductor layer 33. A p ⁺ -type body contact region 38 is provided inside the body region 37 on the surface of the silicon semiconductor layer 33. The drain region 35 is provided on another part of the surface of the silicon semiconductor layer 33. The drain region 35 is surrounded by an n-type buffer region 39. The buffer region 39 is formed in a range from the front surface to the back surface of the silicon semiconductor layer 33.

  One end of the drift region 36 is in contact with the body region 37, and the other end is in contact with the buffer region 39. The drift region 36 is separated from the source region 34 by the body region 37 and separated from the drain region 35 by the buffer region 39. In the present embodiment, in the silicon semiconductor layer 33, the drift region 36 is located between the source region 34 and the drain region 35, that is, a part of the body region 37 and the buffer region 39 adjacent to the drift region 36. Constitutes the central semiconductor region.

  A part of the surface of the source region 34 and the body contact region 38 is not formed with the insulating layer 43, is in contact with the source electrode 40 as the first main electrode, and is electrically connected to the source electrode 40. Yes. A part of the surface of the drain region 35 is not formed with the insulating layer 43, is in contact with the drain electrode 41 as the second main electrode, and is electrically connected to the drain electrode 41. A gate electrode 44 is opposed to the surface of the body region 37 through a gate insulating film 42 made of silicon oxide. A gate wiring 45 is connected to the gate electrode 44.

  The insulating layer 43 includes a front side silicon oxide layer 46, a high thermal conductive layer 47, and an interlayer insulating film layer 48. The insulating layer 43 insulates the source electrode 40, the drain electrode 41, and the gate electrode 44. Although not shown, the wirings connected to the electrodes 40, 41, and 44 are insulated from each other by an interlayer insulating film.

  The front side silicon oxide layer 46 is formed on the surface of the silicon semiconductor layer 33 so as to cover the drift region 36 and the portion of the buffer region 39 on the drift region 36 side. The front-side silicon oxide layer 46 is formed continuously and integrally with the gate insulating film 42. The thickness of the front side silicon oxide layer 46 is the same as that of the gate oxide film. The thickness of the front side silicon oxide layer 46 may be equal to or less than the thickness of the gate insulating film 42. Since the front-side silicon oxide layer 46 is formed, the generation of electric charges at the interface between the silicon semiconductor layer 33 and the insulating layer 43 is suppressed, and the generation of leakage current can be suppressed.

  The high thermal conductive layer 47 is formed so as to cover most of the surface of the front side silicon oxide layer 46 and extends right above the drift region 36. The high thermal conductive layer 47 is made of silicon nitride and has a thickness of 1.3 μm. The interlayer insulating film layer 48 is formed around and above the high thermal conductive layer 47 and is made of silicon oxide.

  In the LDMOS 30, since a part of the insulating layer 43 is the high thermal conductive layer 47, the p / n junction between the body region 37 and the drift region 36 is present even when a short circuit occurs in the circuit. The temperature can be suppressed to a low temperature. Therefore, it is possible to protect the semiconductor structure formed in the silicon semiconductor layer 33 from thermal destruction by taking a measure that the gate voltage is turned off within the design time from the occurrence of the short-circuit phenomenon by the protection circuit.

The lateral semiconductor device according to the fourth embodiment is a PIN diode. A PIN diode according to Example 4 will be described with reference to FIG.
As shown in FIG. 6, in the PIN diode 50, a support substrate 51, a buried silicon oxide layer 52, and a silicon semiconductor layer 53 are formed in this order. The main material of the support substrate 51 is silicon, and is fixed to the ground potential. The buried silicon oxide layer 52 has a thickness of about 4 μm, and the silicon semiconductor layer 53 has a thickness of about 1.5 μm. In the PIN diode 50, a high breakdown voltage can be realized by thinning the silicon semiconductor layer 53. Most of the surface of the silicon semiconductor layer 53 is covered with an insulating layer 63.

The silicon semiconductor layer 53 includes a p ⁺ -type first anode region 54 as a first semiconductor region and an n ⁺ -type cathode region 55 as a second semiconductor region. An n ⁻ -type drift region 56 is provided between the first anode region 54 and the cathode region 55. The drift region 56 may be an i-type (intrinsic semiconductor) region and is not necessarily n ^- type. In the PIN diode 50, by reducing the impurity concentration of the drift region 56, current flows from the anode electrode 60 side to the cathode electrode 61 side only when a voltage of a predetermined value or higher is applied to the anode electrode 60. .

  The first anode region 54 is provided on a part of the surface of the silicon semiconductor layer 53. The first anode region 54 is surrounded by a p-type second anode region 57 having an impurity concentration lower than that of the first anode region 54. The second anode region 57 is formed in a range from the front surface to the back surface of the silicon semiconductor layer 53. The cathode region 55 is provided on another part of the surface of the silicon semiconductor layer 53. The cathode region 55 is surrounded by an n-type buffer region 59. The buffer region 59 is formed in a range from the front surface to the back surface of the silicon semiconductor layer 53.

  One end of the drift region 56 is in contact with the second anode region 57, and the other end is in contact with the buffer region 59. The drift region 56 is separated from the first anode region 54 by the second anode region 57 and separated from the cathode region 55 by the buffer region 59. In this embodiment, in the silicon semiconductor layer 53, drift occurs between the first anode region 54 and the cathode region 55, that is, a part of the second anode region 57 and the buffer region 59 on the side adjacent to the drift region 56. The region 56 forms a central semiconductor region. Note that an interface between the second anode region 57 and the drift region 56 exists in the central semiconductor region, and this interface is a p / n junction interface in this embodiment.

  A part of the surface of the first anode region 54 is not formed with the insulating layer 63, is in contact with the anode electrode 60 as the first main electrode, and is electrically connected to the anode electrode 60. Further, a part of the surface of the cathode region 55 is not formed with the insulating layer 63, is in contact with the cathode electrode 61 as the second main electrode, and is electrically connected to the cathode electrode 61.

  The insulating layer 63 includes a front side silicon oxide layer 66, a high thermal conductive layer 67, and an interlayer insulating film layer 68. The anode layer 60 and the cathode electrode 61 are insulated by the insulating layer 63. Although not shown, wirings connected to the electrodes 60 and 61 are insulated from each other by an interlayer insulating film.

  The front side silicon oxide layer 66 is formed on the surface of the silicon semiconductor layer 53 so as to cover the drift region 56 side of the second anode region 57 and the buffer region 59 on the drift region 56 side. The entire drift region 56 is covered. By forming the front-side silicon oxide layer 66, the generation of electric charges at the interface between the silicon semiconductor layer 53 and the insulating layer 63 is suppressed, and the generation of a leakage current can be suppressed. The high thermal conductive layer 67 is formed so as to cover most of the surface of the front side silicon oxide layer 66 and extends right above the drift region 56. The high thermal conductive layer 67 is made of silicon nitride and has a thickness of 1.3 μm. The interlayer insulating film layer 68 is formed around and above the high thermal conductive layer 67 and is made of silicon oxide.

  Since the PIN diode 50 has a part of the insulating layer 63 that is the high thermal conductive layer 67, the PIN diode 50 drifts with the second anode region 57 even when a short circuit occurs in the circuit to which the PIN diode 50 is connected. The temperature of the p / n junction between the region 56 can be suppressed to a low temperature. Therefore, the semiconductor structure formed in the silicon semiconductor layer 53 can be protected from thermal destruction.

The horizontal semiconductor device of Example 5 is an ESD (Electro Static Discharge) protection diode. An ESD protection diode according to Example 5 will be described with reference to FIG.
As shown in FIG. 6, in the ESD protection diode 70, a support substrate 71, a buried silicon oxide layer 72, and a silicon semiconductor layer 73 are formed in this order. The main material of the support substrate 71 is silicon, and is fixed to the ground potential. The buried silicon oxide layer 72 has a thickness of about 4 μm, and the silicon semiconductor layer 73 has a thickness of about 1.5 μm. In the ESD protection diode 70, a high breakdown voltage can be realized by thinning the silicon semiconductor layer 73. Most of the surface of the silicon semiconductor layer 73 is covered with an insulating layer 83.

The silicon semiconductor layer 73 includes a p ⁺ -type first anode region 74 as a first semiconductor region and an n ⁺ -type first cathode region 75 as a second semiconductor region. The first anode region 74 is provided on a part of the surface of the silicon semiconductor layer 73. The first anode region 74 is surrounded by a p-type second anode region 76 having an impurity concentration lower than that of the first anode region 74. The second anode region 76 is formed in a range from the front surface to the back surface of the silicon semiconductor layer 73. The first cathode region 75 is provided on another part of the surface of the silicon semiconductor layer 73. The first cathode region 75 is surrounded by an n-type second cathode region 77 having an impurity concentration lower than that of the first cathode region 75. The second cathode region 77 is formed in a range from the front surface to the back surface of the silicon semiconductor layer 73.

The second anode region 76 and the second cathode region 77 are in contact with each other. That is, unlike the PIN diode of the fourth embodiment, the ESD protection diode 70 of the present embodiment does not have an n ⁻ type drift region. Therefore, even when a weak voltage is applied to the anode electrode 80, a current flows from the anode electrode 80 side to the cathode electrode 81 side. Therefore, by connecting the ESD protection diode 70 between an IC housing a semiconductor device such as an IGBT and an input / output signal pad, when a voltage due to static electricity is generated, the charge is transferred to the ESD protection diode 70. It is possible to flow to the ground through 70, and the IC is protected. In the present embodiment, in the silicon semiconductor layer 73, the region between the first anode region 74 and the first cathode region 75 in the second anode region 76 and the second cathode region 77 constitutes the central semiconductor region.

  A part of the surface of the first anode region 74 is not formed with the insulating layer 83, is in contact with the anode electrode 80 as the first main electrode, and is electrically connected to the anode electrode 80. Further, a part of the surface of the first cathode region 75 is not formed with the insulating layer 83, is in contact with the cathode electrode 81 as the second main electrode, and is electrically connected to the cathode electrode 81. .

  The insulating layer 83 includes a front side silicon oxide layer 86, a high thermal conductive layer 87, and an interlayer insulating film layer 88. The insulating layer 83 insulates the anode electrode 80 and the cathode electrode 81 from each other. Although not shown, the wirings connected to the electrodes 80 and 81 are insulated from each other by an interlayer insulating film formed on the surface of the insulating layer 83.

  The front-side silicon oxide layer 86 covers most of the region between the first anode region 74 and the first cathode region 75 in the second anode region 76 and the second cathode region 77 on the surface of the silicon semiconductor layer 73. Is formed. Since the front side silicon oxide layer 86 is formed, generation of electric charges at the interface between the silicon semiconductor layer 73 and the insulating layer 83 can be suppressed, and generation of leakage current can be suppressed. The high thermal conductive layer 87 is formed so as to cover the entire surface of the front side silicon oxide layer 86. The high thermal conductive layer 87 is made of silicon nitride and has a thickness of 1.3 μm. Further, the interlayer insulating film layer 88 is formed around and above the high thermal conductive layer 87 and is made of silicon oxide.

In the ESD protection diode 70, since the insulating layer 83 is partly the high thermal conductive layer 87, even if a short-circuit phenomenon occurs in the circuit to which the ESD protection diode 70 is connected, the second anode region 76. And the temperature of the p / n junction between the second cathode region 77 can be kept low. Therefore, the semiconductor structure formed in the silicon semiconductor layer 73 can be protected from thermal destruction.
(Other examples)

  In each of the above embodiments, the high thermal conductive layer is made of silicon nitride. However, the high thermal conductive layer may be made of aluminum nitride or other material having higher thermal conductivity than silicon oxide. . In each of the above embodiments, the high thermal conductive layer is made of a material having a higher heat capacity than silicon oxide, and this also effectively suppresses the local temperature rise of the silicon semiconductor layer. However, the high thermal conductive layer may be a material having a higher thermal conductivity than silicon oxide, and may not be a material having a high heat capacity.

  In each of the above embodiments, the high thermal conductive layer is formed on the surface of the silicon semiconductor layer via the silicon oxide layer to suppress the occurrence of leakage current. The high heat conductive layer may be directly formed. Even in such a case, when heat is generated in the silicon semiconductor layer, this heat can be conducted to the surroundings by the high thermal conductive layer. Moreover, in each said Example, although a part of insulating layer was used as the high heat conductive layer, it is good also considering the whole insulating layer as a high heat conductive layer.

  In each of the above embodiments, the thickness of the buried silicon oxide layer is 4 μm and the thickness of the silicon semiconductor layer is 1.5 μm. However, the thickness of the silicon semiconductor layer may be about 2 μm, and these thicknesses are not particularly limited. . That is, these thicknesses may be set so that the silicon semiconductor layer can realize a high breakdown voltage. Further, the thickness of the high thermal conductive layer is not limited to 1.3 μm, and may be any thickness as long as the heat of the silicon semiconductor layer can be appropriately conducted to the surroundings.

As mentioned above, although the specific example of the technique disclosed by this specification was demonstrated in detail, these are only illustrations and do not limit a claim. The technology described in the claims includes various modifications and changes of the specific examples illustrated above.
In addition, the technical elements described in the present specification or drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or the drawings achieves a plurality of objects at the same time, and has technical utility by achieving one of the objects.

1, 2: IGBT
11, 31, 51, 71: Support substrates 12, 32, 52, 72: Embedded silicon oxide layers 13, 33, 53, 73: Silicon semiconductor layer 14: Emitter region 15: Collector regions 16, 29, 36, 56: Drift Regions 17, 37: Body regions 18, 38: Body contact regions 19, 39, 59: Buffer regions 20: Emitter electrodes 21: Collector electrodes 22, 42: Gate insulating films 23, 43, 63, 83, 91: Insulating layers 24 44: Gate electrode 25, 45: Gate wiring 26, 46, 66, 86: Front side silicon oxide layers 27, 47, 67, 87: High thermal conductive layers 28, 48, 68, 88: Interlayer insulating film layer 29a: First Layer 29b: Second layer 30: LDMOS
34: source region 35: drain region 40: source electrode 41: drain electrode 50: PIN diode 54, 74: first anode region 55: cathode region 57, 76: second anode region 60, 80: anode electrodes 61, 81: Cathode electrode 70: ESD protection diode 75: First cathode region 77: Second cathode region

Claims (6)

A supporting substrate, a buried silicon oxide layer, a silicon semiconductor layer, and an insulating layer are formed in order, and a first main electrode and a second main electrode are in contact with the silicon semiconductor layer in a range where the insulating layer is not formed. And
A first semiconductor region in contact with the first main electrode; a second semiconductor region in contact with the second main electrode; and between the first semiconductor region and the second semiconductor region. And a central semiconductor region present in the
A lateral semiconductor device, wherein at least a part of the insulating layer is formed of a material having higher thermal conductivity than silicon oxide and is a high thermal conductive layer spreading right above the central semiconductor region.   The lateral semiconductor device according to claim 1, wherein the high thermal conductive layer is formed on a surface of the silicon semiconductor layer via a silicon oxide layer. A p-type body region surrounding the first semiconductor region and facing the gate electrode through a gate insulating film in the central semiconductor region, and adjacent to the body region and the second semiconductor An n-type drift region extending to the vicinity of the region,
The lateral semiconductor device according to claim 1, wherein the high thermal conductive layer is formed immediately above the drift region. The gate insulating film is composed of a silicon oxide layer;
The horizontal semiconductor device according to claim 3, wherein the high thermal conductive layer is formed on a surface of the silicon semiconductor layer via a silicon oxide layer having a thickness equal to or less than a thickness of the gate insulating film. The first semiconductor region is an anode region;
The second semiconductor region is a cathode region;
The lateral semiconductor device according to claim 1, wherein a p / n junction interface exists in the central semiconductor region.   The lateral semiconductor device according to claim 4, wherein the high thermal conductivity material is silicon nitride or aluminum nitride.

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