JP2010283205A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP2010283205A
JP2010283205A JP2009136203A JP2009136203A JP2010283205A JP 2010283205 A JP2010283205 A JP 2010283205A JP 2009136203 A JP2009136203 A JP 2009136203A JP 2009136203 A JP2009136203 A JP 2009136203A JP 2010283205 A JP2010283205 A JP 2010283205A
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igbt
fwd
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JP5577628B2 (en
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Koji Hotta
幸司 堀田
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Toyota Motor Corp
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device for securing reliability when applied with a current. <P>SOLUTION: The semiconductor device 11 includes a semiconductor substrate 12 where IGBTs having a plurality of IGBT cells, and FWDs 14 having a plurality of FWD cells arranged so as to be dispersed with the IGBs interposed therebetween are arranged side by side. Wire bonding regions 16 are arranged in positions corresponding to the FWDs 14 at one surface side of the semiconductor substrate 12. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

本発明は、ＩＧＢＴとＦＷＤとが併設された半導体基板を備える半導体装置に関するものである。   The present invention relates to a semiconductor device including a semiconductor substrate in which an IGBT and an FWD are provided.

従来、電力変換装置等に用いられる半導体装置として、ＩＧＢＴ（絶縁ゲート型バイポーラトランジスタ、Ｉｎｓｕｌａｔｅｄ Ｇａｔｅ Ｂｉｐｏｌａｒ Ｔｒａｎｓｉｓｔｏｒ）と、負荷電流を転流させるためのＦＷＤ（Ｆｒｅｅ Ｗｈｅｅｌｉｎｇ Ｄｉｏｄｅ）とを備えたものがあった（例えば特許文献１，２）。   2. Description of the Related Art Conventionally, semiconductor devices used for power conversion devices and the like have been provided with IGBTs (Insulated Gate Bipolar Transistors) and FWDs (Free Wheeling Diodes) for commutating load currents. (For example, Patent Documents 1 and 2).

特許文献１の半導体装置においては、半導体基板の主表面側に設けられたワイヤボンディング領域（ワイヤボンディング部）に金属ワイヤを接合することで通電が行われるようになっていた。   In the semiconductor device of Patent Document 1, energization is performed by bonding a metal wire to a wire bonding region (wire bonding portion) provided on the main surface side of the semiconductor substrate.

また、こうした半導体装置には、特許文献２に示すように、小型化のためにＩＧＢＴとＦＷＤとが共通の半導体基板に併設されたものがあった。すなわち、図３及び図４に示す従来の半導体装置１１１は、共通の半導体基板１１２にトレンチゲート構造のＩＧＢＴ部１１３とＦＷＤ部１１４とが併設されている。   In addition, as shown in Patent Document 2, such a semiconductor device includes one in which IGBT and FWD are provided on a common semiconductor substrate for miniaturization. That is, the conventional semiconductor device 111 shown in FIG. 3 and FIG. 4 is provided with an IGBT portion 113 and an FWD portion 114 having a trench gate structure on a common semiconductor substrate 112.

図３に示すように、半導体基板１１２の主表面側のアクティブ領域Ａｃ上には、ワイヤボンディング領域１１５，１１６が設けられている。ワイヤボンディング領域１１５は、ＩＧＢＴ部１１３のゲート電極に通電するためのワイヤが接合される領域である。また、ワイヤボンディング領域１１６は、ＩＧＢＴ部１１３のエミッタ電極及びＦＷＤ部１１４のアノード電極として機能する電極に通電するためのワイヤ１１７が接合される領域である。なお、半導体基板１１２の主表面側にはゲート電極用の配線をする必要があるために、ワイヤボンディング領域１１６は複数に分割される態様となっている。そして、ワイヤボンディング領域１１６に対してアルミニウム系のワイヤ１１７が超音波等で接合されることで、接合部１１８が形成される。   As shown in FIG. 3, wire bonding regions 115 and 116 are provided on the active region Ac on the main surface side of the semiconductor substrate 112. The wire bonding region 115 is a region where a wire for energizing the gate electrode of the IGBT portion 113 is joined. The wire bonding region 116 is a region where a wire 117 for energizing an electrode functioning as an emitter electrode of the IGBT portion 113 and an anode electrode of the FWD portion 114 is joined. Note that since the gate electrode wiring needs to be provided on the main surface side of the semiconductor substrate 112, the wire bonding region 116 is divided into a plurality of parts. Then, an aluminum-based wire 117 is bonded to the wire bonding region 116 with ultrasonic waves or the like, so that a bonding portion 118 is formed.

図４に示すように、半導体装置１１１においては、半導体基板１１２のＮ導電型（ｎ−）層１１９が、ＩＧＢＴ部１１３及びＦＷＤ部１１４のドリフト層となっている。また、Ｎ導電型（ｎ−）層１１９の主表面側にはＩＧＢＴ部１１３のベース領域となるＰ導電型（Ｐ）層１２０が形成されている。   As shown in FIG. 4, in the semiconductor device 111, the N conductivity type (n−) layer 119 of the semiconductor substrate 112 is a drift layer of the IGBT portion 113 and the FWD portion 114. In addition, a P conductivity type (P) layer 120 serving as a base region of the IGBT portion 113 is formed on the main surface side of the N conductivity type (n−) layer 119.

Ｐ導電型（Ｐ）層１２０には主表面側からＰ導電型（Ｐ）層１２０を貫通して底面がＮ導電型（ｎ−）層１１９に達するトレンチが複数形成されている。そして、各トレンチにはゲート絶縁膜１２１を介してゲート電極１２２が埋め込まれている。   A plurality of trenches are formed in the P conductivity type (P) layer 120 so as to penetrate the P conductivity type (P) layer 120 from the main surface side and reach the bottom surface to the N conductivity type (n−) layer 119. In each trench, a gate electrode 122 is embedded via a gate insulating film 121.

Ｐ導電型（Ｐ）層１２０の主表面側にはＩＧＢＴ部１１３のエミッタ領域となるＮ導電型（ｎ＋）領域１２３とＦＷＤ部１１４のアノード領域となるＰ導電型（Ｐ＋）領域１２４とが選択的に形成されている。そして、半導体基板１１２の主表面側には、各ゲート電極１２２を主表面側から覆いつつ、Ｐ導電型（Ｐ＋）領域１２４及びＮ導電型（ｎ＋）領域１２３の一部を露出するように層間絶縁膜１２５が形成されている。   On the main surface side of the P conductivity type (P) layer 120, an N conductivity type (n +) region 123 serving as an emitter region of the IGBT portion 113 and a P conductivity type (P +) region 124 serving as an anode region of the FWD portion 114 are selected. Is formed. Then, on the main surface side of the semiconductor substrate 112, an interlayer is formed so as to expose a part of the P conductivity type (P +) region 124 and the N conductivity type (n +) region 123 while covering each gate electrode 122 from the main surface side. An insulating film 125 is formed.

さらに、半導体基板１１２の主表面には、アルミニウム系材料からなる電極１２６がＮ導電型（ｎ＋）領域１２３及びＰ導電型（Ｐ＋）領域１２４と電気的に接続されるように形成されている。すなわち、電極１２６はエミッタ領域に接続されるエミッタ電極及びアノード領域に接続されるアノード電極として機能するようになっている。   Furthermore, an electrode 126 made of an aluminum-based material is formed on the main surface of the semiconductor substrate 112 so as to be electrically connected to the N conductivity type (n +) region 123 and the P conductivity type (P +) region 124. That is, the electrode 126 functions as an emitter electrode connected to the emitter region and an anode electrode connected to the anode region.

また、Ｎ導電型（ｎ−）層１１９の裏面側には、フィールドストップ層となるＮ導電型（ｎ）層１２７が形成されている。さらに、Ｎ導電型（ｎ）層１２７の裏面側には、ＩＧＢＴ部１１３のコレクタ領域となるＰ導電型（Ｐ＋）層１２８及びＦＷＤ部１１４のカソード領域となるＮ導電型（ｎ＋）領域１２９が形成されている。   Further, an N conductivity type (n) layer 127 to be a field stop layer is formed on the back side of the N conductivity type (n−) layer 119. Further, on the back side of the N conductivity type (n) layer 127, there are a P conductivity type (P +) layer 128 serving as a collector region of the IGBT portion 113 and an N conductivity type (n +) region 129 serving as a cathode region of the FWD portion 114. Is formed.

特開平６−３０２６３９号公報JP-A-6-302039 特開２００９−９４１０５号公報JP 2009-94105 A

ところで、半導体装置１１１においては、ワイヤ１１７を通じて大電流が繰り返し通電される。通電時には、ＩＧＢＴ部１１３及びＦＷＤ部１１４において損失に伴う発熱が生じるとともに、ワイヤ１１７においても同様に発熱が生じる。その結果、接合部１１８においては、半導体基板１１２側からの熱とワイヤ１１７側からの熱が伝わることにより、局所的な温度上昇が生じていた。そして、繰り返し通電に伴って接合部１１８で温度の上昇と下降が繰り返されることにより、熱応力によってワイヤ１１７が剥がれてしまうという問題があった。   By the way, in the semiconductor device 111, a large current is repeatedly supplied through the wire 117. During energization, heat is generated due to loss in the IGBT unit 113 and the FWD unit 114, and similarly, heat is generated in the wire 117. As a result, in the bonding portion 118, heat from the semiconductor substrate 112 side and heat from the wire 117 side are transmitted, and thus a local temperature rise has occurred. In addition, there is a problem that the wire 117 is peeled off due to thermal stress due to repeated increase and decrease in temperature at the joint 118 with repeated energization.

こうした問題に対応するため、特許文献１の半導体装置においては、ワイヤの材質及び線径、並びに接合部のサイズ等を規定することで、接合強度を確保するようにしていた。
一方、ワイヤボンディング領域に接続されるワイヤの本数は少ない方が製造効率上好ましいため、従来から、電流容量を確保しつつワイヤの本数を削減する工夫がなされてきた。しかし、ワイヤの本数を削減すると、ワイヤ１本あたりの電流密度が高まる分、発熱量も増すことになる。 In order to cope with such a problem, in the semiconductor device of Patent Document 1, the bonding strength is ensured by defining the material and diameter of the wire, the size of the bonding portion, and the like.
On the other hand, since it is preferable from the viewpoint of manufacturing efficiency that the number of wires connected to the wire bonding region is small, there has been conventionally devised to reduce the number of wires while securing the current capacity. However, if the number of wires is reduced, the amount of heat generated increases as the current density per wire increases.

すなわち、接続するワイヤの本数の削減や大電流化によって各ワイヤの電流容量が大きくなる場合には、ワイヤの材質及び線径、並びに接合部のサイズを適正化しても、接合部における信頼性を確保することができない虞があった。   In other words, if the current capacity of each wire increases due to a reduction in the number of wires to be connected or an increase in current, the reliability of the joint can be improved even if the material and diameter of the wire and the size of the joint are optimized. There was a possibility that it could not be secured.

この発明はこうした事情に鑑みてなされたものであり、その目的は、通電時における信頼性を確保することができる半導体装置を提供することにある。   The present invention has been made in view of such circumstances, and an object of the present invention is to provide a semiconductor device capable of ensuring reliability during energization.

以下、上記目的を達成するための手段及びその作用効果について記載する。
請求項１に記載の発明は、複数のＩＧＢＴセルを含むＩＧＢＴ部と、間に前記ＩＧＢＴ部を介して分散するように配置された、複数のＦＷＤセルを含むＦＷＤ部とが併設された半導体基板を備え、該半導体基板の一面側において、前記ＦＷＤ部と対応する位置にワイヤボンディング領域が設けられたことをその要旨とする。 In the following, means for achieving the above object and its effects are described.
The invention according to claim 1 is a semiconductor substrate in which an IGBT unit including a plurality of IGBT cells and an FWD unit including a plurality of FWD cells disposed so as to be distributed between the IGBT units are provided. And a wire bonding region is provided at a position corresponding to the FWD portion on one surface side of the semiconductor substrate.

同構成では、複数のＩＧＢＴセルを含むＩＧＢＴ部と、複数のＦＷＤセルを含むＦＷＤ部とが併設された半導体基板の一面側において、ＦＷＤ部と対応する位置にワイヤボンディング領域が設けられている。そして、ＩＧＢＴ部よりも通電時の発熱量が少ないＦＷＤ部に対応して設けられたワイヤボンディング領域にワイヤが接合されることにより、ワイヤと半導体基板との接合部における局所的な温度上昇を抑制することができる。そして、ＦＷＤ部を、間にＩＧＢＴ部を介して分散するように配置することにより、ワイヤとＩＧＢＴ部の熱をＦＷＤ部に拡散させて、全体の温度分布を調整することができる。これにより、接合部における温度上昇を抑制し、通電時における信頼性を確保することができる。   In this configuration, a wire bonding region is provided at a position corresponding to the FWD portion on one surface side of a semiconductor substrate where an IGBT portion including a plurality of IGBT cells and an FWD portion including a plurality of FWD cells are provided. In addition, the wire is bonded to the wire bonding region provided corresponding to the FWD portion that generates less heat when energized than the IGBT portion, thereby suppressing a local temperature rise at the bonding portion between the wire and the semiconductor substrate. can do. And by arrange | positioning an FWD part so that it may disperse | distribute via an IGBT part in between, the heat | fever of a wire and an IGBT part can be spread | diffused to an FWD part, and the whole temperature distribution can be adjusted. Thereby, the temperature rise in a junction part can be suppressed and the reliability at the time of electricity supply can be ensured.

本実施形態における半導体装置のワイヤボンディング模式図。The wire bonding schematic diagram of the semiconductor device in this embodiment. 図１のＡ−Ａ線における断面構造を示す模式図。The schematic diagram which shows the cross-section in the AA of FIG. 従来の半導体装置のワイヤボンディング模式図。The wire bonding schematic diagram of the conventional semiconductor device. 図３のＡ−Ａ線における断面構造を示す模式図。The schematic diagram which shows the cross-section in the AA of FIG.

以下、本発明を大容量の電力変換装置として用いられる半導体装置に具体化した一実施形態について、図１及び図２を併せ参照して説明する。
図１及び図２に示す本実施形態の半導体装置１１は、共通の半導体基板１２に複数のＩＧＢＴセルを含むＩＧＢＴ部１３と複数のＦＤＷセルを含むＦＷＤ部１４とが併設されている。 Hereinafter, an embodiment in which the present invention is embodied in a semiconductor device used as a large-capacity power conversion device will be described with reference to FIGS.
The semiconductor device 11 of this embodiment shown in FIGS. 1 and 2 is provided with an IGBT section 13 including a plurality of IGBT cells and an FWD section 14 including a plurality of FDW cells on a common semiconductor substrate 12.

図１に示すように、半導体基板１２の主表面側のアクティブ領域Ａｃには、ワイヤボンディング領域１５，１６が設けられている。ワイヤボンディング領域１５は、ＩＧＢＴ部１３のゲート電極に通電するためのワイヤが接合される領域である。また、ワイヤボンディング領域１６は、ＩＧＢＴ部１３のエミッタ電極及びＦＷＤ部１４のアノード電極として機能する電極に通電するためのワイヤ１７が接合される領域である。   As shown in FIG. 1, wire bonding regions 15 and 16 are provided in the active region Ac on the main surface side of the semiconductor substrate 12. The wire bonding region 15 is a region where a wire for energizing the gate electrode of the IGBT portion 13 is joined. The wire bonding region 16 is a region where a wire 17 for energizing an electrode functioning as an emitter electrode of the IGBT portion 13 and an anode electrode of the FWD portion 14 is joined.

なお、半導体基板１１２の主表面側にはゲート電極用の配線をする必要があるために、ワイヤボンディング領域１６は複数に分割される態様となっている。そして、ワイヤボンディング領域１６に対しては、アルミニウム系のワイヤ１７が超音波等で接合されることで、接合部１８が形成される。   In addition, since it is necessary to wire for the gate electrode on the main surface side of the semiconductor substrate 112, the wire bonding region 16 is divided into a plurality of parts. Then, an aluminum-based wire 17 is bonded to the wire bonding region 16 with ultrasonic waves or the like, so that a bonding portion 18 is formed.

そして、本実施形態の半導体装置１１は、ＩＧＢＴ部１３のアクティブ領域Ａｃ内に、ＦＷＤ部１４が、間にＩＧＢＴ部１３を介して分散するように配置され、半導体基板１２の一面側となる主表面側において、ＦＷＤ部１４と対応する位置にワイヤボンディング領域１６が設けられている点が、図３及び図４に示す従来の半導体装置１１１と異なる。   In the semiconductor device 11 according to the present embodiment, the FWD portions 14 are arranged in the active region Ac of the IGBT portion 13 so as to be dispersed via the IGBT portion 13 between them, and become the main surface of the semiconductor substrate 12. On the surface side, the point that the wire bonding region 16 is provided at a position corresponding to the FWD portion 14 is different from the conventional semiconductor device 111 shown in FIGS.

図２に示すように、半導体装置１１においては、半導体基板１２のＮ導電型（ｎ−）層１９が、ＩＧＢＴ部１３及びＦＷＤ部１４のドリフト層となっている。また、Ｎ導電型（ｎ−）層１９の主表面側にはＩＧＢＴ部１３のベース領域となるＰ導電型（Ｐ）層２０が形成されている。   As shown in FIG. 2, in the semiconductor device 11, the N conductivity type (n−) layer 19 of the semiconductor substrate 12 is a drift layer of the IGBT portion 13 and the FWD portion 14. In addition, a P conductivity type (P) layer 20 serving as a base region of the IGBT portion 13 is formed on the main surface side of the N conductivity type (n−) layer 19.

そして、ＩＧＢＴ部１３のＰ導電型（Ｐ）層２０には、主表面側からＰ導電型（Ｐ）層２０を貫通して底面がＮ導電型（ｎ−）層１９に達するトレンチが複数形成されている。そして、各トレンチにはゲート絶縁膜２１を介してゲート電極２２が埋め込まれている。   The P conductivity type (P) layer 20 of the IGBT portion 13 is formed with a plurality of trenches that penetrate the P conductivity type (P) layer 20 from the main surface side and reach the bottom surface to the N conductivity type (n−) layer 19. Has been. A gate electrode 22 is embedded in each trench through a gate insulating film 21.

さらに、ＩＧＢＴ部１３のＰ導電型（Ｐ）層２０の主表面側には、エミッタ領域となるＮ導電型（ｎ＋）領域２３とコンタクト領域となるＰ導電型（Ｐ＋）領域２４ａとが選択的に形成されている。そして、半導体基板１２の主表面側には、各ゲート電極２２を主表面側から覆いつつ、Ｐ導電型（Ｐ＋）領域２４ａ及びＮ導電型（ｎ＋）領域２３の一部を露出するように層間絶縁膜２５が形成されている。   Further, an N conductivity type (n +) region 23 serving as an emitter region and a P conductivity type (P +) region 24a serving as a contact region are selectively provided on the main surface side of the P conductivity type (P) layer 20 of the IGBT portion 13. Is formed. Then, on the main surface side of the semiconductor substrate 12, the gate electrode 22 is covered from the main surface side, and an interlayer is formed so as to expose a part of the P conductivity type (P +) region 24a and the N conductivity type (n +) region 23. An insulating film 25 is formed.

一方、ＦＷＤ部１４のＰ導電型（Ｐ）層２０には、アノード領域となるＰ導電型（ｐ＋）領域２４ｂが選択的に形成されている。
そして、半導体基板１２の主表面には、アルミニウム系材料からなる電極２６がＮ導電型（ｎ＋）領域２３、Ｐ導電型（Ｐ＋）領域２４ａ及びＰ導電型（Ｐ＋）領域２４ｂと電気的に接続されるように形成されている。すなわち、電極１２６はエミッタ領域に接続されるエミッタ電極及びアノード領域に接続されるアノード電極として機能するようになっている。 On the other hand, the P conductivity type (P) layer 20 of the FWD portion 14 is selectively formed with a P conductivity type (p +) region 24b serving as an anode region.
On the main surface of the semiconductor substrate 12, an electrode 26 made of an aluminum-based material is electrically connected to the N conductivity type (n +) region 23, the P conductivity type (P +) region 24a, and the P conductivity type (P +) region 24b. It is formed to be. That is, the electrode 126 functions as an emitter electrode connected to the emitter region and an anode electrode connected to the anode region.

また、Ｎ導電型（ｎ−）層１９の裏面側には、フィールドストップ層となるＮ導電型（ｎ）層２７が形成されている。さらに、Ｎ導電型（ｎ）層２７の裏面側には、ＩＧＢＴ部１３のコレクタ領域となるＰ導電型（Ｐ＋）層２８及びＦＷＤ部１４のカソード領域となるＮ導電型（ｎ＋）領域２９が形成されている。そして、Ｐ導電型（Ｐ＋）層２８及びＮ導電型（ｎ＋）領域２９は、ＩＧＢＴ部１３のコレクタ電極及びＦＷＤ部１４のカソード電極として機能する電極基板に接続されるようになっている。   Further, an N conductivity type (n) layer 27 serving as a field stop layer is formed on the back surface side of the N conductivity type (n−) layer 19. Further, on the back side of the N conductivity type (n) layer 27, there are a P conductivity type (P +) layer 28 that becomes a collector region of the IGBT portion 13 and an N conductivity type (n +) region 29 that becomes a cathode region of the FWD portion 14. Is formed. The P conductivity type (P +) layer 28 and the N conductivity type (n +) region 29 are connected to an electrode substrate that functions as a collector electrode of the IGBT portion 13 and a cathode electrode of the FWD portion 14.

次に、ＩＧＢＴ部１３の動作を説明する。
エミッタ電極とコレクタ電極との間に所定のコレクタ電圧を印可するとともに、エミッタ電極とゲート電極２２との間に所定のゲート電圧を印可すると、エミッタ領域であるＮ導電型（ｎ＋）領域２３とＮ導電型（ｎ−）層１９との間の部分（チャネル領域）がＮ型に反転してチャネルが形成される。すると、このチャネルを通じて、エミッタ電極からＮ導電型（ｎ−）層１９に電子が注入される。 Next, the operation of the IGBT unit 13 will be described.
When a predetermined collector voltage is applied between the emitter electrode and the collector electrode and a predetermined gate voltage is applied between the emitter electrode and the gate electrode 22, the N conductivity type (n +) region 23 as the emitter region and the N A portion (channel region) between the conductive type (n−) layer 19 is inverted to N-type to form a channel. Then, electrons are injected from the emitter electrode into the N conductivity type (n−) layer 19 through this channel.

そして、注入された電子により、コレクタ領域であるＰ導電型（Ｐ＋）層２８とＮ導電型（ｎ−）層１９が順バイアスされ、Ｐ導電型（Ｐ＋）層２８からホールが注入されてＮ導電型（ｎ−）層１９の抵抗が大幅に下がり、ＩＧＢＴの電流容量が増大する。   Then, by the injected electrons, the P conductivity type (P +) layer 28 and the N conductivity type (n−) layer 19 which are collector regions are forward-biased, and holes are injected from the P conductivity type (P +) layer 28 to form N The resistance of the conductivity type (n−) layer 19 is greatly reduced, and the current capacity of the IGBT is increased.

また、エミッタ電極とゲート電極２２との間に印可されていたゲート電圧を０Ｖにする、又は逆バイアスすると、Ｎ型に反転していたチャネル領域がＰ型に戻り、エミッタ電極からの電子の注入が止まる。これにより、Ｐ導電型（Ｐ＋）層２８からのホールの注入も止まる。その後、Ｎ導電型（ｎ−）層１９に蓄積されていたキャリア（電子とホール）がそれぞれコレクタ電極とエミッタ電極から排出されるか、互いに再結合して消滅する。   Further, when the gate voltage applied between the emitter electrode and the gate electrode 22 is set to 0 V or reverse biased, the channel region that has been inverted to the N type returns to the P type, and electrons are injected from the emitter electrode. Stops. Thereby, the injection of holes from the P conductivity type (P +) layer 28 is also stopped. Thereafter, the carriers (electrons and holes) accumulated in the N conductivity type (n−) layer 19 are discharged from the collector electrode and the emitter electrode, respectively, or recombine with each other and disappear.

次に、ＦＷＤ部１４の動作を説明する。
ＦＷＤ部１４においては、アノード電極である電極２６とＮ導電型（ｎ−）層１９との間にアノード電圧（順バイアス）を印可し、アノード電圧が閾値を超えると、アノード領域であるＰ導電型（ｐ＋）領域２４ｂとＮ導電型（ｎ−）層１９とが順バイアスされ、ＦＷＤが導電する。一方、電極２６とＮ導電型（ｎ−）層１９との間に逆バイアスを印可すると、空乏層がアノード領域よりＮ導電型（ｎ−）層１９側へ伸びることで、逆方向耐圧を保持することができる。 Next, the operation of the FWD unit 14 will be described.
In the FWD section 14, an anode voltage (forward bias) is applied between the electrode 26 serving as the anode electrode and the N conductivity type (n−) layer 19, and when the anode voltage exceeds a threshold value, the P conductivity serving as the anode region is applied. The type (p +) region 24b and the N conductivity type (n−) layer 19 are forward biased, and the FWD conducts. On the other hand, when a reverse bias is applied between the electrode 26 and the N conductivity type (n−) layer 19, the depletion layer extends from the anode region to the N conductivity type (n−) layer 19 side, thereby maintaining a reverse breakdown voltage. can do.

ところで、ＩＧＢＴ部１３及びＦＷＤ部１４においては、通電時に電流が流れることで発生する定常損失やスイッチ動作の際に発生するスイッチング損失が原因となって発熱を生じる。また、通電時には各ワイヤ１７も発熱するため、ワイヤ１７側からの熱と半導体基板１２側の熱とにより、接合部１８において局所的な温度上昇が生じる虞がある。   By the way, in the IGBT part 13 and the FWD part 14, heat is generated due to a steady loss caused by a current flowing during energization and a switching loss caused during a switch operation. Further, since each wire 17 also generates heat when energized, there is a possibility that a local temperature rise may occur in the joint portion 18 due to heat from the wire 17 side and heat from the semiconductor substrate 12 side.

ここで、本実施形態の半導体装置１１は、ＦＷＤ部１４の直上にのみワイヤボンディング領域１６が配置されている。そして、一般にＦＷＤ部１４はＩＧＢＴ部１３よりも損失が少ないため、通電時の発熱量も小さい傾向にある。したがって、ＦＷＤ部１４の直上に配置されたワイヤボンディング領域１６にワイヤ１７が接合されることにより、ワイヤ１７とＩＧＢＴ部１３の熱はＦＷＤ部１４に拡散され、接合部１８における温度上昇が抑制される。   Here, in the semiconductor device 11 of the present embodiment, the wire bonding region 16 is disposed only immediately above the FWD portion 14. And generally, since the FWD part 14 has less loss than the IGBT part 13, the amount of heat generated during energization tends to be small. Therefore, when the wire 17 is joined to the wire bonding region 16 disposed immediately above the FWD portion 14, the heat of the wire 17 and the IGBT portion 13 is diffused to the FWD portion 14, and the temperature rise at the joint 18 is suppressed. The

これに対して、従来の半導体装置１１１においては、ワイヤボンディング領域１１６と対応する位置にはＩＧＢＴ部１１３とＦＷＤ部１１４とが混在しているために、ワイヤ１１７とＩＧＢＴ部１１３の発熱により接合部１１８における温度上昇が顕著となる。   On the other hand, in the conventional semiconductor device 111, the IGBT portion 113 and the FWD portion 114 are mixed at a position corresponding to the wire bonding region 116, so that the junction portion is generated by the heat generated by the wire 117 and the IGBT portion 113. The temperature rise at 118 is significant.

すなわち、本実施形態の半導体装置１１においては、半導体基板１２の温度分布を均一化させるのに適切なサイズ及び間隔で配置したＦＷＤ部１４と対応する位置にワイヤボンディング領域１６を設けたことで、接合部１８における温度上昇を抑制することが可能となる。したがって、繰り返し通電に伴う接合部１８の温度変化の幅を小さくすることにより、熱応力による接合部１８の劣化やワイヤ１７の剥離を抑制することができる。   That is, in the semiconductor device 11 of the present embodiment, the wire bonding region 16 is provided at a position corresponding to the FWD portion 14 arranged at an appropriate size and interval to make the temperature distribution of the semiconductor substrate 12 uniform. It is possible to suppress the temperature rise at the joint 18. Therefore, by reducing the width of the temperature change of the joint portion 18 due to repeated energization, deterioration of the joint portion 18 and peeling of the wire 17 due to thermal stress can be suppressed.

以上説明した本実施形態によれば、以下のような効果を得ることができる。
（１）複数のＩＧＢＴセルを含むＩＧＢＴ部１３と、複数のＦＷＤセルを含むＦＷＤ部１４とが併設された半導体基板１２の主表面側において、ＦＷＤ部１４と対応する位置にワイヤボンディング領域１６が設けられている。そして、ＩＧＢＴ部１３よりも通電時の発熱量が少ないＦＷＤ部１４に対応して設けられたワイヤボンディング領域１６にワイヤ１７が接合されることにより、接合部１８における局所的な温度上昇を抑制することができる。 According to this embodiment described above, the following effects can be obtained.
(1) On the main surface side of the semiconductor substrate 12 where the IGBT unit 13 including a plurality of IGBT cells and the FWD unit 14 including a plurality of FWD cells are provided, the wire bonding region 16 is provided at a position corresponding to the FWD unit 14. Is provided. And the wire 17 is joined to the wire bonding area | region 16 provided corresponding to the FWD part 14 with less calorific value at the time of energization than the IGBT part 13, and the local temperature rise in the junction part 18 is suppressed. be able to.

そして、ＦＷＤ部１４を、間にＩＧＢＴ部１３を介して分散するように配置することにより、ワイヤ１７とＩＧＢＴ部１３の熱をＦＷＤ部１４に拡散させて、全体の温度分布を調整することができる。これにより、接合部１８における温度上昇を抑制し、通電時における信頼性を確保することができる。   And by arrange | positioning the FWD part 14 so that it may disperse | distribute via the IGBT part 13, it can diffuse the heat | fever of the wire 17 and the IGBT part 13 to the FWD part 14, and can adjust the whole temperature distribution. it can. Thereby, the temperature rise in the junction part 18 can be suppressed and the reliability at the time of electricity supply can be ensured.

（２）半導体基板１２において、ＦＷＤ部１４を、間にＩＧＢＴ部１３を介して分散するように配置することで、全体の温度分布を調整することができる。これにより、ワイヤ１７の電流容量を確保しつつ、接合部１８の温度上昇を抑制することができる。したがって、接合部１８は従来の半導体装置１１１よりも電力集中に耐えることができるため、ワイヤ１７の本数を削減することで製造効率を向上させ、コストダウンに貢献することができる。   (2) In the semiconductor substrate 12, by disposing the FWD part 14 so as to be dispersed via the IGBT part 13, the overall temperature distribution can be adjusted. Thereby, the temperature rise of the junction part 18 can be suppressed, ensuring the current capacity of the wire 17. Therefore, since the junction 18 can withstand more power concentration than the conventional semiconductor device 111, reducing the number of wires 17 can improve manufacturing efficiency and contribute to cost reduction.

なお、上記実施形態は以下のように変更して実施することもできる。
・ワイヤボンディング領域１６は電極２６の表面側に設けてもよいし、電極２６の表面側に別途ボンディングパットを形成するようにしてもよい。 In addition, the said embodiment can also be changed and implemented as follows.
The wire bonding region 16 may be provided on the surface side of the electrode 26, or a separate bonding pad may be formed on the surface side of the electrode 26.

・フィールドストップ層は省略してもよい。
・ＩＧＢＴセルはトレンチゲート構造に限らず、例えばプレーナ型のセル構造を採用してもよい。 -The field stop layer may be omitted.
The IGBT cell is not limited to the trench gate structure, and may be a planar cell structure, for example.

・ＩＧＢＴセル及びＦＷＤセルのＩＧＢＴ部１３及びＦＷＤ部１４における配置数や、ＩＧＢＴ部１３とＦＷＤ部１４のサイズ及び配置、ワイヤ１７の本数や接合部１８の数は任意に設定することができる。   The number of IGBT cells and FWD cells arranged in the IGBT part 13 and the FWD part 14, the size and arrangement of the IGBT part 13 and the FWD part 14, the number of wires 17 and the number of joints 18 can be arbitrarily set.

・半導体装置１１は、ｎ−ｐ−ｎ型のＩＧＢＴセルとしてもよいし、ｐとｎの導電型を逆にしたｐ−ｎ−ｐ型のＩＧＢＴセルとしてもよい。
・ワイヤ１７は、より断面積の大きいテープ形状やリボン形状のものを用いてもよい。 The semiconductor device 11 may be an npn type IGBT cell, or may be a pnp type IGBT cell in which the conductivity types of p and n are reversed.
The wire 17 may be a tape shape or ribbon shape having a larger cross-sectional area.

１１…半導体装置、１２…半導体基板、１３…ＩＧＢＴ部、１４…ＦＷＤ部、１６…ワイヤボンディング領域。   DESCRIPTION OF SYMBOLS 11 ... Semiconductor device, 12 ... Semiconductor substrate, 13 ... IGBT part, 14 ... FWD part, 16 ... Wire bonding area | region.

Claims (1)

複数のＩＧＢＴセルを含むＩＧＢＴ部と、間に前記ＩＧＢＴ部を介して分散するように配置された、複数のＦＷＤセルを含むＦＷＤ部とが併設された半導体基板を備え、
該半導体基板の一面側において、前記ＦＷＤ部と対応する位置にワイヤボンディング領域が設けられたことを特徴とする半導体装置。 A semiconductor substrate provided with an IGBT section including a plurality of IGBT cells and an FWD section including a plurality of FWD cells arranged so as to be dispersed through the IGBT section between the IGBT sections;
A semiconductor device, wherein a wire bonding region is provided at a position corresponding to the FWD portion on one surface side of the semiconductor substrate.
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