JP2014011213A - Diode and power conversion device using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a diode capable of obtaining high recovery breakdown resistance due to a simple structure, and a power conversion device using the same.SOLUTION: A semiconductor substrate 1 in a diode comprises: an anode p layer AP in contact with a principal surface 10 of an anode side; an n-drift layer NM adjacent to the anode p layer AP; a cathode n layer in contact with a principal surface 20 of a cathode side and having a higher impurity concentration than the n-drift layer NM; and a termination p layer TP in contact with the principal surface of the cathode side.

Description

  The present invention relates to a semiconductor device and a power conversion device using the same.

  Free power converters are used in reverse parallel connection with semiconductor switching elements such as insulated gate bipolar transistors (hereinafter abbreviated as IGBT (Insulated Gate Bipolar Transistor)) and MOS (abbreviated as Metal-Oxide-Semiconductor) transistors. The wheel diode is required to improve the recovery (reverse recovery) characteristics as the drive frequency of the power converter increases. Specifically, there is a demand for softening recovery characteristics and improving resistance to recovery breakdown (destruction caused by a large current flowing in a high electric field portion at the boundary between the active region and termination region of the diode).

  As a means for realizing softening of recovery characteristics, in the diode described in Patent Document 1, a p-type semiconductor region is locally provided in the semiconductor region on the cathode electrode side. In this diode, when the reverse voltage applied between the anode electrode and the cathode electrode of the diode during recovery increases, holes are injected from the p-type semiconductor region into the n-drift region. This hole serves as a source of recovery current and moderates the time variation of the recovery current in the tail current portion, so that soft recovery characteristics can be obtained.

  In the diode described in Patent Document 2 as means for improving the resistance to recovery breakdown, the anode p layer made of p-type impurities and the anode electrode are not in contact with the active region side end of the termination region of the diode. A region (hereinafter referred to as a HIRC (High Reverse Recovery dI / dt Capability) region) is provided. Recovery breakdown occurs when a large recovery current at the time of recovery flows into the high electric field region at the end of the p-type semiconductor region, but by providing the HIRC region, the electric field and current at the boundary between the active region and the termination region of the diode Reduces density and improves fracture resistance.

JP-A-8-316501 JP-A-9-232597

  In the conventional diode described in Patent Document 1, the n-type semiconductor region and the p-type semiconductor region must be patterned using a lithography process on the cathode electrode side on the back surface of the diode, which complicates the manufacturing process and reduces the cost. It will increase. In particular, in a diode having a withstand voltage of 600 V or 1.2 kV, the thickness of the Si substrate must be reduced to about 70 μm to 140 μm in order to reduce the n-drift region, and the backside lithography process must be performed. Accompanied by difficulties.

  In the conventional diode described in Patent Document 2, the width of the HIRC region is as large as about 100 μm for a diode with a withstand voltage of 600 V and about 400 μm with a diode with a withstand voltage of 3.3 kV, and the chip area increases accordingly. Furthermore, as the drive frequency of the power converter increases and the current density flowing through the semiconductor chip increases, the width of the HIRC region must be further increased in order to further improve the resistance to recovery breakdown.

  The present invention has been made in consideration of the above problems, and an object of the present invention is to provide a diode capable of obtaining a high recovery breakdown resistance with a simple structure and a power converter using the same.

  In order to solve the above problems, a diode according to the present invention includes a semiconductor substrate having first and second main surfaces, and the semiconductor substrate includes a first semiconductor layer of a first conductivity type in contact with the first main surface; A second conductive type second semiconductor layer adjacent to the first semiconductor layer; a second conductive type third semiconductor layer in contact with the second main surface and having a higher impurity concentration than the second semiconductor layer; and a second main type And a termination region including a fourth semiconductor layer of the first conductivity type in contact with the surface. Further, the first main electrode is electrically connected to the first semiconductor layer on the first main surface, and the second main electrode is electrically connected to the third semiconductor layer on the second main surface.

  Here, the first main surface and the second main surface are, for example, an anode main surface and a cathode main surface. The first conductivity type and the second conductivity type are p-type or n-type, and are opposite conductivity types. For example, the first conductivity type and the second conductivity type are p-type and n-type, respectively. For example, the first main electrode and the second main electrode are an anode electrode and a cathode electrode, respectively.

  According to the above means, by having the termination region including the first conductive type fourth semiconductor layer in contact with the second main surface, the electric field strength at the end of the first semiconductor layer at the time of recovery can be relaxed. Accordingly, the resistance to recovery destruction is improved.

  Preferably, in the diode according to the present invention, the semiconductor substrate further includes a fifth semiconductor layer of a first conductivity type in contact with the second main surface and adjacent to the third semiconductor layer, and the second main surface has a first semiconductor layer. The five semiconductor layers are electrically connected to the second main electrode. As a result, the resistance to recovery breakdown is improved, and the recovery characteristics are softened by the accumulation of carriers injected from the fifth semiconductor layer. The fifth semiconductor layer is, for example, a so-called FLR (Field Limiting Ring) or a guard ring.

  According to the power conversion device in which the diode according to the present invention is connected in antiparallel to the semiconductor switching element as described above, the resistance to recovery breakdown of the diode is improved, so that the power conversion device is less likely to fail and its reliability is improved. Improves.

  According to the present invention, the resistance to recovery breakdown of the diode is improved. Furthermore, the reliability of the power converter can be improved by applying the diode according to the present invention.

  Other features of the present invention will become apparent from the following description of the present specification and the description of the drawings.

It is sectional drawing of the diode which is one Embodiment of this invention. It is a voltage-current waveform of the recovery characteristic of the diode of a prior art and embodiment. It is sectional drawing of the diode which is one Embodiment of this invention. It is sectional drawing of the diode which is one Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the diode of FIG. It is sectional drawing which shows the manufacturing method of the diode of FIG. It is sectional drawing which shows the manufacturing method of the diode of FIG. It is sectional drawing which shows the manufacturing method of the diode of FIG. It is sectional drawing which shows the manufacturing method of the diode of FIG. It is sectional drawing which shows the manufacturing method of the diode of FIG. It is sectional drawing which shows the manufacturing method of the diode of FIG. It is sectional drawing which shows the manufacturing method of the diode of FIG. It is sectional drawing of the diode which is one Embodiment of this invention. It is sectional drawing of the diode which is one Embodiment of this invention. It is sectional drawing of the diode which is one Embodiment of this invention. It is sectional drawing of the diode which is one Embodiment of this invention. It is sectional drawing of the diode which is one Embodiment of this invention. It is a circuit diagram of a power converter which is one embodiment of the present invention.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In addition, in the figure, the same code | symbol is attached | subjected to the thing which has the same thing, an equivalent, and the same function. In the following embodiments, a diode using an n-type silicon (hereinafter referred to as Si) wafer will be described, but a p-type Si wafer can also be used. Note that the notation n +, n, n− in the text or drawings indicates that the conductivity type of the semiconductor layer is n-type, and the impurity concentration is relatively high in the order of n +, n, n−. The same applies to the notations p +, p, p-.

  FIG. 1 shows a structure of a diode according to an embodiment of the present invention, and shows a cross section including a termination region for ensuring a withstand voltage and a part of an active region through which a main current flows. In addition, this sectional drawing has shown the half of the whole cross section of the diode which is this embodiment. That is, the left end portion of the cross section in the figure is the central portion of the actual active region. The semiconductor substrate 1 made of Si in the present diode is provided on the entire anode side, and is located at the anode p layer AP made of a p-type impurity region and in the longitudinal direction of the semiconductor substrate 1, that is, at the center in the thickness direction, and the anode p A pn junction is formed adjacent to the layer AP, and an n-drift layer NM composed of an n-type impurity region having an impurity concentration lower than that of the anode p layer AP, and provided locally in the active region on the cathode side. A cathode n layer KN which is adjacent to and in contact with the n-drift layer NM and has a higher impurity concentration than the n-drift layer NM, and a termination region on the cathode side, and has an impurity concentration higher than that of the n-drift layer NM. Are provided in a plurality of termination p layers TP composed of high p-type impurity regions and a cathode n layer KN. It consists of a p-type impurity region which is in contact with the cathode n layer KN in a direction parallel to each main surface and forms a pn junction adjacent to the n-drift layer NM in the vertical direction and has a higher impurity concentration than the n-drift layer NM. A plurality of cathode p layers KP are provided.

  The anode p layer KP is in contact with the anode main surface 10 of the semiconductor substrate 1 and is electrically connected to the anode electrode AE by ohmic contact on the anode main surface 10 in the active region and the termination region. The cathode n layer KN and the cathode p layer KP are in contact with the cathode-side main surface 20 of the semiconductor substrate, and are electrically connected to the cathode electrode KE by ohmic contact on the cathode-side main surface 20 in the active region. Each termination p layer TP is in contact with the anode main surface 10 of the semiconductor substrate 1 and is electrically connected to the so-called field plate electrode FP by ohmic contact at the cathode main surface 20 of the semiconductor substrate in the termination region. . An oxide film OX is provided on the cathode-side main surface 20 between two adjacent termination p layers and between adjacent cathode electrodes KE and termination p layers, and the field plate electrodes FP and the cathode electrodes KE are separated from each other. Yes. Since the end portions of the cathode electrode KE and each field plate electrode FP extend on the oxide film OX, the cathode electrode KE and each field plate electrode FP are separated from the n-drift layer NM and are not in contact with the n-drift layer NM.

In the active region, the n-drift layer NM is located at the center of the semiconductor substrate in the vertical direction, the anode p layer AP is located on the entire anode side, and the cathode n layer KN and cathode p are locally located on the cathode electrode side. Layer KP is located. In order to form the semiconductor substrate of the diode of this embodiment, an FZ (Floating Zone) Si wafer or an Si wafer having an epitaxial layer grown on the surface thereof is used. Therefore, the n-drift layer NM is formed from a portion of the original wafer that is not doped with impurities. The specific resistance and thickness of the n-drift layer NM vary depending on the withstand voltage and recovery characteristics of the diode. For example, in the case of a diode having a withstand voltage of 600 V, each of a diode having a withstand voltage of about 25 Ωcm and 70 μm and 1.2 kV It is about 55Ωcm and 120μm. The peak concentration of the p-type impurity in the anode p layer AP is set to about 1 × 10 ¹⁵ to 1 × 10 ¹⁹ / cm ³ .

The cathode p layer KP has a planar shape such as a dot (circle) shape or a stripe shape on the cathode side main surface 20. The cathode p layer KP is desirably arranged at equal intervals in order to soften the recovery characteristics. For example, stripe-shaped cathode p layers KP having a width of 10 μm or dots having a diameter of 10 μm are arranged at equal intervals with an interval of 10 μm. The peak concentration of the n-type impurity in the cathode n layer KN is about 1 × 10 ¹⁷ to 1 × 10 ²¹ / cm ^3, but is preferably higher than the peak concentration of the p-type impurity in the anode p layer AP. As a result, when the anode electrode AE and the cathode electrode KE are connected to an external circuit and the main current flows through the active region, electrons and holes (holes) are present on the cathode side rather than the anode side in the semiconductor substrate 1. The density increases, the amount of holes remaining on the cathode side during recovery increases, and the recovery characteristics can be made soft. The peak concentration of the p-type impurity in the cathode p layer KP is set to about 1 × 10 ¹⁵ to 1 × 10 ¹⁹ / cm ³ . The higher the peak concentration of the p-type impurity in the cathode p layer KP, the more holes are injected during recovery, and the recovery characteristics can be softened.

  In the termination region, the n-drift layer NM is located at the center of the semiconductor substrate 1 in the vertical direction, like the active region, the anode p layer AP is located on the entire anode side, and the cathode side is located on the cathode side. A termination p layer TP made of a p-type impurity region, a field plate electrode FP made of a conductor such as aluminum or polysilicon, and an oxide film OX separating the field plate electrode FP and the n − drift layer NM are located. On the anode side, the anode p layer AP is formed on the entire surface of the wafer without performing processing by the lithography technique. That is, there is no local structure on the anode side. Thereby, the structure of the anode can be made simply and at low cost. In order to relieve the electric field and increase the breakdown voltage, the anode p layer AP has a high concentration p-type impurity region on the anode electrode AE side and a p-type impurity region located on the n-drift layer NM side at a lower concentration than this. It may consist of layers. Also in this case, two p-type impurity layers are formed on the entire surface of the wafer without performing processing using a lithography technique.

  In the termination region, a termination structure is formed on the cathode electrode KE side. For example, in the termination region around the semiconductor substrate 1, a ring-shaped termination p layer TP (so-called FLR (abbreviation of Field Limiting Ring)) is formed so as to surround the active region, and a field plate electrode FP is formed on each termination p layer TP. Arrange. When a reverse voltage is applied to the diode, the depletion layer extending from the anode p layer AP to the n-drift layer NM further spreads between the termination p layers TP, thereby relaxing the electric field applied to the end of the termination region. Further, by adopting a structure in which each field plate electrode FP extends from the termination p layer TP onto the oxide film OX, the extension of the depletion layer between the termination p layers TP is controlled, and the electric field strength between the termination p layers TP is reduced. At the same time, the voltage sharing after each termination p layer is made uniform. Thereby, the withstand voltage of the diode is improved, and a desired withstand voltage can be secured.

  2 (a) and 2 (b) show recovery characteristics when switching between the diode shown in FIG. 1 and a conventional diode in which a termination layer is provided on the anode side and a local p layer is not provided on the cathode side. A comparative example of current and voltage waveforms is shown. As shown in FIG. 2B, in the conventional diode, the current change (di / dt) in the tail portion is large, the voltage jumps due to the parasitic inductance of the main circuit wiring, and ringing occurs. On the other hand, as shown in FIG. 2A, in the diode of FIG. 1, the current in the tail portion is gently reduced by the holes injected from the cathode p layer KP locally provided on the cathode side, and the voltage Bounce and ringing can be suppressed.

  In the diode shown in FIG. 1, when a high voltage is applied during recovery, the anode p layer AP terminates at the end face of the semiconductor substrate and does not have an end in the anode main surface. The electric field at the end portion is reduced as compared with the case where the end portion is provided inside, and current concentration at the end portion hardly occurs. On the cathode side, the depletion layer extends from the boundary between the cathode n layer KN and the n− drift layer NM at the end of the cathode n layer KN located at the boundary between the active region and the termination region, as indicated by a in FIG. As a result, the electric field is reduced. Therefore, destruction at the end a during recovery is unlikely to occur.

  In the diode of FIG. 1, the cathode n layer KN is located at the boundary between the active region and the termination region, and the cathode side of the active region is terminated with the cathode n layer KN on the termination region side. As shown, a structure terminated with a cathode p layer KP may be used. Even in this case, a forward voltage is applied to the pn junction at the boundary between the cathode p layer KP and the n-drift layer NM located at the boundary between the active region and the termination region on the cathode side at the time of recovery. Since the depletion layer does not extend and the electric field strength is reduced, the end a is not easily broken.

  FIG. 4 shows another embodiment of the present invention. Unlike the embodiment of FIG. 1, the cathode p layer KP is not provided, and the cathode n layer KN is formed on the entire surface of the active region on the cathode side main surface 20 side. Similar to the embodiment of FIG. 1, there is a termination structure on the cathode-side main surface 20 side, and no patterned structure on the anode-side main surface 10 side. In the diode of the embodiment of FIG. 4 as well, as with the diode of FIG. 1, the electric field strength at the end (a) of the cathode n layer KN is reduced during recovery, so that the resistance to recovery breakdown is improved.

  Next, an example of a method for manufacturing the diode shown in FIG. 1 will be described with reference to FIGS. 5 to 12 are cross-sectional views of relevant parts showing a method of manufacturing the diode of FIG. Each drawing shows a cross section of a part of the active region and the termination region as in FIG. 5 to 12 show only a cross section of one diode. Until dicing, each manufacturing process is performed in the state of a Si wafer, and a large number of diodes are formed on one Si wafer. Is done.

  First, FIG. 5 will be described. As the Si wafer, an FZ wafer having a specific resistance corresponding to a withstand voltage is used, and the bulk of the FZ wafer is used for the n-drift layer NM. Then, the Si wafer is thermally oxidized to form an oxide film OX on the entire surface of the wafer. Next, in a lithography process for forming the cathode p-layer KP and the termination p-layer TP on the cathode side, a resist RES is applied, exposed, and developed to open a part of the resist RES. Subsequently, the oxide film exposed at the opening of the resist RES is removed by wet etching. Thereafter, the p-type impurities of the cathode p layer KP and the termination p layer TP are simultaneously ion-implanted. When the optimized p-type impurity concentration is set for each of the cathode p layer KP and the termination p layer TP, the cathode p layer KP and the termination p layer TP are ion-implanted separately.

  Next, FIG. 6 will be described. In order to form the cathode n layer KN, a resist RES is applied, exposed, and developed in a lithography process, and a part of the resist RES is opened. Subsequently, n-type impurities in the cathode n layer KN are ion-implanted using the oxide film OX in the opening of the resist RES as a through film. The order of the ion implantation of the p-type impurity described in FIG. 5 and the ion implantation of the n-type impurity described in FIG. 6 may be reversed.

  Next, FIG. 7 will be described. Annealing is performed to activate and diffuse impurities in the cathode p layer KP, termination p layer TP, and cathode n layer KN. Thermal oxidation is also performed before or after the annealing to grow an oxide film OX.

  Next, FIG. 8 will be described. In a lithography process for making contact with the Si surface, a resist RES is applied, exposed, and developed to open a part of the resist RES. The oxide film OX exposed at the opening of the resist RES is removed by wet etching or dry etching.

  Next, FIG. 9 will be described. A conductive electrode film such as AlSi is formed on the entire surface so as to be in contact with the surface of the Si substrate at the contact opening. Subsequently, in a lithography process for electrode processing, a resist RES is applied, exposed, and developed, and a part of the resist RES is opened. Thereafter, the electrode film exposed at the opening of the resist RES is removed by wet etching or dry etching.

  Next, FIG. 10 will be described. After removing the resist for electrode processing, a protective film PI such as a polyimide film is formed and exposed to leave the protective film PI only in the termination region.

  Next, FIG. 11 will be described. The back side of the Si wafer is ground to make the Si wafer thinner. The wafer thickness differs depending on the withstand voltage, and is, for example, about 70 μm at a 600V withstand voltage and about 140 μm at a 1200V withstand voltage. Chemical etching is performed after mechanical polishing so as not to leave a damaged layer of grinding. When the diameter is large, such as an 8-inch wafer, a wafer thicker than the wafer thickness necessary for securing the pressure resistance is required in advance so that the wafer is not easily cracked. It is preferable to use a well-known grinding method that ensures the strength of the wafer by grinding to the thickness and leaving the periphery of the wafer in the original ring shape.

Next, FIG. 12 will be described. P-type impurities of the anode p layer AP are ion-implanted into the entire surface from the back side of the Si wafer, and the impurities are activated by annealing. For the annealing for activation, laser annealing from the anode surface side is preferably used so that the cathode electrode KE and the field plate protective film PI on the opposite surface of the Si wafer are not thermally damaged. When a carbon dioxide (CO ₂ ) laser is used as the type of laser, heating can be performed without dissolving the Si surface, so that defects introduced by laser annealing can be reduced, and conduction loss of the diode can be suppressed. Further, when a YLF laser or a YAG laser is used, defects are introduced near the boundary between the anode p layer AP and the n-drift layer MN in order to melt and heat the surface of the Si wafer. Control can be performed to suppress the hole injection amount from the anode, and the switching loss of the diode can be suppressed. When the CO ₂ laser is used, the profile in the depth direction of the impurity is almost the same as that immediately after the ion implantation, and when a YLF laser or a YAG laser is used, the impurity concentration in the portion where Si is dissolved becomes substantially constant.

  After the activation annealing, the anode electrode AE is formed. Thereafter, the wafer is diced to produce a diode chip. The dicing surface of the chip side wall causes a leakage current when a defect due to dicing occurs, so that dicing is performed so as not to cause a defect as much as possible. Dicing using a dicing blade may be used, but dicing using a laser is less likely to cause defects, and leakage current can be suppressed. When dicing using a laser is performed in an oxygen atmosphere and the chip side wall is oxidized together with dicing, leakage current can be suppressed.

  In the manufacturing method described above, the cathode-side structure is formed in the steps of FIGS. 5 to 10, and then the Si wafer is ground to form a thin wafer, and the anode-side structure is formed in the steps of FIGS. 11 and 12. In the case of a diode with a withstand voltage of 600 V or 1200 V, the finished wafer thickness is thin, so it is preferable to manufacture in this order. However, with a diode with a withstand voltage of 3.3 kV or more, the finished Si wafer thickness is increased, so The structure on the cathode side may be formed after the structure is formed. In this case as well, it is possible to obtain the effect of softening the recovery characteristics and improving the resistance to recovery destruction.

  FIG. 13 shows another embodiment of the present invention, and is a sectional view of a diode including a termination region and a part of an active region. Different parts from the embodiment of FIG. 1 will be described. In the present embodiment, a p-layer region SP composed of a p-type impurity region is provided at the chip termination near the chip sidewall. The p layer region SP reduces the electric field in the vicinity of the chip side wall, and suppresses an increase in leakage current due to defects generated in the side wall due to chip dicing. In the p layer region SP, before forming the structure on the cathode main surface 20 side, a resist is applied to the Si wafer surface on the cathode main surface side by lithography, exposed, and developed to ion-implant p-type impurities, and then The p-type impurities are diffused by annealing at a high temperature for a long time. Since it is formed by diffusion from the Si wafer surface on the cathode main surface side, the p-layer region SP is located between the anode-side main surface 10 and the cathode-side main surface 20, and in this embodiment, the anode p-layer AP and the cathode The side main surface 20 is in contact with the anode side main surface 10 toward the cathode side main surface 20 and has a shape spreading in the lateral direction.

  FIG. 14 shows another embodiment of the present invention, and is a sectional view of a diode including a termination region and a part of an active region. Different parts from the embodiment of FIG. 13 will be described. In the present embodiment, a p-layer region SP composed of a p-type impurity region is formed on the chip side wall by forming a trench groove in the Si substrate and performing oblique ion implantation into the trench groove. As in the embodiment of FIG. 13, an increase in leakage current due to defects caused by chip dicing can be suppressed. In addition, this formation method can suppress the spread of the width of the p layer region SP, and can suppress an increase in the area of termination due to the formation of the p layer region SP.

  FIG. 15 shows another embodiment of the present invention, and is a sectional view of a diode including a termination region and a part of an active region. Different parts from the embodiment of FIG. 1 will be described. In this embodiment, the metal layer SE is formed on the chip side wall after dicing the wafer. When a voltage is applied during recovery, the equipotential lines do not extend toward the chip side wall, and the electric field strength at the chip side wall is reduced. The metal layer SE is made of a metal such as aluminum (Al), and is formed, for example, by spraying a liquid containing Al atoms.

  FIG. 16 shows another embodiment of the present invention, and is a sectional view of a diode including a termination region and a part of an active region. Different parts from the embodiment of FIG. 1 will be described. In the present embodiment, the buffer n layer BN including an n-type impurity region is provided between the cathode n layer KN and cathode p layer KP on the cathode side main surface 20 side and the n − drift layer NM. The n-type impurity concentration of the buffer n layer BN is set higher than the n-type impurity concentration of the n − drift layer NM and lower than the n-type impurity concentration of the cathode n layer KN. When a voltage is applied to the diode, the expansion of the depletion layer is suppressed by the buffer n layer BN, and the electric field applied to the boundary between the cathode p layer KP and the n-drift layer is reduced, thereby improving the breakdown voltage of the diode. be able to.

  FIG. 17 shows another embodiment of the present invention, and is a sectional view of a diode including a termination region and a part of an active region. Differences from the embodiment of FIG. 16 will be described. In the present embodiment, the cathode p layer KP ′ is not in contact with the cathode electrode KE, and the cathode n layer KN is in contact with the cathode electrode KE over the entire surface of the cathode-side main surface 20 in the active region. Since the cathode electrode KE and the cathode n layer KN are in contact with the entire surface of the active region, the amount of electrons injected from the cathode n layer KN during conduction increases, so that conduction loss is reduced. In the present embodiment, a buffer n layer BN is provided as in the embodiment of FIG. 16, and the cathode p layer KP ′ is located in the buffer n layer BN. This improves the breakdown voltage of the diode as in the embodiment of FIG. 16, but the process may be simplified by not forming the buffer n layer BN. Here, a buffer n layer BN is interposed between the cathode p layer KP ′ and the cathode n layer KN, and the cathode p layer KP ′ is separated from the cathode n layer KN. The cathode p layer KP ′ may be in contact with the cathode n layer KN.

  FIG. 18 shows a power conversion device using a diode embodying the present invention, which is an embodiment of the present invention. The power converter includes a three-phase inverter circuit for driving a motor. Diodes 201a to 201f are connected in reverse parallel to the IGBTs 200a to 200f. That is, the diodes 201a to 201f operate as freewheeling diodes. As these diodes, the diodes of any of the above-described embodiments are used. Two IGBTs are connected in series. Accordingly, two anti-parallel circuits of IGBTs and diodes are connected in series to form a half-bridge circuit for one phase. Half bridge circuits are provided for the number of AC phases, in this embodiment, for three phases. An AC output is generated from a series connection point of two IGBTs, that is, a series connection point of two anti-parallel circuits, and is connected to a motor 206 such as an induction machine or a synchronous machine. The collectors of the IGBTs 200a, 200b, and 200c on the upper arm side are commonly connected and connected to the DC high potential side of the rectifier circuit. The emitters of the IGBTs 200d, 200e, and 200f on the lower arm side are commonly connected and connected to the ground side of the rectifier circuit. The rectifier circuit 203 converts alternating current from the alternating current power source 202 into direct current. The IGBTs 200a to 200f perform on / off switching to convert DC power received from the rectifier circuit 203 into AC power and drive a motor such as a synchronous machine or an induction machine. Upper arm drive circuit 204 and lower arm drive circuit 205 supply drive signals to the gates of upper arms IGBTTa to IGBTc and lower arms IGBTd to IGBTf, respectively, to turn on and off IGBTs.

  Regarding the mounting of the IGBT and the diode in this power converter, conventionally, the IGBT chip and the diode chip of the same arm both have a collector electrode and a cathode electrode having no termination structure on the same conductive pattern on the insulating substrate. In the case of using a diode chip embodying the present invention, it is placed on a conductive pattern different from the IGBT chip, and the anode electrode of the diode is connected to the conductive pattern. Connect electrically. With such mounting, since the IGBT chip and the diode chip are mounted on different conductive patterns, the influence of heat generated during operation on the mutual chips can be reduced. In the case of double-sided cooling mounting, the IGBT collector electrode and the diode cathode electrode are oriented in the same direction, and the IGBT collector electrode and the diode cathode electrode are placed on the same conductive plate, and the IGBT emitter is mounted. The electrode and the anode electrode of the diode are mounted so as to be connected to another identical conductive plate.

  According to the present embodiment, since the diode according to the present invention is connected in reverse parallel to the IGBT as a freewheel diode, noise due to a jumping voltage at the time of reverse recovery and ringing of current / voltage can be reduced. Thereby, it can prevent that a power converter device fails by an overvoltage or malfunctions by noise. Furthermore, the failure of the power conversion device is prevented by improving the resistance to recovery breakdown of the diode. Therefore, the reliability of the power conversion device is improved.

  Although the embodiments of the present invention have been described in detail above, the embodiments of the present invention are not limited to those described above, and various embodiments are possible within the scope of the technical idea of the present invention. For example, the present invention may be applied to a lateral diode incorporated in a semiconductor integrated circuit or a diode incorporated in a reverse conducting semiconductor switching element. Further, instead of the IGBT in the power conversion device of FIG. 18, a semiconductor such as a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), a junction bipolar transistor, a junction FET, a static induction transistor, a GTO thyristor (Gate Turn Off Thyristor), etc. A switching element can be used. The power conversion device may be a converter such as a forward conversion device, various power supply devices, or the like in addition to the inverter device. Furthermore, even if the conductivity type of each semiconductor layer in each embodiment is reversed, that is, even if the p-type is changed to the n-type and the n-type is changed to the p-type, the operation is the same as in each embodiment.

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 10 Anode side main surface 20 Cathode side main surface 200a-200f IGBT
201a to 201f Diode 202 AC power supply 203 Rectifier circuit 204 Upper arm drive circuit 205 Lower arm drive circuit 206 Motor NM n-drift layer AP Anode p layer AE Anode electrode KN Cathode n layer KP Cathode p layer KE Cathode electrode BN Buffer n layer OX Oxide film TP termination p layer FP field plate electrode PI protective film RES resist SP p layer region SE metal layer

Claims (13)

In a diode comprising a semiconductor substrate having first and second main surfaces,
The semiconductor substrate is
A first conductivity type first semiconductor layer in contact with the first main surface;
A second semiconductor layer of a second conductivity type adjacent to the first semiconductor layer;
A third semiconductor layer of the second conductivity type in contact with the second main surface and having an impurity concentration higher than that of the second semiconductor layer;
A termination region comprising a first semiconductor layer of the first conductivity type in contact with the second main surface;
Have
A first main electrode electrically connected to the first semiconductor layer at the first main surface;
A second main electrode electrically connected to the third semiconductor layer at the second main surface;
A diode comprising:   2. The diode according to claim 1, wherein the semiconductor substrate includes a fifth semiconductor layer of the first conductivity type that is in contact with the second main surface and is adjacent to the third semiconductor layer, and the second main surface. The diode of claim 5, wherein the fifth semiconductor layer is electrically connected to the second main electrode.   3. The diode according to claim 2, wherein the semiconductor substrate includes an active region including the first semiconductor layer, the second semiconductor layer, the third semiconductor layer, and the fifth semiconductor layer, and the fifth semiconductor layer. Is located at the boundary between the active region and the termination region.   3. The diode according to claim 2, wherein the semiconductor substrate includes an active region including the first semiconductor layer, the second semiconductor layer, the third semiconductor layer, and the fifth semiconductor layer, and the fourth semiconductor layer. Is located at the boundary between the active region and the termination region. The diode according to claim 1 or claim 2,
The diode characterized by not having a local structure in which the first semiconductor layer is patterned on the first surface on the first main surface.   6. The diode according to claim 5, wherein the first semiconductor layer is in contact with the entire surface of the first main surface. The diode according to claim 1 or claim 2,
A diode comprising a field plate electrode electrically connected to the fourth semiconductor layer. The diode according to claim 1 or claim 2,
A diode having a sixth semiconductor layer of a first conductivity type in contact with an end portion of the semiconductor substrate and positioned between the first main surface and the second main surface in the termination region. The diode according to claim 1 or claim 2,
The sixth semiconductor layer extends in a lateral direction from the first main surface toward the second main surface. The diode according to claim 1 or claim 2,
A diode having a metal layer in contact with an end portion of the semiconductor substrate and positioned between the first main surface and the second main surface in the termination region.   3. The diode according to claim 2, wherein the semiconductor substrate includes the eighth semiconductor layer of the second conductivity type between the second semiconductor layer and the fifth semiconductor layer, and the eighth semiconductor layer. The diode has a higher impurity concentration than the second semiconductor layer and lower than the third semiconductor layer.   2. The diode according to claim 1, wherein the semiconductor substrate includes an eighth semiconductor layer of the second conductivity type between the second semiconductor layer and the fifth semiconductor layer, and the eighth semiconductor layer. The diode has a higher impurity concentration than the second semiconductor layer and lower than the third semiconductor layer, and the ninth semiconductor layer of the first conductivity type is provided in the eighth semiconductor layer. A first semiconductor switching element and a second semiconductor switching element connected in series, a first diode connected in antiparallel to the first semiconductor switching element, and antiparallel to the second semiconductor switching element In a power conversion device including a second diode to be connected,
The power converter according to claim 1, wherein the first and second diodes are the diodes according to claim 1.