JPH1117176A - Silicon-carbide semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To alleviate the electric field strength of the interface along an insulating film and the first conducting-type drift by providing the second trench, which is deeper than the first trench filled with a gate electrode and the second conducting type region along the second trench. SOLUTION: A gate electrode 13 of polycrystal silicon is provided at the inner side of a trench 5 through a gate insulating film 6 of a silicon oxide film. A drain electrode 11 of an Ni film is provided at the back surface of an n<+> substrate 1. From the surface of a p-base layer 3, a p<+> type region 7 is formed along a second trench 8, which is deeper than the trench 5 at the gate part, and the side surface and the bottom surface of the second trench 8. A source electrode 12 comprising Ti-Al up to the p-base layer 3 and the surface of an n<+> source region 4 from the p<+> -type region 7 is formed. Thus, the electric field strength of the interface of the gate insulating film 6 and an n<-> drift layer 2 can be alleviated by a depletion layer expanding from the pn junction to the n<-> drift layer 2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a silicon carbide semiconductor device.

[0002]

2. Description of the Related Art Since silicon carbide (hereinafter abbreviated as SiC) is a material having a large band gap and being chemically stable, various semiconductor devices that can be used even at high temperature and under radiation compared to silicon are expected. Has been studied. At most 150 ° C for conventional silicon devices
Although the degree of operation is considered to be the operation limit, in SiC, element devices such as pn junction diodes and MOSFETs (field-effect transistors having a metal-oxide-semiconductor structure) have already been prototyped, and operation has been confirmed even at a high temperature of 400 ° C. or higher. Have been. If the use at such a high temperature becomes possible, the environment such as a nuclear reactor and space is severe, and a robot or a computer in an environment that is inaccessible to humans can be used. In addition, since the temperature of a conventional silicon device rises due to heat generated due to a loss generated during operation, it is necessary to provide a cooling facility for suppressing the temperature increase. I will. With SiC, these cooling facilities can be significantly reduced in size and simplified. If a semiconductor device occupying many components can be miniaturized as described above, for example, in an automobile, fuel efficiency can be greatly improved, and a great effect can be expected for environmental conservation. Thus, SiC semiconductor devices are expected in many application fields.

A vertical MOSFET is an important device when considering application of SiC to a power semiconductor device. The reason is that the device is a voltage-driven device, so that the devices can be driven in parallel and the drive circuit can be simplified, and that the device is a unipolar device, so that high-speed switching is possible. In SiC, unlike silicon, it is difficult to diffuse a deep impurity, but epitaxial growth is relatively easy. Therefore, a trench MOSFET having a trench 5 as shown in FIG. 5 is generally used. FIG. 5 is a cross-sectional view of a principal part of a SiC trench MOSFET that has been prototyped so far. 5, lower it than the impurity concentration on the n ⁺ substrate 1 n ^- drift layer 2 and the p-type p base layer 3 on the surface layer of the SiC substrate epitaxially grown selectively high concentrations of n ⁺ source region 4 is formed, and a groove (hereinafter referred to as a trench) 5 reaching the n ⁻ drift layer 2 from the surface is formed in a part of the n ⁺ source region 4. Inside the trench 5, a gate electrode 1 is interposed via a gate insulating film 6.
3 is provided, also, the source electrode 12 in contact with the common exposed surface of the n ⁺ surface and the p base layer 3 of the source region 4,
Drain electrodes 11 are provided on the back surface of the n ⁺ substrate 1, respectively. In the case of SiC, a silicon oxide film formed by thermally oxidizing SiC can be used as the gate insulating film.

The operation of this MOSFET is such that when a positive voltage of a certain value or more is applied to the gate electrode 13 while a voltage is applied between the drain electrode 11 and the source electrode 12, the p base An inversion layer is formed on the surface layer of the layer 3, and an electron current flows from the source electrode 12 to the drain electrode 11 through the inversion layer.

[0005]

Assuming that the electric field of the insulating film is Ei and the electric field of the semiconductor is Es at the interface between the insulating film and the semiconductor, the following equation holds: εi · Ei = εs · Es. Where εs is the relative dielectric constant of the semiconductor,
εi is the relative dielectric constant of the insulating film. Therefore, Ei / Es = εs / εi. This value will be calculated for silicon and SiC.

Εs = 11.7 (silicon) εs = 10.0 (SiC), and if the insulating film is a silicon oxide film and its dielectric constant εi = 3.8 is substituted, Ei / Es = 3.1 (Silicon) Ei / Es = 2.6 (SiC). That is, in the conventional structure of FIG. 5, a much larger electric field is applied to the gate insulating film than to the semiconductor portion. FIG. 6 shows an electric field distribution at the gate portion along the line XX 'in FIG. The vertical axis is the electric field strength, and the horizontal axis is the depth. The electric field strength Ei of the insulating film is about three times larger than the electric field strength Es of the semiconductor.

Further, since the maximum electric field Esmax of the semiconductor is Esmax = 2 × 10 ⁵ V / cm (silicon) Esmax = 2 × 10 ⁶ V / cm (SiC), the maximum electric field Eimax of the insulating film is Eimax = 6 × 10 ⁵ V / cm (silicon) Eimax = 5 × 10 ⁶ V / cm (SiC) The dielectric breakdown voltage of the silicon oxide film is 8 × 10 ⁶ V
When the avalanche breakdown starts inside the semiconductor, a large electric field close to the dielectric breakdown voltage is applied to the gate insulating film in the case of SiC.

Normally, a power device is required to withstand a certain current when an avalanche current flows. However, in a conventional SiC trench MOSFET, since avalanche breakdown starts in a trench at a gate portion, the avalanche withstand capability is reduced. It is determined by the dielectric breakdown of the insulating film, and cannot utilize the high dielectric breakdown electric field strength of SiC. In view of the above problems, it is an object of the present invention to provide a SiC trench MOSFET having a large avalanche withstand voltage, which does not cause a dielectric breakdown of a gate insulating film.

[0009]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, a silicon carbide semiconductor device according to the present invention is a silicon carbide semiconductor device having a lower impurity concentration than a substrate formed sequentially on a silicon carbide semiconductor substrate of a first conductivity type. A first conductivity type drift layer, a second conductivity type base layer of silicon carbide, a first conductivity type source region formed in a part of a surface layer of the second conductivity type base layer, and a first conductivity type source A first trench reaching the first conductivity type drift layer from the surface of the region, including an electrode for applying a voltage via an insulating film in the first trench, a second trench further deeper than the trench, And a second conductivity type region along the second trench.

According to the above means, by providing the second trench deeper than the first trench filled with the gate electrode and the second conductivity type region along the second trench, the insulating film and the first trench are formed. The electric field intensity at the interface of the conductivity type drift layer can be reduced, and the avalanche resistance can be increased.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a SiC according to an embodiment of the present invention.
FIG. 3 is a sectional view of a main part of a trench MOSFET. FIG. 1 shows an active region for turning on and off a current. The MOSFET mainly has a portion that bears a withstand voltage mainly at a peripheral portion, and the portion is a portion related to the essence of the present invention. Therefore, the description is omitted. In FIG. 1, in a SiC substrate in which an n ⁻ drift layer 2 having a lower impurity concentration and a p-type p base layer 3 having a lower impurity concentration are epitaxially grown on an n ⁺ substrate 1, a high concentration is selectively formed on a surface layer of the p base layer 3. the n ⁺ source region 4 is formed, a part of the n ⁺ source region 4,
Trench 5 reaching n ⁻ drift layer 2 from the surface is formed. Inside the trench 5, a gate electrode 13 of polycrystalline silicon is interposed via a gate insulating film 6 of a silicon oxide film.
Is provided. On the back surface of the n ⁺ substrate 1, a drain electrode 11 of a Ni film is provided. This MOSF
In the ET, a second trench 8 deeper than the gate portion trench 5 from the surface of the p base layer 3 and ap ⁺ -type region 7 are formed along the side and bottom surfaces of the second trench 8. Then, from the p ⁺ type region 7, the p base layer 3,
A source electrode 12 made of Ti—Al reaching the surface of n ⁺ source region 4 is provided. The operation of the MOSFET shown in FIG. 1 is as follows. When a positive voltage of a certain value or more is applied to the gate electrode 13 in a state where a voltage is applied between the drain electrode 11 and the source electrode 12, the p base layer next to the gate electrode 13 3, an inversion layer is formed on the surface layer, and an electron current flows from the source electrode 12 to the drain electrode 11 through the inversion layer. In the MOSFET of FIG. 1, the depth of the second trench 8 is deeper than the trench 5 in the gate portion. Therefore, when a voltage is applied between the drain electrode 11 and the source electrode 12 and the voltage is increased, the depletion spreading from the pn junction formed by the p ⁺ type region 7 and the n ⁻ drift layer 2 to the n ⁻ drift layer 2 The layer reduces the electric field strength at the interface between the gate insulating film 6 and the n ⁻ drift layer 2.

FIG. 2 shows the results of simulating the electric field strength along XX 'of the conventional MOSFET shown in FIG. 5 and the MOSFET according to the present invention shown in FIG. The horizontal axis represents the distance from the bottom of the gate insulating film 6 (the distance from the upper surface in the XX ′ direction), and the vertical axis represents the electric field intensity. As can be seen from FIG. 3, the electric field strength on the n ⁻ drift layer 2 side at the interface between the gate insulating film 6 and the n ⁻ drift layer 2 is 2.0 in the conventional technique, whereas the electric field strength in the present invention is 1.2. Can be reduced. That is, the pn composed of the p ⁺ type region 7 and the n ⁻ drift layer 2
By the depletion layer extending from the junction to the n ⁻ drift layer 2,
Since the electric field strength at the interface between the gate insulating film 6 and the n ⁻ drift layer 2 is reduced, avalanche breakdown does not occur at the corners of the trench 5 in the gate portion, and the gate insulating film 6 is not broken. That is, a MOSFET having a large avalanche withstand capability can be obtained without causing a gate insulating film to undergo dielectric breakdown when a voltage is applied.

FIGS. 3A to 3D are cross-sectional views of respective steps for explaining a method of manufacturing the trench MOSFET of the embodiment of FIG. An n ⁻ drift layer 2 having a lower impurity concentration and a p-type p base layer 3 are formed on the n ⁺ substrate 1 by epitaxial growth (FIG. 3A). Next, high-concentration nitrogen ions are selectively implanted into the surface layer of p base layer 3 to form n ⁺ source region 4. Next, a trench 5 at a gate portion is formed by patterning a photoresist and performing plasma etching using a mixed gas of fluorine and oxygen. Next, a gate insulating film 6 is formed in the trench 5 at the gate portion by thermal oxidation, and polycrystalline silicon is filled by a low pressure CVD method to form a gate electrode 13 (FIG. 3B). Next, a second trench 8 is formed by patterning a photoresist and performing plasma etching using a mixed gas of fluorine and oxygen. Next, boron ions are implanted at a high concentration to form p ⁺ -type regions 7 and heat treatment is performed to recover defects. It is important that the depth of the second trench 8 is greater than the depth of the trench 5 in the gate portion (FIG. 3C). Finally, Ni is deposited to form a drain electrode 11 and Ti-Al is deposited to form a source electrode 12 (FIG. 3D).

FIG. 4 is a sectional view of another embodiment of the present invention. The point that the second trench 8 is deeper than the trench 5 in the gate portion from the surface of the p base layer 3 and that the p ⁺ type region 7 is formed along the bottom and side surfaces of the second trench 8 is the same as FIG. It is. However, this MOSFET is different in that there are a plurality of trenches 5 between the p ⁺ -type region 7 and another adjacent p ⁺ -type region 7. At the time of forward conduction, p ⁺ type region 7
In this case, a dead space in which no current flows increases, and the on-voltage increases. However, the structure as shown in FIG. 4 can reduce the area occupied by the p ⁺ -type region 7 and reduce the on-voltage.

FIG. 7 is a cross-sectional view of another embodiment in which the effect of relaxing the electric field is further improved with respect to FIG. In FIG. 7, in the SiC substrate on which the n ⁻ drift layer 2 and the p-type p base layer 3 having lower impurity concentrations are epitaxially grown on the n ⁺ substrate 1, the surface layer of the p base layer 3 is selectively highly doped. The n ⁺ source region 4 is formed, and a trench 5 reaching the n ⁻ drift layer 2 from the surface is formed in a part of the n ⁺ source region 4. A gate electrode 13 made of polycrystalline silicon is provided inside the trench 5 via a gate insulating film 6 made of a silicon oxide film. A drain electrode 1 made of a Ni film is formed on the back surface of the n ⁺ substrate 1.
1 is provided. A second trench 8 deeper than the gate portion trench 5 is formed from the surface of the p base layer 3, and ap ⁺ type region 7 is provided along the side and bottom surfaces of the second trench 8. Then, the Ti − layer reaching the surface of p base layer 3 and n ⁺ source region 4 from p ⁺ type region 7.
A source electrode 12 made of Al is provided. A feature of FIG. 7 is that the position of the p ⁺ -type region 7 which is most widened in the lateral direction is an inverted tapered type which is located inside the substrate surface. When a voltage is applied between the drain electrode 11 and the source electrode 12 and the voltage is increased, the p ⁺ -type region 7
And n ^- from the pn junction consisting of the drift layer 2, n ^- depletion layer that spreads in the drift layer 2 becomes wider toward the interior than the substrate surface. Therefore, by adopting the structure as shown in FIG. 7, p ⁺
A depletion layer extending in the direction of n ⁻ drift layer 2 from another p ⁺ -type region 7 adjacent to n-type region 7 has a lower source,
Since the contact is made with the voltage between the drains, the gate insulating film 6 and n ⁻
The effect of relaxing the electric field at the interface of the drift layer 2 is great.

FIG. 8 is a sectional view of another embodiment of the present invention. In FIG. 8, in the SiC substrate on which the n ⁻ drift layer 2 and the p-type p base layer 3 having lower impurity concentrations are epitaxially grown on the n ⁺ substrate 1, the surface layer of the p base layer 3 is selectively made to have a high concentration. N ⁺ source region 4
Is formed, and a trench 5 reaching the n ⁻ drift layer 2 from the surface is formed in a part of the n ⁺ source region 4. A gate electrode 13 made of polycrystalline silicon is provided inside the trench 5 via a gate insulating film 6 made of a silicon oxide film. On the back surface of the n ⁺ substrate 1, a drain electrode 11 of a Ni film is provided. In this MOSFET, a second trench 8 deeper than the trench 5 in the gate portion from the surface of the p base layer 3 and ap ⁺ type region 7 are formed so as to intersect with the trench 5. A source electrode 12 made of Ti-Al is provided from the p ⁺ type region 7 to the surface of the p base layer 3 and the n ⁺ source region 4. Also in the structure of FIG. 8, when a voltage is applied between the drain electrode 11 and the source electrode 12 and the voltage is increased,
The depletion layer extending from the pn junction composed of the p ⁺ type region 7 and the n ⁻ drift layer 2 to the n ⁻ drift layer 2 reduces the electric field strength at the interface between the gate insulating film 6 and the n ⁻ drift layer 2. Therefore, the avalanche withstand capability of the MOSFET is SiC
Of the gate insulating film 6
Will not be destroyed. That is, a MOSFET having a large avalanche withstand capability can be obtained without causing a gate insulating film to undergo dielectric breakdown when a voltage is applied.

FIG. 9 shows an example of a main circuit of a power inverter device using a MOSFET as a switching element according to the present invention. The MOSFET according to the present invention is applied to a portion surrounded by a broken line in the drawing, that is, an anti-parallel circuit portion of the MOSFET and the diode. This inverter device has a pair of DC terminals 121 and 12
2, and three AC terminals 131 to
133, a DC power supply is connected to the DC terminal,
By switching 1 to 106, DC power is converted into AC power and output to an AC terminal. Between the DC terminals
A set of MOSFETs 101 and 102, 103 and 1 connected in series
04, 105 and 106 are connected at both ends. Each MOSFET
An AC terminal is taken out from the series connection point of the two MOSFETs in the set.

If the SiC MOSFET according to the present invention is used,
MOSFETs with much lower loss than silicon can be achieved, module loss can be reduced, and the efficiency of the inverter device improves. Further, when the diode is a Schottky diode of SiC, both the switching device and the diode are unipolar. Therefore, the speed of the inverter device can be further increased.

FIG. 10 is a sectional view of an embodiment of a trench type insulated gate bipolar transistor (hereinafter referred to as IGBT) according to the present invention. Referring to FIG. 10, in a SiC substrate in which n ⁻ drift layer 2 and p-type p base layer 3 are epitaxially grown on p ⁺ substrate 9, a high concentration n ⁺ source region 4 is selectively formed on the surface layer of p base layer 3. Is formed, and a part of the n ⁺ source region 4 is n ⁻ from the surface.
A trench 5 reaching the drift layer 2 is formed. Inside the trench 5, a gate insulating film 6 of a silicon oxide film is formed.
, A gate electrode 13 of polycrystalline silicon is provided. Also, a Ti-Al collector electrode 14 is provided on the back surface of the p ⁺ substrate 9. In the IGBT, a second trench 8 deeper than the gate portion trench 5 from the surface of the p base layer 3 and ap ⁺ type region 7 are formed along the side and bottom surfaces of the second trench 8. Then, p base layer 3 from the p ⁺ -type region 7, n ⁺
An emitter electrode 15 made of Ti-Al reaching the surface of the source region 4 is provided. The operation of the IGBT of FIG. 10 is as follows. When a positive voltage of a certain value or more is applied to the gate electrode 13 with a voltage applied between the collector electrode 14 and the emitter electrode 15, the p base layer 3, an inversion layer is formed on the surface layer, and an electron current is injected from the emitter electrode 15 to the p base layer 3 through the inversion layer. This electron current is applied to p base layer 3, n ⁻ drift layer 2,
The current becomes the base current of the bipolar transistor composed of the p ⁺ substrate 9, and the IGBT operates. I in FIG.
In the GBT, when a voltage is applied between the collector electrode 14 and the emitter electrode 15 and the voltage is increased, the p ⁺ -type region 7
And n ^- from the pn junction consisting of the drift layer 2, n ^- the depletion layer that spreads in the drift layer 2, a gate insulating film 6 n ^-
The electric field strength at the interface of the drift layer 2 is reduced. Therefore, the avalanche withstand capability of the IGBT is determined by the dielectric breakdown electric field strength of SiC, and the gate insulating film 6 does not break. In other words, an IGB having a large avalanche withstand voltage does not cause breakdown of the gate insulating film when a voltage is applied.
T.

In general, it is difficult for SiC to form a p-type region having a low resistivity. This is aluminum,
This is because the impurity activation rate of impurities is extremely low because the impurity level of a p-type impurity such as boron is as deep as 200 meV to 300 meV. Therefore, the SiC IGBT has a drawback that it is easy to latch up. However, with the structure shown in FIG. 10, a current flows through the p ⁺ -type region 7, so that latch-up hardly occurs.

FIG. 11 shows an example of a main circuit of a power inverter device using an IGBT as a switching element according to the present invention. The IGBT of the present invention is applied to a portion surrounded by a broken line in the drawing, that is, an antiparallel circuit portion of the IGBT and the diode. This inverter device has a pair of DC terminals 121 and 1
22, and three AC terminals 131 to
133, DC power supply is connected to DC terminal, IGBT141
By switching 〜146, DC power is converted to AC power and output to the AC terminal. Between the DC terminals
Both ends of the series-connected IGBT sets 101 and 102, 103 and 104, and 105 and 106 are connected. Each IG
An AC terminal is taken out from a series connection point of two IGBTs in the set of BTs.

By using the SiC IGBT of the present invention, an IGBT having a much lower loss than silicon can be realized, the module loss can be reduced, and the efficiency of the inverter device can be improved.

[0023]

As described above, according to the SiC semiconductor device of the present invention, by providing the second trench deeper than the gate portion and the p-type region along the second trench, the p-type The electric field intensity applied to the gate insulating film is reduced by the depletion layer extending from the region. Therefore, a SiC trench MOSFET having a large avalanche resistance can be obtained without dielectric breakdown of the gate insulating film.

[Brief description of the drawings]

FIG. 1 is a sectional structural view of a trench MOSFET according to an embodiment of the present invention.

FIG. 2 is an electric field intensity distribution along XX ′ of the trench MOSFET of FIGS. 1 and 5;

FIG. 3 is a sectional view illustrating a method of manufacturing the trench MOSFET of FIG. 1 in a manufacturing process order.

FIG. 4 is a cross-sectional view of a trench MOSFET in which a plurality of trench gates are provided between second trenches.

FIG. 5 is a sectional structural view of a conventional trench MOSFET.

6 is an electric field intensity distribution along XX 'of the trench MOSFET of FIG.

FIG. 7 is a sectional structural view of a trench MOSFET in which the effect of electric field relaxation is enhanced.

FIG. 8 is a sectional structural view of a trench MOSFET in which a p-type region is arranged to intersect a trench gate.

FIG. 9 is an embodiment of a main circuit of a power inverter device to which the trench MOSFET of the present invention is applied.

FIG. 10 is a sectional view of a trench IGBT according to an embodiment of the present invention.

FIG. 11 is an embodiment of a main circuit of a power inverter device to which the trench IGBT of the present invention is applied.

[Explanation of symbols]

1 ... n ⁺ substrate, 2 ... n ^- drift layer, 3 ... p
Base layer, 4 ... n ⁺ source region, 5 ... trench, 6 ... gate insulating film, 7 ... p ⁺ type region, 8 ... second trench, 9
... p ⁺ substrate, 11 ... drain electrode, 12 ... source electrode, 13 ... gate electrode, 14 ... collector electrode, 1
5 ... Emitter electrode, 101-106 ... MOSFET, 111-
116: diode, 121, 122: DC terminal, 13
1 to 133 ... AC terminals, 141 to 146 ... IGBTs.

Claims (5)

[Claims] A first conductivity type silicon carbide semiconductor substrate;
A first conductivity type drift layer and a second conductivity type base layer formed in order, a first conductivity type source region formed on the second conductivity type base layer, and a first conductive type source region from the surface of the first conductivity type source region. A first trench that reaches the mold drift layer, a gate electrode is provided in the first trench via an insulating film, and a second trench that is deeper than the first trench is provided. A silicon carbide semiconductor device comprising a second conductivity type region along an inner surface. 2. The silicon carbide semiconductor device according to claim 1, wherein at least two first trenches are provided between the second trench and another adjacent second trench. 3. The silicon carbide semiconductor device according to claim 1, wherein the position of the second trench deeper than the first trench in the lateral direction is located inside the substrate surface. 4. The silicon carbide semiconductor device according to claim 1, wherein the first trench and the second trench deeper than the first trench intersect. 5. The method according to claim 5, wherein the second conductivity type silicon carbide semiconductor substrate is
A first conductivity type drift layer and a second conductivity type base layer formed in order, a first conductivity type source region formed on the second conductivity type base layer, and a first conductive type source region from the surface of the first conductivity type source region. A first trench reaching the mold drift layer, a gate electrode provided in the trench via an insulating film, a second trench deeper than the first trench, and an inner surface of the second trench extending along the inner surface of the second trench. And a second conductivity type region.