JP2002319676A - Semiconductor device, manufacturing method and control method - Google Patents
Semiconductor device, manufacturing method and control methodInfo
- Publication number
- JP2002319676A JP2002319676A JP2001159178A JP2001159178A JP2002319676A JP 2002319676 A JP2002319676 A JP 2002319676A JP 2001159178 A JP2001159178 A JP 2001159178A JP 2001159178 A JP2001159178 A JP 2001159178A JP 2002319676 A JP2002319676 A JP 2002319676A
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- conductivity type
- semiconductor substrate
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- collector
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Abstract
Description
【０００１】[0001]
【発明の属する技術分野】この発明は、電力変換装置な
どに用いられる逆阻止型ＩＧＢＴなどの半導体装置とそ
の製造方法およびその制御方法に関する。ここでＩＧＢ
Ｔは絶縁ゲート型バイポーラトランジスタのことであ
る。[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor device such as a reverse blocking IGBT used for a power converter or the like, a method of manufacturing the same, and a method of controlling the same. Where IGB
T is an insulated gate bipolar transistor.
【０００２】[0002]
【従来の技術】図１３で示されるプレーナゲート型ＮＰ
Ｔ（ノンパンチスルー）−ＩＧＢＴは、ｎ形ＦＺ（フロ
ーティングゾーン）ウェハにｐベース領域５２、チャネ
ルストッパーであるｐ+ 領域６０、ゲート酸化膜５６、
ゲート電極５４、ｎ+ エミッタ領域５３およびエミッタ
電極５８等の表面構造を形成した後に、裏面を所定の厚
さに削り、１μｍ程度の厚さのｐ+ コレクタ領域５５お
よびコレクタ電極５９を形成して製造される。裏面のｐ
+ コレクタ領域５５を形成するためのｐ形不純物の活性
化処理温度は、表面に形成済みのアルミニウムのエミッ
タ電極５８が溶融しないように低温度で行う必要があ
る。また各耐圧クラスに応じて図示しない適切なエッジ
ターミネーション構造（端部耐圧構造）が外周部に付加
される。ここでは、１セル（ｐベース領域５２）のみを
図示してあるが、通常は複数のセル構造が存在する。2. Description of the Related Art A planar gate type NP shown in FIG.
T (non-punch through) -IGBT is obtained by forming a p base region 52, a p + region 60 serving as a channel stopper, a gate oxide film 56 on an n-type FZ (floating zone) wafer,
After forming the surface structures such as the gate electrode 54, the n + emitter region 53 and the emitter electrode 58, the back surface is cut to a predetermined thickness, and the p + collector region 55 and the collector electrode 59 having a thickness of about 1 μm are formed. Manufactured. P on the back
The activation treatment temperature of the p-type impurity for forming + collector region 55 must be performed at a low temperature so that aluminum emitter electrode 58 formed on the surface does not melt. In addition, an appropriate edge termination structure (end withstand voltage structure) (not shown) is added to the outer peripheral portion according to each withstand voltage class. Here, only one cell (p base region 52) is shown, but usually there are a plurality of cell structures.
【０００３】コレクタ電極５９に正電圧を印加した状態
で、ゲート電極に正電圧を印加すると、ＩＧＢＴ表面に
チャネルが形成されてｎ- ドリフト領域５１中を電子電
流が流れる。電子がｐ+ コレクタ領域５５に到達すると
ホールがドリフト領域に注入され、ｐ+ ドリフト領域５
５は高注入状態となり、伝導度変調を起こして、抵抗が
激減する。このため低オン電圧が実現される。When a positive voltage is applied to the gate electrode while a positive voltage is applied to the collector electrode 59, a channel is formed on the IGBT surface, and an electron current flows through the n - drift region 51. When the electrons reach the p + collector region 55, holes are injected into the drift region, and the p + drift region 5
5 has a high injection state, causing conductivity modulation, and the resistance is drastically reduced. Therefore, a low on-voltage is realized.
【０００４】コレクタ電極５９に正電圧を印加（順バイ
アス）し、ゲート電極５４に電圧を印加しない状態で
は、空乏領域がｐベース領域５２とｎ- ドリフト領域５
１のｐｎ接合からｎ- ドリフト領域５１側に伸びる。ま
た、空乏層の終端はシリコン表面に形成される耐圧構造
部となるために、順方向電圧を確実に阻止できる。一
方、コレクタ電極５９に負電圧を印加（逆バイアス）す
ると、空乏領域がｐ + コレクタ領域５５とｎ- ドリフト
領域５１のｐｎ接合から伸びるが、このｐｎ接合は、シ
リコンの側面に露出しており、空乏領域はむき出しのシ
リコン側面に沿って形成されるために、発生電流（もれ
電流）が極めて大きくなり、逆耐圧が低下する。またシ
リコン側面（デバイス側面）はパッシベーション処理し
ていないために、長期間デバイスを使用すると逆方向耐
圧が変化するといった信頼性上の問題が存在する。従っ
て図１３のような、従来のＩＧＢＴでは十分な逆方向耐
圧が保証できない。つぎに、この逆方向耐圧を保証する
従来の逆阻止型ＩＧＢＴについて説明する。A positive voltage is applied to the collector electrode 59 (forward bias).
In the state where no voltage is applied to the gate electrode 54.
Is that the depletion region is p base region 52 and n-Drift area 5
1 pn junction to n-It extends to the drift region 51 side. Ma
The depletion layer ends at the silicon surface withstand voltage structure
As a part, the forward voltage can be reliably blocked. one
On the other hand, a negative voltage is applied to the collector electrode 59 (reverse bias).
Then, the depletion region becomes p +Collector region 55 and n-Drift
The pn junction extends from the pn junction in the region 51.
Exposed on the side of the recon, the depletion area is exposed
The current generated (leakage)
Current) becomes extremely large, and the reverse breakdown voltage decreases. Also
The recon side (device side) is passivated
The device will not withstand reverse
There are reliability issues such as pressure changes. Follow
In the conventional IGBT as shown in FIG.
Pressure cannot be guaranteed. Next, this reverse breakdown voltage is guaranteed.
A conventional reverse blocking IGBT will be described.
【０００５】図１４で示されるプレーナゲート構造の逆
阻止型ＩＧＢＴは、エピタキシャル成長基板（エピタキ
シャルウエハ）を用いて製作されたものである。数百μ
ｍの厚みを有する高濃度ｐ形基板６５上にｎ- エピタキ
シャル領域６１ａを成長させ、活性領域を囲むように選
択的に深いｐ+ 領域８５（分離拡散領域：側面のｐ+コ
レクタ領域となる）を形成し、ｐベース領域６２、ゲー
ト酸化膜６６、ゲート電極６４、ｎ+ エミッタ領域６３
およびエミッタ電極６８等の表面構造を形成し、電子線
等のライフタイムキラーを導入して製造される。デバイ
ス側面が高濃度のｐ+ 領域８５と基板６５（裏面のｐ+
コレクタ領域となる）で囲まれているので、逆電圧を印
加した際にも空乏領域がデバイス側面に現れることはな
いため、十分な逆耐圧を得ることが可能となる。The reverse blocking IGBT having a planar gate structure shown in FIG. 14 is manufactured using an epitaxial growth substrate (epitaxial wafer). Several hundred μ
An n - epitaxial region 61a is grown on a high-concentration p-type substrate 65 having a thickness of m, and ap + region 85 selectively deep so as to surround an active region (isolation diffusion region: becomes a p + collector region on a side surface) Are formed, and a p base region 62, a gate oxide film 66, a gate electrode 64, an n + emitter region 63
And a surface structure such as the emitter electrode 68 and the like, and a lifetime killer such as an electron beam is introduced. The device side surface has a high concentration of p + region 85 and substrate 65 (p +
(Becomes a collector region), so that a depletion region does not appear on the side of the device even when a reverse voltage is applied, so that a sufficient reverse breakdown voltage can be obtained.
【０００６】この逆阻止形ＩＧＢＴを図１５のように逆
並列に接続すると、双方向の電流を制御でき、双方向の
印加電圧にも耐えられる、双方向デバイスとして機能す
る。尚、図中、Ｔ１、Ｔ２は主端子、Ｇ１、Ｇ２はゲー
ト端子、Ｅ１、Ｅ２はエミッタ端子である。双方向デバ
イスを交流−交流変換器に応用すると、直接変換が可能
になり、従来のコンバータ＋コンデンサ＋インバータで
構成される変換回路と比べて装置のサイズが縮小化さ
れ、コストダウンが可能になる。また双方向デバイスを
構成する逆阻止型ＩＧＢＴは、ＩＧＢＴとしての機能は
勿論のこと、正のゲート電圧を印加しているときは、後
述するようにダイオード（還流ダイオード）としての機
能も有する。When this reverse blocking IGBT is connected in anti-parallel as shown in FIG. 15, it functions as a bidirectional device that can control bidirectional current and withstand bidirectional applied voltage. In the figure, T1 and T2 are main terminals, G1 and G2 are gate terminals, and E1 and E2 are emitter terminals. When a bidirectional device is applied to an AC-AC converter, direct conversion becomes possible, and the size of the device can be reduced and cost can be reduced as compared with a conversion circuit composed of a conventional converter + capacitor + inverter. . The reverse blocking IGBT constituting the bidirectional device has not only a function as an IGBT but also a function as a diode (return diode) as described later when a positive gate voltage is applied.
【０００７】図１６に示されるプレーナゲート構造の逆
阻止型ＩＧＢＴは、ＦＺ基板（ＦＺウエハ）を用いて製
作されたものである。ｎ形ＦＺウェハの表面および裏面
から深いｐ+ 領域９５（分離拡散領域：側面のｐ+ コレ
クタ領域となる）を形成し、同時に裏面から深いｐ+ 領
域を拡散形成し裏面のｐ+ コレクタ領域７５とし、その
後表面にｐベース領域７２、ゲート酸化膜７６、ゲート
電極７４、ｎ+ エミッタ領域７３およびエミッタ電極７
８等の表面構造を形成する。この素子に、電子線等のラ
イフタイムキラーを導入しても、十分な逆方向耐圧を確
保できる。A reverse blocking IGBT having a planar gate structure shown in FIG. 16 is manufactured using an FZ substrate (FZ wafer). A deep p + region 95 (separated diffusion region: side p + collector region) is formed from the front and back surfaces of the n-type FZ wafer, and at the same time, a deep p + region is diffused from the back surface to form a p + collector region 75 on the back surface. Then, the p base region 72, the gate oxide film 76, the gate electrode 74, the n + emitter region 73 and the emitter electrode 7
A surface structure such as 8 is formed. Even if a lifetime killer such as an electron beam is introduced into this element, a sufficient reverse breakdown voltage can be ensured.
【０００８】これらの逆阻止型ＩＧＢＴにおいて、エピ
タキシャルウエハを用いて裏面のｐ + コレクタ領域６５
を形成する場合も、ＦＺウエハを用いて裏面のｐ+ コレ
クタ領域７５を熱拡散で形成する場合も、裏面のｐ+ コ
レクタ領域６５、７５の厚みは数十μｍから数百μｍと
なる。このように裏面のｐ+ コレクタ領域６５、７５が
厚くなると、オン電流を流したとき、裏面のコレクタ領
域内での電圧降下が大きくなるため、この電圧降下を低
く抑えるために、裏面のｐ+ コレクタ領域６５、７５の
不純物ピーク濃度を１０18ｃｍ-3を超える濃度にして、
裏面のｐ+ コレクタ領域６５、７５内での電圧降下を極
力小さくする必要がある。In these reverse blocking IGBTs, epi-
P on the back side using a TAXIAL wafer +Collector area 65
Is also formed using the FZ wafer,+this
When the collector region 75 is formed by thermal diffusion, p+Ko
The thickness of the rectifier regions 65 and 75 ranges from several tens of μm to several hundred μm.
Become. Thus, p on the back+Collector regions 65 and 75
When the on current flows, the thickness of the collector
Since the voltage drop in the region increases, this voltage drop
P on the back side+Of the collector regions 65 and 75
Impurity peak concentration of 1018cm-3To a concentration exceeding
P on the back+The voltage drop in the collector regions 65 and 75
It is necessary to reduce the force.
【０００９】[0009]
【発明が解決しようとする課題】しかし、裏面のｐ+ コ
レクタ領域６５、７５の不純物濃度が高くなると、ｎ-
ドリフト領域６１、７１への正孔のキャリア注入量が多
くなり、この正孔を中和するように電子密度も増加す
る。この電子密度は、図１７の実線Ａで示すように、裏
面のｐ+ コレクタ領域６５、７５とｎ- ドリフト領域６
１、７１のｐｎ接合付近のｎ- ドリフト領域で大きくな
り、この箇所に過剰キャリアが蓄積する。これはダイオ
ード動作時（ＦＷＤ動作時）のアノード側（ＩＧＢＴの
コレクタ側）偏重のキャリア分布となることを意味す
る。このようなアノード側（コレクタ側）偏重のキャリ
ア分布をしていると、ＩＧＢＴ動作時のターンオフ時に
は、空乏領域は表面ｐｎ接合から伸びて蓄積キャリアを
掃き出していくので、コレクタ側のキャリアは空乏領域
が十分伸びた段階、すなわち高電圧が印加された状態で
掃き出される。従ってコレクタ側の蓄積キャリアはエミ
ッタ側のキャリアと比べてより大きなターンオフ損失を
発生する。このためコレクタ側偏重のキャリア分布を有
する従来の逆阻止型ＩＧＢＴは、ターンオフ損失が大き
い。However, when the impurity concentration of the p + collector regions 65 and 75 on the back surface is increased, n −
The carrier injection amount of holes into the drift regions 61 and 71 increases, and the electron density also increases so as to neutralize the holes. This electron density is, as shown by the solid line A in FIG. 17, the p + collector regions 65 and 75 on the back surface and the n − drift region 6.
It increases in the n − drift region near the pn junction of 1, 71, and excess carriers accumulate at this position. This means that the carrier distribution is biased toward the anode side (the collector side of the IGBT) during the diode operation (FWD operation). If the carrier distribution is biased toward the anode side (collector side), the depletion region extends from the surface pn junction and sweeps out the accumulated carriers at the time of turn-off during the IGBT operation. Are swept out at the stage when the voltage has sufficiently extended, that is, in a state where a high voltage is applied. Therefore, the accumulated carriers on the collector side generate a larger turn-off loss than the carriers on the emitter side. For this reason, the conventional reverse blocking IGBT having the collector-side biased carrier distribution has a large turn-off loss.
【００１０】また、ダイオード動作時の逆回復過程で
は、アノード側（ＩＧＢＴのコレクタ側）から伸びる空
乏領域によって蓄積過剰キャリアが掃き出されるため、
アノード側のキャリア量が多いと逆回復ピーク電流が大
きくなり、ハードリカバリーになる。つまり、この逆阻
止型ＩＧＢＴは、ゲート電極に正電圧を印加し続ける
と、印加している期間は、ｐ+ コレクタ領域６５、７５
がアノードで、ｎ+ エミッタ領域６３、７３がカソード
のダイオード（還流ダイオード）として働く。前記のよ
うに、ｎ- ドリフト領域６１、７１のコレクタ領域側に
過剰キャリアが蓄積していると、このダイオードの逆回
復動作で、大きな逆回復電流が流れる。In the reverse recovery process during the diode operation, excess accumulated carriers are swept out by a depletion region extending from the anode side (IGBT collector side).
When the amount of carriers on the anode side is large, the reverse recovery peak current becomes large and hard recovery is performed. In other words, in the reverse blocking IGBT, if a positive voltage is continuously applied to the gate electrode, the p + collector regions 65, 75
Denotes an anode, and the n + emitter regions 63 and 73 function as cathode diodes (reflux diodes). As described above, when excess carriers are accumulated on the collector region side of n − drift regions 61 and 71, a large reverse recovery current flows by the reverse recovery operation of the diode.
【００１１】この逆回復電流の大きさは、前記したよう
に、ｎ- ドリフト領域６１、７１のコレクタ側での過剰
キャリアの蓄積量が大きい程大きく、また、逆回復電流
が大きい程、ハードリカバリー波形になる傾向が強い。
逆回復電流の波形がハードリカバリーとなると、飛躍逆
電圧が高くなり、この飛躍逆電圧が高く成りすぎると、
素子の逆電圧定格を超えてしまい、素子を破壊する。As described above, the magnitude of the reverse recovery current increases as the accumulated amount of excess carriers on the collector side of n − drift regions 61 and 71 increases, and as the reverse recovery current increases, the hard recovery current increases. Strong tendency to form a waveform.
If the waveform of the reverse recovery current becomes hard recovery, the jump reverse voltage will increase, and if this jump reverse voltage becomes too high,
Exceeding the reverse voltage rating of the device will destroy the device.
【００１２】また、図１５のように、この逆阻止型ＩＧ
ＢＴを２個逆並列に接続して、双方向ＩＧＢＴとした場
合、アバランシェ電圧以上のサージ電圧が印加されたと
き、アバランシェ電圧が低い逆阻止型ＩＧＢＴにアバラ
ンシェ電流が流れる。通常の逆阻止型ＩＧＢＴのアバラ
ンシェ電圧は、順方向と逆方向でほぼ等しく製造され
る。Also, as shown in FIG.
When two BTs are connected in antiparallel to form a bidirectional IGBT, when a surge voltage higher than the avalanche voltage is applied, an avalanche current flows through the reverse blocking IGBT having a low avalanche voltage. The avalanche voltage of a normal reverse blocking IGBT is manufactured substantially equal in the forward direction and the reverse direction.
【００１３】しかし、この双方向ＩＧＢＴを構成する２
個の逆阻止型ＩＧＢＴの順方向および逆方向のアバラン
シェ電圧が、製造ばらつきによって、第１のＩＧＢＴ
（ゲート端子Ｇ１、エミッタ端子Ｅ１）の順方向のアバ
ランシェ電圧より、第２のＩＧＢＴ（ゲート端子Ｇ２、
エミッタ端子Ｅ２）の逆方向のアバランシェ電圧が多少
低く、また、第１のＩＧＢＴの逆方向のアバランシェ電
圧が、第２のＩＧＢＴの順方向のアバランシェ電圧より
多少高くなることがある。その場合には、主端子Ｔ１に
正電圧のサージ電圧が印加されたとき、第２のＩＧＢＴ
に順方向のアバランシェ電流が流れる。また、主端子Ｔ
２に正電圧のサージ電圧が印加されたとき、やはり第２
のＩＧＢＴに逆方向のアバランシェ電流が流れる。However, 2 which constitutes this bidirectional IGBT
The avalanche voltages of the reverse blocking IGBTs in the forward and reverse directions may be changed by the first IGBT due to manufacturing variations.
From the forward avalanche voltage of (gate terminal G1, emitter terminal E1), the second IGBT (gate terminal G2,
The reverse avalanche voltage of the emitter terminal E2) may be slightly lower, and the reverse avalanche voltage of the first IGBT may be slightly higher than the forward avalanche voltage of the second IGBT. In that case, when a positive surge voltage is applied to the main terminal T1, the second IGBT
Avalanche current flows in the forward direction. The main terminal T
When a positive surge voltage is applied to the second
Avalanche current flows through the IGBT of the same direction.
【００１４】そのため、順方向、逆方向いずれのサージ
電圧に対しても、第２のＩＧＢＴにのみサージ電流が流
れて、第２のＩＧＢＴの発生損失が増大し、素子が破壊
することもあり、双方向ＩＧＢＴとしてのサージ耐量が
低下する。また、前記第１のＩＧＢＴまたは第２のＩＧ
ＢＴが逆バイアスされると、空乏層中で電子および正孔
の対が発生する。発生した正孔はコレクタ電極に流れ込
み、電子はエミッタ電極に向かって流れ、ｐベース領域
に流れ込む。この電子電流は、ＩＧＢＴの寄生バイポー
ラトランジスタ（ｐベース領域がエミッタ、ｎ- ドリフ
ト領域がベース、ｐコレクタ領域がコレクタであるｐｎ
ｐトランジスタ）のベース電流となるために、正孔がｐ
ベース領域からｎ- ドリフト領域に向かって注入されて
コレクタ電極に流れ込み、非常に大きな逆方向漏れ電流
となる。For this reason, a surge current flows only in the second IGBT with respect to a surge voltage in either the forward direction or the reverse direction, so that the generation loss of the second IGBT increases and the element may be destroyed. The surge withstand capability of the bidirectional IGBT is reduced. Further, the first IGBT or the second IGBT
When the BT is reverse-biased, electron and hole pairs are generated in the depletion layer. The generated holes flow into the collector electrode, the electrons flow toward the emitter electrode, and flow into the p base region. This electron current is generated by a parasitic bipolar transistor of the IGBT (pn which has an emitter in the p base region, a base in the n − drift region, and a collector in the p collector region).
holes become p
It is injected from the base region toward the n − drift region and flows into the collector electrode, resulting in a very large reverse leakage current.
【００１５】この発明の目的は、前記の課題を解決し
て、サージ耐量が高い双方向ＩＧＢＴを製作できて、Ｉ
ＧＢＴ動作時およびダイオード順動作時のオン電圧が低
く、また、ダイオード逆動作時の逆回復電流が小さく、
ソフトリカバリー特性となる半導体装置とその製造方法
および漏れ電流を小さくできる制御方法を提供すること
にある。SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and to manufacture a bidirectional IGBT having a high surge withstand capability.
The ON voltage during the GBT operation and the diode forward operation is low, and the reverse recovery current during the diode reverse operation is small.
An object of the present invention is to provide a semiconductor device having soft recovery characteristics, a method of manufacturing the same, and a control method capable of reducing leakage current.
【００１６】[0016]
【課題を解決するための手段】前記の目的を達成するた
めに、 （１）第１導電形半導体基板の第１主面の表面層に選択
的に形成される第２導電形ベース領域と、該ベース領域
の表面層に選択的に形成される第１導電形エミッタ領域
と、前記半導体基板と前記エミッタ領域に挟まれた前記
ベース領域上にゲート絶縁膜を介して形成されるゲート
電極と、前記半導体基板の第２主面の表面層に形成され
る第２導電形コレクタ領域と、前記エミッタ領域上と前
記ベース領域上に選択的に形成されるエミッタ電極と、
前記コレクタ領域上に形成されるコレクタ電極とを有す
る半導体装置において、前記第１導電形半導体基板と前
記コレクタ領域との境界に形成されるｐｎ接合の逆方向
のアバランシェ電圧を、前記第１導電形半導体基板と前
記第２導電形ベース領域との境界に形成されるｐｎ接合
の順方向のアバランシェ電圧より、高くなる構成とす
る。 （２）第１導電形半導体基板の第１主面の表面層に選択
的に形成される第２導電形ベース領域と、該ベース領域
の表面層に選択的に形成される第１導電形エミッタ領域
と、前記半導体基板と前記エミッタ領域に挟まれた前記
ベース領域上にゲート絶縁膜を介して形成されるゲート
電極と、前記ベース領域を取り囲むように、前記半導体
基板の第２主面および前記半導体基板の第１主面から第
２主面に亘って形成される第２導電形コレクタ領域と、
前記エミッタ領域上と前記ベース領域上に選択的に形成
されるエミッタ電極と、前記コレクタ領域上に形成され
るコレクタ電極とを有する半導体装置において、前記第
１導電形半導体基板と、前記第２主面側に形成される前
記コレクタ領域との境界に形成されるｐｎ接合の逆方向
のアバランシェ電圧を、前記第１導電形半導体基板、前
記第２導電形ベース領域との境界に形成されるｐｎ接合
の順方向のアバランシェ電圧より、高くなる構成とす
る。 （３）第１導電形半導体基板の第１主面の表面層に選択
的に形成される第２導電形ベース領域と、該ベース領域
の表面から前記ベース層を貫通し、前記半導体基板内に
到達するように形成されたトレンチ溝と、該トレンチ溝
にゲート絶縁膜を介して形成されるゲート電極と、前記
ベース領域の表面層に、前記トレンチ溝と接して、選択
的に形成される第１導電形エミッタ領域と、前記ベース
領域を取り囲むように、前記半導体基板の第２主面およ
び前記半導体基板の第１主面から第２主面に亘って形成
される第２導電形コレクタ領域とを有する半導体装置に
おいて、前記第１導電形半導体基板と、前記第２主面側
に形成される前記コレクタ領域との境界に形成されるｐ
ｎ接合の逆方向のアバランシェ電圧を、前記第１導電形
半導体基板、前記第２導電形ベース領域との境界に形成
されるｐｎ接合の順方向のアバランシェ電圧より、高く
なる構成とする。 （４）第１導電形半導体基板の第１主面の表面層に選択
的に形成される第２導電形ベース領域と、該ベース領域
の表面層に選択的に形成される第１導電形エミッタ領域
と、前記半導体基板と前記エミッタ領域に挟まれた前記
ベース領域上にゲート絶縁膜を介して形成されるゲート
電極と、前記ベース領域を取り囲むように、前記半導体
基板の第２主面および前記半導体基板の第１主面から第
２主面に亘って形成される第２導電形コレクタ領域と、
前記エミッタ領域上と前記ベース領域上に選択的に形成
されるエミッタ電極と、前記コレクタ領域上に形成され
るコレクタ電極とを有する半導体装置において、前記ベ
ース領域下の前記半導体基板の第２主面側に形成され、
前記半導体基板のコレクタ電極との間に位置する前記コ
レクタ領域の厚みが、０．１μｍないし１０μｍである
構成とする。 （５）第１導電形半導体基板の第１主面の表面層に選択
的に形成される第２導電形ベース領域と、該ベース領域
の表面から前記ベース層を貫通し、前記半導体基板内に
到達するように形成されたトレンチ溝と、該トレンチ溝
にゲート絶縁膜を介して形成されるゲート電極と、前記
ベース領域の表面層に、前記トレンチ溝と接して、選択
的に形成される第１導電形エミッタ領域と、前記ベース
領域を取り囲むように、前記半導体基板の第２主面およ
び前記半導体基板の第１主面から第２主面に亘って形成
される第２導電形コレクタ領域と、前記エミッタ領域上
と前記ベース領域上に選択的に形成されるエミッタ電極
と、前記コレクタ領域上に形成されるコレクタ電極とを
有する半導体装置において、前記ベース領域下の前記半
導体基板の第２主面側に形成され、前記半導体基板のコ
レクタ電極との間に位置する前記コレクタ領域の厚み
が、０．１μｍないし１０μｍである構成とする。 （６）第１導電形半導体基板の第１主面の表面層に選択
的に第２導電形ベース領域を形成し、該ベース領域の表
面層に選択的に第１導電形エミッタ領域を形成し、前記
半導体基板と前記エミッタ領域に挟まれた前記ベース領
域上にゲート絶縁膜を介してゲート電極を形成し、前記
ベース領域を取り囲むように、前記半導体基板の第２主
面および前記半導体基板の第１主面から第２主面に亘っ
て形成される第２導電形コレクタ領域と、前記エミッタ
領域上と前記ベース領域上に選択的に形成されるエミッ
タ電極と、前記コレクタ領域上に形成されるコレクタ電
極とを有する半導体装置において、前記ベース領域の側
面を取り囲むコレクタ領域となる第２導電形の第１領域
を、前記ベース領域より深い深さで半導体基板の第１主
面側から形成する工程と、該半導体基板の第２主面側
を、前記第１領域が露出する深さに削除する工程と、該
第１領域が露出した第２主面の表面層に０．１μｍない
し１０μｍの深さで、前記第１領域に接して、前記第２
主面側のコレクタ領域となる第２導電形の第２領域を形
成する工程とを含む製造方法とする。 （７）第１導電形半導体基板の第１主面の表面層に選択
的に第２導電形ベース領域を形成し、該ベース領域の表
面から該ベース領域を貫通し、前記半導体基板内に到達
するトレンチ溝を形成し、該トレンチ溝にゲート絶縁膜
を介してゲート電極を形成し、前記ベース領域の表面層
に前記トレンチ溝と接して、第１導電形エミッタ領域を
選択的に形成し、前記ベース領域を取り囲むように、前
記半導体基板に形成された第２導電形コレクタ領域を有
する半導体装置において、前記ベース領域の側面を取り
囲むコレクタ領域となる第２導電形の第１領域を、前記
ベース領域より深い深さで半導体基板の第１主面側から
形成する工程と、該半導体基板の第２主面側を、前記第
１領域が露出する深さに削除する工程と、該第１領域が
露出した第２主面の表面層に０．１μｍないし１０μｍ
の深さで、前記第１領域に接して、前記第２主面側のコ
レクタ領域となる第２導電形の第２領域を形成する工程
とを含む製造方法とする。 （８） （６）項および（７）項のコレクタ領域が、第
２導電形不純物をイオン注入し、３００℃ないし５００
℃で熱処理されて形成されるとよい。 （９） （６）項および（７）項のコレクタが、第２導
電形不純物をイオン注入し、レーザーアニール処理で形
成されるとよい。 （１０） （６）項から（９）項のコレクタ領域の活性
化した第２導電形不純物のピーク濃度が、５×１０16ｃ
ｍ-3以上で、１×１０18ｃｍ-3以下であるとよい。 （１１）（６）項および（７）項の第１主面側に形成さ
れた前記エミッタ領域表面から、前記第２主面側に形成
された前記コレクタ領域表面までの距離が５０μｍない
し２００μｍであることよい。 （１２）第１導電形半導体基板の第１主面の表面層に選
択的に形成され る第２導電形ベース領域と、該ベース
領域の表面層に選択的に形成される第１導電形エミッタ
領域と、前記半導体基板と前記エミッタ領域に挟まれた
前記ベース領域上にゲート絶縁膜を介して形成されるゲ
ート電極と、前記半導体基板の第２主面の表面層に形成
される第２導電形コレクタ領域と、前記エミッタ領域上
と前記ベース領域上に選択的に形成されるエミッタ電極
と、前記コレクタ領域上に形成されるコレクタ電極とを
有し、前記第１導電形半導体基板と前記コレクタ領域と
の境界に形成されるｐｎ接合と、前記第１導電形半導体
基板と前記第２導電形ベース領域との境界に形成される
ｐｎ接合とが、前記第１導電形半導体基板の側面に露出
するベベル構造を有する半導体装置において、前記第１
導電形半導体基板と前記コレクタ領域との境界に形成さ
れるｐｎ接合の逆方向のアバランシェ電圧を、前記第１
導電形半導体基板と前記第２導電形ベース領域との境界
に形成されるｐｎ接合の順方向のアバランシェ電圧よ
り、高くなる構成とする。 （１３）第１導電形半導体基板の第１主面の表面層に選
択的に形成される第２導電形ベース領域と、該ベース領
域の表面層に選択的に形成される第１導電形エミッタ領
域と、前記半導体基板と前記エミッタ領域に挟まれた前
記ベース領域上にゲート絶縁膜を介して形成されるゲー
ト電極と、前記半導体基板の第２主面の表面層に形成さ
れる第２導電形コレクタ領域と、前記エミッタ領域上と
前記ベース領域上に選択的に形成されるエミッタ電極
と、前記コレクタ領域上に形成されるコレクタ電極とを
有し、前記第１導電形半導体基板と前記コレクタ領域と
の境界に形成されるｐｎ接合と、前記第１導電形半導体
基板と前記第２導電形ベース領域との境界に形成される
ｐｎ接合とが、前記第１導電形半導体基板の側面に露出
するベベル構造を有する半導体装置において、前記半導
体基板の第２主面側に形成され、前記半導体基板とコレ
クタ電極との間に位置する前記コレクタ領域の厚みが、
０．１μｍないし１０μｍである構成とする。 （１４） （４）項、（５）項および（１３）項のコレ
クタ領域の厚みが０．１μｍないし２μｍであるとさら
によい。In order to achieve the above object, (1) a second conductivity type base region selectively formed in a surface layer of a first main surface of a first conductivity type semiconductor substrate; A first conductivity type emitter region selectively formed on a surface layer of the base region; a gate electrode formed on the base region between the semiconductor substrate and the emitter region via a gate insulating film; A second conductivity type collector region formed on a surface layer of a second main surface of the semiconductor substrate; an emitter electrode selectively formed on the emitter region and the base region;
In a semiconductor device having a collector electrode formed on the collector region, an avalanche voltage in a reverse direction of a pn junction formed at a boundary between the semiconductor substrate of the first conductivity type and the collector region is set to the first conductivity type. It is configured to be higher than the forward avalanche voltage of the pn junction formed at the boundary between the semiconductor substrate and the second conductivity type base region. (2) A second conductivity type base region selectively formed on the surface layer of the first main surface of the first conductivity type semiconductor substrate, and a first conductivity type emitter selectively formed on the surface layer of the base region. A region, a gate electrode formed on the base region interposed between the semiconductor substrate and the emitter region via a gate insulating film, and a second main surface of the semiconductor substrate and the second surface so as to surround the base region. A second conductivity type collector region formed from the first main surface to the second main surface of the semiconductor substrate;
In a semiconductor device having an emitter electrode selectively formed on the emitter region and the base region, and a collector electrode formed on the collector region, the semiconductor device may further include a first conductive type semiconductor substrate; The avalanche voltage in the opposite direction of the pn junction formed at the boundary with the collector region formed on the surface side is changed to the pn junction formed at the boundary between the first conductivity type semiconductor substrate and the second conductivity type base region. Above the avalanche voltage in the forward direction. (3) a second conductivity type base region selectively formed on the surface layer of the first main surface of the first conductivity type semiconductor substrate, and penetrating through the base layer from the surface of the base region, and into the semiconductor substrate. A trench groove formed so as to reach, a gate electrode formed in the trench groove via a gate insulating film, and a second electrode selectively formed in a surface layer of the base region in contact with the trench groove. A first conductivity type emitter region; a second conductivity type collector region formed from the first main surface to the second main surface of the semiconductor substrate so as to surround the base region; In the semiconductor device having the first conductivity type semiconductor substrate and the collector region formed on the second main surface side.
The avalanche voltage in the reverse direction of the n-junction is higher than the avalanche voltage in the forward direction of the pn junction formed at the boundary between the first conductivity type semiconductor substrate and the second conductivity type base region. (4) A second conductivity type base region selectively formed on the surface layer of the first main surface of the first conductivity type semiconductor substrate, and a first conductivity type emitter selectively formed on the surface layer of the base region. A region, a gate electrode formed on the base region interposed between the semiconductor substrate and the emitter region via a gate insulating film, and a second main surface of the semiconductor substrate and the second surface so as to surround the base region. A second conductivity type collector region formed from the first main surface to the second main surface of the semiconductor substrate;
In a semiconductor device having an emitter electrode selectively formed on the emitter region and the base region, and a collector electrode formed on the collector region, a second main surface of the semiconductor substrate below the base region Formed on the side,
The collector region located between the semiconductor substrate and the collector electrode has a thickness of 0.1 μm to 10 μm. (5) A second conductivity type base region selectively formed on a surface layer of the first main surface of the first conductivity type semiconductor substrate, and penetrating through the base layer from a surface of the base region and into the semiconductor substrate. A trench groove formed so as to reach, a gate electrode formed in the trench groove via a gate insulating film, and a second electrode selectively formed in a surface layer of the base region in contact with the trench groove. A first conductivity type emitter region; a second conductivity type collector region formed from the first main surface to the second main surface of the semiconductor substrate so as to surround the base region; A semiconductor device having an emitter electrode selectively formed on the emitter region and the base region, and a collector electrode formed on the collector region, wherein a second main electrode of the semiconductor substrate below the base region is provided. Formed on the side, the thickness of the collector region located between the collector electrode of said semiconductor substrate, a configuration to not 0.1μm is 10 [mu] m. (6) A second conductivity type base region is selectively formed on a surface layer of a first main surface of a first conductivity type semiconductor substrate, and a first conductivity type emitter region is selectively formed on a surface layer of the base region. Forming a gate electrode on the base region interposed between the semiconductor substrate and the emitter region with a gate insulating film interposed therebetween, and enclosing the second main surface of the semiconductor substrate and the semiconductor substrate so as to surround the base region; A second conductivity type collector region formed from the first main surface to the second main surface, an emitter electrode selectively formed on the emitter region and the base region, and formed on the collector region And a collector region surrounding the side surface of the base region, a first region of the second conductivity type, which is a collector region surrounding the side surface of the base region, is formed from the first main surface side of the semiconductor substrate at a depth deeper than the base region. Removing the second main surface side of the semiconductor substrate to a depth at which the first region is exposed; and forming a surface layer of 0.1 μm to 10 μm on the surface layer of the second main surface at which the first region is exposed. The second region in contact with the first region at a depth;
Forming a second region of the second conductivity type to be a collector region on the main surface side. (7) A second conductivity type base region is selectively formed on a surface layer of a first main surface of the first conductivity type semiconductor substrate, penetrates the base region from a surface of the base region, and reaches the inside of the semiconductor substrate. Forming a trench groove, forming a gate electrode in the trench groove via a gate insulating film, contacting the trench groove in a surface layer of the base region, selectively forming a first conductivity type emitter region; In a semiconductor device having a collector region of a second conductivity type formed on the semiconductor substrate so as to surround the base region, a first region of a second conductivity type serving as a collector region surrounding a side surface of the base region may be formed by using the base material. Forming the semiconductor substrate at a depth deeper than the region from the first main surface side, removing the second main surface side of the semiconductor substrate to a depth at which the first region is exposed, Exposed second main surface It does not 0.1μm on the surface layer 10μm
Forming a second region of the second conductivity type that is to be in contact with the first region at a depth of the second conductive surface and that is to be the collector region on the second main surface side. (8) The collector region of (6) and (7) is ion-implanted with a second conductivity type impurity,
It may be formed by heat treatment at a temperature of ° C. (9) It is preferable that the collectors of (6) and (7) are formed by ion-implanting impurities of the second conductivity type and by laser annealing. (10) The peak concentration of the activated second conductivity type impurity in the collector region according to the above items (6) to (9) is 5 × 10 16 c
It is preferably not less than m −3 and not more than 1 × 10 18 cm −3 . (11) The distance from the surface of the emitter region formed on the first main surface side of the items (6) and (7) to the surface of the collector region formed on the second main surface side is 50 μm to 200 μm. Good to be. (12) A second conductivity type base region selectively formed on the surface layer of the first main surface of the first conductivity type semiconductor substrate, and a first conductivity type emitter selectively formed on the surface layer of the base region. A region, a gate electrode formed on the base region between the semiconductor substrate and the emitter region via a gate insulating film, and a second conductive layer formed on a surface layer of a second main surface of the semiconductor substrate. A collector electrode, a collector electrode formed selectively on the emitter region and the base region, and a collector electrode formed on the collector region. A pn junction formed at a boundary with a region and a pn junction formed at a boundary between the first conductivity type semiconductor substrate and the second conductivity type base region are exposed on side surfaces of the first conductivity type semiconductor substrate. Bevel structure Semiconductor device, wherein the first
An avalanche voltage in a reverse direction of a pn junction formed at a boundary between the conductivity type semiconductor substrate and the collector region,
It is configured to be higher than the forward avalanche voltage of the pn junction formed at the boundary between the conductivity type semiconductor substrate and the second conductivity type base region. (13) A second conductivity type base region selectively formed on the surface layer of the first main surface of the first conductivity type semiconductor substrate, and a first conductivity type emitter selectively formed on the surface layer of the base region. A region, a gate electrode formed on the base region between the semiconductor substrate and the emitter region via a gate insulating film, and a second conductive layer formed on a surface layer of a second main surface of the semiconductor substrate. A collector electrode, a collector electrode formed selectively on the emitter region and the base region, and a collector electrode formed on the collector region. A pn junction formed at a boundary with a region and a pn junction formed at a boundary between the first conductivity type semiconductor substrate and the second conductivity type base region are exposed on side surfaces of the first conductivity type semiconductor substrate. Bevel structure That in the semiconductor device, is formed on the second main surface side of the semiconductor substrate, the thickness of the collector region located between the semiconductor substrate and the collector electrode,
The structure is 0.1 μm to 10 μm. (14) It is more preferable that the thickness of the collector region in the items (4), (5) and (13) is 0.1 μm to 2 μm.
【００１７】前記のように、裏面に形成されたコレクタ
領域が、従来の逆阻止型ＩＧＢＴのコレクタ領域に対し
て厚みを薄くすることで、低濃度にしても、オン電圧の
上昇は抑制される。また、定常オン状態におけるエミッ
タ注入効率が低いため、ＩＧＢＴ動作時においてコレク
タ側のキャリア濃度が制限されて、キャリア分布が改善
されてターンオフ損失が低減される。また、ダイオード
動作時においても、アノード側のキャリア濃度が制限さ
れ、逆回復ピーク電流が低減されるのでソフトリカバリ
ー特性が得られる。As described above, the collector region formed on the back surface is made thinner than the collector region of the conventional reverse blocking IGBT, so that even if the concentration is low, the rise of the ON voltage is suppressed. . Further, since the emitter injection efficiency in the steady ON state is low, the carrier concentration on the collector side is limited during the IGBT operation, so that the carrier distribution is improved and the turn-off loss is reduced. Also during the diode operation, the carrier concentration on the anode side is limited, and the reverse recovery peak current is reduced, so that soft recovery characteristics can be obtained.
【００１８】また、従来型構造と同様に、デバイス側面
が高濃度ｐ+ 領域で囲まれているので、逆電圧を印加し
た際にも空乏領域がデバイス側面に現れることはなく、
順方向のアバランシェ電圧より、逆方向のアバランシェ
電圧を高くすることができる。また、コレクタ領域と半
導体基板との境界のｐｎ接合を側面に露出させ、ベベル
構造とし、そのベベル角を所定の値にすることで、順方
向のアバランシェ電圧より、逆方向のアバランシェ電圧
を高くすることができる。Since the side surface of the device is surrounded by the high-concentration p + region as in the conventional structure, a depletion region does not appear on the side surface of the device even when a reverse voltage is applied.
The reverse avalanche voltage can be higher than the forward avalanche voltage. Further, the pn junction at the boundary between the collector region and the semiconductor substrate is exposed on the side surface to form a bevel structure, and the bevel angle is set to a predetermined value, so that the avalanche voltage in the reverse direction is higher than the avalanche voltage in the forward direction. be able to.
【００１９】また、コレクタ領域を形成する温度を低温
度で行うことで、表面に形成済みのエミッタ電極が溶融
しないようにできる。 （１５） （１）項ないし（５）項および（１２）項な
いし（１４）項のいずれかに記載の半導体装置の制御方
法において、前記エミッタ電極の電位に対して前記コレ
クタ電極の電位が低電位にある期間、前記エミッタ電極
に対して前記ゲート電極が、しきい値電圧以上の正電圧
を印加され、前記第２導電型ベース領域の表面層に第１
導電型のチャネルを形成するような制御方法とする。Further, by performing the formation of the collector region at a low temperature, the emitter electrode formed on the surface can be prevented from melting. (15) In the method for controlling a semiconductor device according to any one of the above modes (1) to (5) and (12) to (14), the potential of the collector electrode is lower than the potential of the emitter electrode. During the period when the potential is at a potential, the gate electrode is applied with a positive voltage equal to or higher than a threshold voltage with respect to the emitter electrode, and a first voltage is applied to the surface layer of the second conductivity type base region.
The control method is such that a conductive channel is formed.
【００２０】（１６） 逆阻止型ＩＧＢＴ半導体装置に
おいて、エミッタ電極の電位に対して、コレクタ電極の
電位が低電位にある期間、前記エミッタ電極に対してゲ
ート電極がしきい値電圧以上の正電圧を印加するような
制御方法とする。(16) In the reverse blocking IGBT semiconductor device, while the potential of the collector electrode is lower than the potential of the emitter electrode, the gate electrode has a positive voltage higher than the threshold voltage with respect to the emitter electrode. Is applied.
【００２１】[0021]
【発明の実施の形態】図１はこの発明の第１実施例の半
導体装置の要部断面図である。半導体基板１００の表面
層にｐベース領域２を形成し、このｐベース領域２の表
面層にｎ+ エミッタ領域３を形成する。この半導体基板
１００の外周部と裏面側に、ｐベース領域２を取り囲む
ようにｐ+ コレクタ領域５（側面に形成されるｐ+ 領域
１５と裏面のｐ+ コレクタ領域５ａ）が形成される。裏
面のｐ+ コレクタ領域５ａの厚さは１μｍ程度である。
半導体基板で前記ｐベース領域２とｐ+ コレクタ領域５
が形成されない箇所がｎ- ドリフト領域１である。この
ｎ- ドリフト領域１とｎ + エミッタ領域３に挟まれたｐ
ベース領域２上にゲート酸化膜６を介してゲート電極４
が形成される。層間絶縁膜７でゲート電極と絶縁されて
エミッタ電極８が形成され、ｐ+ コレクタ領域５上にコ
レクタ電極９が形成される。尚、ｐ+ コレクタ領域５に
取り囲まれる領域には、前記ｐベース領域２が複数個形
成され、それぞれのｐベース領域２内にｎ+ エミッタ領
域３が形成されるが、図１では、模式的に１個のｐベー
ス領域２を示した。つぎに、図１の半導体装置の具体的
な製造方法について説明する。FIG. 1 shows a half of a first embodiment of the present invention.
It is principal part sectional drawing of a conductor apparatus. Surface of semiconductor substrate 100
A p base region 2 is formed in the layer, and a table of the p base region 2 is formed.
N for face layer+An emitter region 3 is formed. This semiconductor substrate
100 surrounding the p base region 2 on the outer peripheral portion and the back surface side
Like p+Collector region 5 (p formed on the side surface)+region
15 and p on the back+A collector region 5a) is formed. back
Surface p+The thickness of the collector region 5a is about 1 μm.
In the semiconductor substrate, the p base region 2 and p+Collector area 5
Where n is not formed is n-This is the drift region 1. this
n-Drift region 1 and n +P sandwiched between emitter regions 3
A gate electrode 4 is formed on the base region 2 via a gate oxide film 6.
Is formed. Insulated from the gate electrode by the interlayer insulating film 7
An emitter electrode 8 is formed, and p+The collector area 5
Lector electrode 9 is formed. Note that p+In the collector area 5
In the region to be surrounded, a plurality of p base regions 2 are formed.
N in each p base region 2+Emitter area
An area 3 is formed, but in FIG.
Area 2 is shown. Next, a specific example of the semiconductor device of FIG.
A simple manufacturing method will be described.
【００２２】図２から図８は、この発明の第２実施例の
半導体装置の製造方法であり、工程順に示した要部製造
工程断面図である。この半導体装置は６００Ｖ耐圧の逆
阻止型ＩＧＢＴの例である。厚さ５２５μｍの不純物濃
度１．５×１０14ｃｍ-3のＦＺウェハ１０１の表面に、
厚さ１．６μｍの初期酸化膜１１を形成し、後工程でｐ
ベース領域２が形成される箇所の周辺部に幅１００μｍ
の開口部１２を選択的にエッチングして形成する（図
２）。FIGS. 2 to 8 show a method of manufacturing a semiconductor device according to a second embodiment of the present invention, and are cross-sectional views of the main part manufacturing steps shown in the order of steps. This semiconductor device is an example of a 600 V reverse blocking IGBT. On the surface of the FZ wafer 101 having a thickness of 525 μm and an impurity concentration of 1.5 × 10 14 cm −3 ,
An initial oxide film 11 having a thickness of 1.6 μm is formed.
A width of 100 μm around the portion where the base region 2 is formed
Is selectively formed by etching (FIG. 2).
【００２３】つぎに、表面にボロンソースを塗布して熱
処理することで、ボロンのデポジションを行うい、ボロ
ンデポジション領域１３を形成する（図３）。つぎに、
ボロンガラスエッチングを行い酸化膜中のボロンを除去
した後、１２００℃以上の温度において酸素雰囲気中で
深さ１２０μｍまでボロンを拡散し、ｐ+ コレクタ領域
５の一部となるｐ+ 領域１５を形成する。このとき、酸
化膜１４も形成される（図４）。Next, a boron source is applied to the surface and heat-treated to form a boron deposition region 13 for boron deposition (FIG. 3). Next,
After removing boron in the oxide film by performing boron glass etching, boron is diffused to a depth of 120 μm in an oxygen atmosphere at a temperature of 1200 ° C. or more to form ap + region 15 which becomes a part of the p + collector region 5. I do. At this time, an oxide film 14 is also formed (FIG. 4).
【００２４】つぎに、ｐベース領域２、ゲート酸化膜
６、ゲート電極４、ｎ+ エミッタ領域３、およびエミッ
タ電極８等を通常のプレーナゲート型ＩＧＢＴと同様の
方法で形成する（図５）。高速化を図るために、ライフ
タイムキラーとして電子線照射やヘリウム照射を行うこ
ともある。つぎに、裏面を削り、ＦＺウェハ１０１の厚
さを１００μｍ程度（ＩＧＢＴの耐圧が１２００Ｖ程度
の場合は１８０μｍ程度）にし、削り面１６にはｐ領域
１５を露出させる（図６）。Next, the p base region 2, the gate oxide film 6, the gate electrode 4, the n + emitter region 3, the emitter electrode 8 and the like are formed by the same method as that of a normal planar gate IGBT (FIG. 5). In order to increase the speed, electron beam irradiation or helium irradiation may be performed as a lifetime killer. Next, the back surface is shaved to make the thickness of the FZ wafer 101 about 100 μm (about 180 μm when the breakdown voltage of the IGBT is about 1200 V), and the p region 15 is exposed on the shaved face 16 (FIG. 6).
【００２５】つぎに、裏面に、ドーズ量１×１０13ｃｍ
-2のボロンをイオン注入して３５０℃程度で１時間程度
の低温アニールを行い、活性化したボロンのピーク濃度
が１×１０17ｃｍ-3程度で、厚みが１μｍ程度の裏面の
ｐ+ コレクタ領域５ａを形成する。この裏面のｐ+ コレ
クタ領域５ａと前記のｐ+ 領域１５を合わせてｐ+ コレ
クタ領域５となる（図７）。Next, on the back surface, a dose of 1 × 10 13 cm
-2 boron is ion-implanted, and low-temperature annealing is performed at about 350 ° C. for about 1 hour, and the activated p + collector has a peak concentration of about 1 × 10 17 cm -3 and a thickness of about 1 μm on the back surface. The region 5a is formed. The p + collector region 5a on the back surface and the p + region 15 are combined to form the p + collector region 5 (FIG. 7).
【００２６】つぎに、コレクタ電極９を形成して、ＦＺ
ウエハ１０１を点線で示した切断箇所１７で切断し（図
８）、図１のような逆阻止型ＩＧＢＴが製造される。上
記方法で製造されたＩＧＢＴの順方向のアバランシェ電
圧が７００Ｖ前後、逆方向のアバランシェ電圧が８００
Ｖ前後となった。この逆阻止形ＩＧＢＴは、裏面のｐ+
コレクタ領域５ａの不純物濃度が低く、注入効率が低減
されているので、ＩＧＢＴ動作時においてはコレクタ側
のキャリア濃度が制限されて、キャリア分布が前記の図
１７の点線Ｂで示すように改善され、ターンオフ損失が
低減される。同じオン電圧２．１Ｖの場合、従来の逆阻
止型ＩＧＢＴのターンオフ損失は３．８３ｍＪであった
が、本発明の逆阻止型ＩＧＢＴのターンオフ損失は２．
９６ｍＪであった。Next, a collector electrode 9 is formed, and FZ
The wafer 101 is cut at a cutting point 17 indicated by a dotted line (FIG. 8), and a reverse blocking IGBT as shown in FIG. 1 is manufactured. The forward avalanche voltage of the IGBT manufactured by the above method is around 700 V, and the reverse avalanche voltage is 800
V. This reverse blocking IGBT has p +
Since the impurity concentration of the collector region 5a is low and the injection efficiency is reduced, the carrier concentration on the collector side is limited during the IGBT operation, and the carrier distribution is improved as shown by the dotted line B in FIG. Turn-off loss is reduced. At the same ON voltage of 2.1 V, the turn-off loss of the conventional reverse blocking IGBT was 3.83 mJ, whereas the turn-off loss of the reverse blocking IGBT of the present invention was 2.
It was 96 mJ.
【００２７】また、ダイオード動作時にはアノード側の
キャリア濃度が制限され、逆回復ピーク電流が低減さ
れ、ソフトリカバリー特性が得られる。また、図１の半
導体基板１００の側面が高濃度ｐ+ 領域１５（側面のｐ
+ コレクタ領域）で囲まれており、全てのｐｎ接合が半
導体基板１００の表面で終端している構造である。その
ため、逆電圧を印加した際にも空乏領域が半導体基板１
００の側面に現れることはなく、十分な逆耐圧を得るこ
とができる。Further, during the diode operation, the carrier concentration on the anode side is limited, the reverse recovery peak current is reduced, and the soft recovery characteristic is obtained. Further, p side of the semiconductor substrate 100 of FIG. 1 is a high concentration p + region 15 (the side surface
+ Collector region), and all pn junctions are terminated at the surface of the semiconductor substrate 100. Therefore, even when a reverse voltage is applied, the depletion region remains in the semiconductor substrate 1.
Thus, a sufficient reverse withstand voltage can be obtained.
【００２８】尚、前記のアニール温度が３００℃未満で
は、不純物イオンの活性化率が低下し、所望のピーク濃
度が得られない。一方、５００℃を超えるとエミッタ電
極材料であるＡｌ−Ｓｉ合金中のシリコンがエミッタ電
極８とｎ+ エミッタ領域３の界面に析出して、ｎ+ エミ
ッタ領域３とエミッタ電極８とのコンタクト抵抗が増大
するために、アニール温度は３００℃以上で、５００℃
以下が望ましい。If the annealing temperature is lower than 300 ° C., the activation rate of impurity ions decreases, and a desired peak concentration cannot be obtained. On the other hand, silicon Al-Si alloy is an emitter electrode material exceeds 500 ° C. is precipitated at the interface between the emitter electrode 8 and the n + emitter region 3, the contact resistance between the n + emitter region 3 and the emitter electrode 8 To increase, the annealing temperature should be above 300 ° C and 500 ° C
The following is desirable.
【００２９】また、前記の裏面のｐ+ コレクタ領域５ａ
のピーク濃度が５×１０16ｃｍ-3未満では、注入効率が
低下して、オン電圧が上昇する。また、逆電圧印加時に
ｐ+コレクタ領域５ａが完全に空乏化して逆耐圧が低下
する。一方、１×１０18ｃｍ -3を超えると逆回復電流が
増大するので、ピーク濃度は５×１０16ｃｍ-3以上で１
×１０18ｃｍ-3以下が望ましい。Further, p+Collector region 5a
Of 5 × 1016cm-3Below, the injection efficiency is
It decreases and the on-voltage increases. Also, when reverse voltage is applied
p+Collector region 5a is completely depleted and reverse breakdown voltage is reduced
I do. On the other hand, 1 × 1018cm -3Beyond which the reverse recovery current
The peak concentration is 5 × 1016cm-31
× 1018cm-3The following is desirable.
【００３０】また、裏面のｐ+ コレクタ領域５ａの厚さ
が０．１μｍ未満では、空乏層がコレクタ電極９に達し
やすくなり、順方向のアバランシェ耐圧が逆方向のアバ
ランシェ耐圧以下になる。一方、１０μｍを超えると、
ｐ+ コレクタ領域５ａからの正孔の注入が大きくなり、
逆回復電流が大きくなる。そのため、逆方向のアバラン
ヘ電圧を順方向のアバランシェ電圧より高くするために
は、コレクタ領域５ａの厚みは０．１μｍ以上で、１０
μｍ以下とする。こうすることで、逆方向のアバランシ
ェ電圧を順方向のアバランシェ電圧より１０％から２０
％程度高くできる。この高くする割合は、製造ばらつき
より大きい。この逆阻止型ＩＧＢＴを用いて図１５の双
方向ＩＧＢＴを製作すると、順、逆方向のサージ電圧が
印加されたとき、片方の逆阻止型ＩＧＢＴにのみサージ
電流が流れることがないために、サージ耐量を向上させ
ることができる。If the thickness of the p + collector region 5a on the rear surface is less than 0.1 μm, the depletion layer easily reaches the collector electrode 9, and the forward avalanche breakdown voltage is lower than the reverse avalanche breakdown voltage. On the other hand, if it exceeds 10 μm,
Injection of holes from p + collector region 5a increases,
The reverse recovery current increases. Therefore, in order to make the reverse avalanche voltage higher than the forward avalanche voltage, the thickness of the collector region 5a should be 0.1 μm or more and 10 μm or more.
μm or less. By doing so, the reverse avalanche voltage is reduced by 10% to 20% from the forward avalanche voltage.
%. This increase rate is larger than the manufacturing variation. When the bidirectional IGBT of FIG. 15 is manufactured using this reverse blocking IGBT, when a forward or reverse surge voltage is applied, a surge current does not flow through only one of the reverse blocking IGBTs. The withstand capacity can be improved.
【００３１】また、２μｍを超えるとボロンイオン注入
時の必要エネルギーが１ＭｅＶを超えて特殊なイオン注
入装置が必要となり、また、逆回復電流をさらに小さく
抑えるためには、ｐ+ コレクタ領域５ａの厚みは２μｍ
以下が望ましい。また、この発明が有効なのは、シリコ
ン厚は５０μｍ以上で２００μｍ以下である。シリコン
厚が５０μｍ未満では、薄すぎてハンドリング（ウエハ
の取扱いでウエハが割れるおそれあり）が困難となり、
２００μｍを超えると、表面からのｐ+ 領域１５の形成
に長時間かかり、製造コストが上昇するため、前記の範
囲が有効となる。If the thickness exceeds 2 μm, the energy required for boron ion implantation exceeds 1 MeV, and a special ion implantation apparatus is required. In order to further suppress the reverse recovery current, the thickness of the p + collector region 5a must be reduced. Is 2 μm
The following is desirable. The present invention is effective when the silicon thickness is 50 μm or more and 200 μm or less. If the silicon thickness is less than 50 μm, it is too thin to handle (wafer may be broken during handling),
When the thickness exceeds 200 μm, it takes a long time to form the p + region 15 from the surface, and the manufacturing cost increases. Therefore, the above range is effective.
【００３２】また、裏面ボロンイオン注入後に、エネル
ギーが５００ｍＪから３Ｊのエキシマレーザーをパルス
的に照射してコレクタ領域を活性化することもできる。
このエネルギーが５００ｍＪ未満では、ボロン等の不純
物が必要量活性化しない。一方、３Ｊを超えるとエミッ
タ電極を形成している金属が溶融する恐れがある。前記
したように、ＩＧＢＴの厚みを１００μｍ程度とし、裏
面のｐ+ コレクタ領域５ａの厚みとピーク濃度を所定の
値にすることで、ＩＧＢＴ動作時およびダイオード順動
作時のオン電圧が低く、また、ダイオード逆動作時の逆
回復電流が小さく、ソフトリカバリー特性とすることが
できる。After the back boron ion implantation, the collector region may be activated by irradiating an excimer laser having an energy of 500 mJ to 3 J in a pulsed manner.
If this energy is less than 500 mJ, the required amount of impurities such as boron is not activated. On the other hand, if it exceeds 3J, the metal forming the emitter electrode may be melted. As described above, by setting the thickness of the IGBT to about 100 μm and setting the thickness and the peak concentration of the p + collector region 5a on the back surface to predetermined values, the on-state voltage during the IGBT operation and the diode forward operation is low, and The reverse recovery current at the time of diode reverse operation is small, and soft recovery characteristics can be obtained.
【００３３】図９はダイオード動作時の逆回復電流・電
圧波形で、同図（ａ）は電流波形、同図（ｂ）は電圧波
形である。従来品は図１６で示す逆阻止型ＩＧＢＴで、
本発明品は図１で示す逆阻止型ＩＧＢＴである。本発明
品の方が逆回復電流が小さく、ソフトリカバリー波形と
なっている。そのため、逆電圧波形の跳ね上がり電圧は
小さく、電圧振動が抑制されている。FIGS. 9A and 9B show reverse recovery current and voltage waveforms during the diode operation. FIG. 9A shows a current waveform, and FIG. 9B shows a voltage waveform. The conventional product is a reverse blocking IGBT shown in FIG.
The product of the present invention is a reverse blocking IGBT shown in FIG. The product of the present invention has a smaller reverse recovery current and a soft recovery waveform. Therefore, the jump voltage of the reverse voltage waveform is small, and the voltage oscillation is suppressed.
【００３４】図１０は、この発明の第３実施例の半導体
装置の要部断面図である。この半導体装置はトレンチゲ
ート型の逆阻止ＩＧＢＴの例である。ゲート構造が、ト
レンチ溝の中にゲート酸化膜２６を介してゲート電極２
４が形成されている点が図１と異なる。ｐ+ コレクタ領
域５の構造や半導体基板２００の厚さは図１の場合と同
じであり、図１と同じ効果が期待できる。FIG. 10 is a sectional view of a principal part of a semiconductor device according to a third embodiment of the present invention. This semiconductor device is an example of a trench gate type reverse blocking IGBT. The gate structure includes a gate electrode 2 in the trench with a gate oxide film 26 interposed therebetween.
4 is different from FIG. The structure of p + collector region 5 and the thickness of semiconductor substrate 200 are the same as those in FIG. 1, and the same effects as in FIG. 1 can be expected.
【００３５】図１１と図１２は、この発明の第４実施例
の半導体装置の製造方法で、要部製造工程断面図であ
る。この半導体装置はトレンチゲート型の逆阻止ＩＧＢ
Ｔである。図１１は図５に相当する図で、図１２は図８
に相当する図である。このようにトレンチゲート構造と
することで、短絡耐量は低下するものの、プレーナゲー
ト型よりもキャリア分布がエミッタ側偏重となり、オン
電圧−ターンオフ損失のトレードオフが向上する。さら
に同じオン電圧であれば、より一層ソフトリカバリー波
形の逆回復特性を得ることが出来る。FIGS. 11 and 12 are cross-sectional views of a main part manufacturing process in a method of manufacturing a semiconductor device according to a fourth embodiment of the present invention. This semiconductor device is a trench gate type reverse blocking IGB.
T. FIG. 11 is a diagram corresponding to FIG. 5, and FIG.
FIG. By adopting the trench gate structure in this manner, although the short-circuit withstand capability is reduced, the carrier distribution is more concentrated on the emitter side than in the planar gate type, and the trade-off between on-voltage and turn-off loss is improved. Further, with the same ON voltage, the reverse recovery characteristic of the soft recovery waveform can be further obtained.
【００３６】前記の図１、図１０の逆方向のアバランシ
ェ電圧が順方向のアバランシェ電圧より高い逆阻止型Ｉ
ＧＢＴを、図１５のように、互いに逆並列に接続するこ
とで、この双方向ＩＧＢＴに、順または逆方向のサージ
電圧が印加された場合には、順方向に電圧が印加された
ＩＧＢＴがアバランシェに突入するために、順、逆方向
のアバランシェで発生する損失を逆並列した両者のＩＧ
ＢＴで均等に受け持つために、双方向ＩＧＢＴのアバラ
ンシェ耐量を強化できる。The reverse blocking type I in which the reverse avalanche voltage in FIGS. 1 and 10 is higher than the forward avalanche voltage.
By connecting the GBTs in antiparallel with each other as shown in FIG. 15, when a forward or reverse surge voltage is applied to the bidirectional IGBT, the IGBT to which the forward voltage is applied is avalanche. In order to rush into the IG, the loss that occurs in the forward and reverse avalanche
The avalanche withstand capability of the bidirectional IGBT can be strengthened so that the BT can equally take charge.
【００３７】また、ｐ+ コレクタ領域が０．１μｍない
し１０μｍ（好ましくは２μｍ）と薄くすると、さらに
オン電圧−ターンオフ損失のトレードオフが良好で、逆
回復電流が小さな、ソフトリカバリー波形の双方向ＩＧ
ＢＴを形成できる。図１８は、この発明の第５実施例の
半導体装置の要部断面図である。ｎ型の半導体基板３０
０の第１主面の表面層にｐベース領域３２を形成し、ｐ
ベース領域３２の表面層にｎ+ エミッタ領域３４を形成
し、半導体基板３００とｎ+ エミッタ領域３４に挟まれ
たｐベース領域３２上にゲート酸化膜３５を介してゲー
ト電極３６を形成する。ゲート電極３６上に層間絶縁膜
３７を形成し、エミッタ電極３８を形成する。半導体基
板３００の第２主面の表面層にｐ+ コレクタ領域３３を
形成し、ｐ+ コレクタ領域３３の表面にコレクタ電極３
９を形成する。最外周のｐベース領域３２と離して溝４
６を形成し、この溝４６の表面を化学処理して、ベベル
部４１を形成する。このベベル部４１表面に、例えばガ
ラスやシリコーンゴムなどの絶縁膜を保護膜４２として
形成する。When the p + collector region is as thin as 0.1 μm to 10 μm (preferably 2 μm), the trade-off between on-voltage and turn-off loss is good, the reverse recovery current is small, and the bidirectional IG having a soft recovery waveform is small.
BT can be formed. FIG. 18 is a sectional view showing a main part of a semiconductor device according to a fifth embodiment of the present invention. n-type semiconductor substrate 30
0, a p base region 32 is formed in the surface layer of the first main surface, and p
An n + emitter region 34 is formed on the surface layer of the base region 32, and a gate electrode 36 is formed on the p base region 32 between the semiconductor substrate 300 and the n + emitter region 34 via a gate oxide film 35. An interlayer insulating film 37 is formed on the gate electrode 36, and an emitter electrode 38 is formed. A p + collector region 33 is formed on the surface layer of the second main surface of the semiconductor substrate 300, and a collector electrode 3 is formed on the surface of the p + collector region 33.
9 is formed. Groove 4 spaced apart from outermost p base region 32
6 is formed, and the surface of the groove 46 is chemically treated to form the bevel portion 41. On the surface of the bevel portion 41, an insulating film such as glass or silicone rubber is formed as a protective film.
【００３８】ｐ+ コレクタ領域３３の厚さ（深さ）は
０．１μｍから１０μｍとする。この厚さが薄い場合
は、溝４６がｐ+ コレクタ領域３３表面に達して、溝４
６の左側の 半導体基板３００は切り落とされる。この
ベベル部４１はポジティブベベルとし、そのベベル角θ
を所定の値に設定することで、ｐｎ接合４３の逆方向の
アバランシェ電圧をｐｎ接合４４の順方向のアバランシ
ェ電圧より、１０％から２０％高くすることができる。
この高くする割合は、製造ばらつき以上とする。この逆
阻止型ＩＧＢＴを用いて図１５の双方向ＩＧＢＴを製作
すると、順、逆方向のサージ電圧が印加されたとき、片
方の逆阻止型ＩＧＢＴにのみサージ電流が流れることが
なく、双方向ＩＧＢＴのサージ耐量を向上させることが
できる。The thickness (depth) of p + collector region 33 is 0.1 μm to 10 μm. If the thickness is small, the groove 46 reaches the surface of the p + collector region 33 and the groove 4
The semiconductor substrate 300 on the left side of 6 is cut off. The bevel portion 41 is a positive bevel and its bevel angle θ
Is set to a predetermined value, the reverse avalanche voltage of the pn junction 43 can be made higher by 10% to 20% than the forward avalanche voltage of the pn junction 44.
The rate of this increase is set to be equal to or more than the manufacturing variation. When the bidirectional IGBT shown in FIG. 15 is manufactured using the reverse blocking IGBT, when a forward or reverse surge voltage is applied, no surge current flows through only one of the reverse blocking IGBTs. Can withstand surges.
【００３９】また、表面部４５をフィールドプレート構
造やガードリング構造とすることで、順方向耐圧を容易
に確保できる。尚、半導体基板３００で各領域が形成さ
れない箇所がｎ- ドリフト領域３１となる。また、前記
のように、ｐ+ コレクタ領域３３の厚さを０．１μｍか
ら１０μｍとすることで、オン電圧−ターンオフ損失の
トレードオフが向上する。さらに同じオン電圧であれ
ば、より一層ソフトリカバリー波形の逆回復特性を得る
ことが出来る。また、ｐ+ コレクタ領域３３の厚さを２
μｍ以下とすることで、逆回復電流の低下など、逆回復
特性を一層向上できる。Further, by forming the surface portion 45 with a field plate structure or a guard ring structure, a forward breakdown voltage can be easily secured. Note that a portion where each region is not formed in the semiconductor substrate 300 is an n − drift region 31. Further, as described above, by setting the thickness of p + collector region 33 to 0.1 μm to 10 μm, the trade-off between on-voltage and turn-off loss is improved. Further, with the same ON voltage, the reverse recovery characteristic of the soft recovery waveform can be further obtained. Further, the thickness of p + collector region 33 is set to 2
When the thickness is not more than μm, the reverse recovery characteristics such as a decrease in the reverse recovery current can be further improved.
【００４０】図１９は、この発明の第６実施例の半導体
装置の制御方法を説明する図で、同図（ａ）は等価回路
図、同図（ｂ）は、同図（ａ）の第１のＩＧＢＴの要部
断面図である。同図（ｂ）は、図１と同じである。Ｔ１
が負で、Ｔ２が正の電圧が印加されている場合、左側の
第１のＩＧＢＴはＥ１に正電圧が印加されて、逆バイア
ス状態となる。この状態のときに、エミッタ端子Ｅ１に
対して、ゲート端子Ｇ１に、しきい値電圧以上の正電圧
を印加し、第１のＩＧＢＴのｐベース領域の表面層にチ
ャネル４８を形成する。FIGS. 19A and 19B are diagrams illustrating a method of controlling a semiconductor device according to a sixth embodiment of the present invention. FIG. 19A is an equivalent circuit diagram, and FIG. FIG. 2 is a sectional view of a main part of the IGBT of FIG. FIG. 2B is the same as FIG. T1
Is negative and a positive voltage is applied to T2, a positive voltage is applied to E1 of the first IGBT on the left, and the first IGBT on the left side is in a reverse bias state. In this state, a positive voltage equal to or higher than the threshold voltage is applied to the gate terminal G1 with respect to the emitter terminal E1, and a channel 48 is formed in the surface layer of the p base region of the first IGBT.
【００４１】このチャネル４８が形成されることで、空
乏層で発生した電子４７はチャネル４８を通ってエミッ
タ電極８に流れ込むために、寄生バイポーラトランジス
タ４９の増幅作用が失われ、ｐベース領域２から、ｎ-
ドリフト領域１へ注入される正孔は抑制される。その結
果、エミッタ電極８からコレクタ電極９に流れる漏れ電
流は大幅に抑制される。Since channel 47 is formed, electrons 47 generated in the depletion layer flow into emitter electrode 8 through channel 48, so that the amplifying action of parasitic bipolar transistor 49 is lost. , n -
Holes injected into the drift region 1 are suppressed. As a result, the leakage current flowing from the emitter electrode 8 to the collector electrode 9 is largely suppressed.
【００４２】図２０は、逆漏れ電流と逆バイアス電圧の
関係を示す図である。ゲート電極に電圧を印加しない場
合と１５Ｖの正電圧を印加した場合の１２５℃の逆漏れ
電流を示す。ゲート電極に１５Ｖの正電圧を印加した場
合は、逆漏れ電流は逆バイアス電圧を大きくしても増加
の割合は極めて小さい。FIG. 20 is a diagram showing the relationship between the reverse leakage current and the reverse bias voltage. A reverse leakage current of 125 ° C. is shown when no voltage is applied to the gate electrode and when a positive voltage of 15 V is applied. When a positive voltage of 15 V is applied to the gate electrode, the rate of increase in reverse leakage current is extremely small even if the reverse bias voltage is increased.
【００４３】[0043]
【発明の効果】この発明によると、半導体基板の厚みが
５０から２００μｍで、コレクタ領域の厚さを０．１な
いし１０μｍにし、コレクタ領域のピーク濃度を５×１
０16ｃｍ-3〜１×１０18ｃｍ-3とすることで、ＩＧＢＴ
動作時およびダイオード順動作時の過剰キャリアの蓄積
量を抑制しながら、オン電圧を低減し、ＩＧＢＴのオン
電圧とターンオフ損失のトレードオフを改善でき、ま
た、ダイオード逆動作時の逆回復電流を低減し、ソフト
リカバリー特性を得ることができる。According to the present invention, the thickness of the semiconductor substrate is 50 to 200 μm, the thickness of the collector region is 0.1 to 10 μm, and the peak concentration of the collector region is 5 × 1.
The IGBT is set to be from 0 16 cm −3 to 1 × 10 18 cm −3.
The ON voltage can be reduced, the trade-off between the ON voltage of the IGBT and the turn-off loss can be improved, and the reverse recovery current during the reverse operation of the diode can be reduced while suppressing the excess carrier accumulation during operation and diode forward operation. Thus, a soft recovery characteristic can be obtained.
【００４４】また、イオン注入し、３００℃から５００
℃の低温アニール処理（レーザーアニールなど）をする
ことで、０．１μｍから１０μｍの厚さのコレクタ領域
をエミッタ電極を溶融させずに形成することができる。
また、ｐベース領域の側面が高濃度ｐ+ 領域で囲まれて
いるので、逆方向のアバランシェ電圧を印加した際にも
空乏領域がシリコン側面に現れることはなく、逆方向の
アバランシェ電圧を順方向のアバランシェ電圧より高く
することができる。Further, ion implantation is performed, and
By performing a low-temperature annealing process (eg, laser annealing) at a temperature of 0.1 ° C., a collector region having a thickness of 0.1 μm to 10 μm can be formed without melting the emitter electrode.
Further, since the side surface of the p base region is surrounded by the high concentration p + region, the depletion region does not appear on the silicon side surface even when the reverse avalanche voltage is applied, and the reverse avalanche voltage is applied in the forward direction. Higher than the avalanche voltage.
【００４５】また、逆耐圧を維持するｐｎ接合の端部に
ポジティブベベル構造を採用することで、逆方向のアバ
ランシェ電圧を順方向のアバランシェ電圧より高くする
ことができる。また、逆方向のアバランシェ電圧が順方
向のアバランシェ電圧より高い逆阻止型ＩＧＢＴを、互
いに逆並列に接続した双方向ＩＧＢＴに、順および逆方
向のサージ電圧を印加した場合に、順方向にサージ電圧
が印加されたＩＧＢＴにアバランシェ電流が流れるため
に、順および逆方向のサージ電圧が印加されて発生する
損失を、逆並列したそれぞれの逆阻止型ＩＧＢＴが分担
し、その結果、双方向ＩＧＢＴとしてのサージ耐量を向
上させることができる。Also, by employing a positive bevel structure at the end of the pn junction for maintaining the reverse breakdown voltage, the reverse avalanche voltage can be made higher than the forward avalanche voltage. When a forward and reverse surge voltage is applied to a bidirectional IGBT in which a reverse avalanche voltage is higher than a forward avalanche voltage and a reverse blocking IGBT is connected in antiparallel to each other, a forward surge voltage is applied. Since the avalanche current flows through the IGBT to which the IGBT is applied, the reverse blocking IGBTs in antiparallel share the loss that occurs due to the application of the forward and reverse surge voltages. Surge tolerance can be improved.
【００４６】また、ＩＧＢＴが逆バイアスされる時に、
ゲート電極にしきい値電圧以上の正電圧を加えると、Ｉ
ＧＢＴの寄生バイポーラトランジスタの増幅作用が失わ
れて、逆漏れ電流を大幅に低減することができる。When the IGBT is reverse-biased,
When a positive voltage higher than the threshold voltage is applied to the gate electrode, I
The amplification effect of the parasitic bipolar transistor of the GBT is lost, and the reverse leakage current can be greatly reduced.
【図１】この発明の第１実施例の半導体装置の要部断面
図FIG. 1 is a sectional view of a main part of a semiconductor device according to a first embodiment of the present invention;
【図２】この発明の第２実施例の半導体装置の要部製造
工程断面図FIG. 2 is a sectional view of a main part manufacturing process of a semiconductor device according to a second embodiment of the present invention;
【図３】図２に続く、この発明の第２実施例の半導体装
置の要部製造工程断面図FIG. 3 is a sectional view of a main part manufacturing step of the semiconductor device according to the second embodiment of the present invention, following FIG. 2;
【図４】図３に続く、この発明の第２実施例の半導体装
置の要部製造工程断面図FIG. 4 is a sectional view of a main part manufacturing step of the semiconductor device according to the second embodiment of the present invention, following FIG. 3;
【図５】図４に続く、この発明の第２実施例の半導体装
置の要部製造工程断面図FIG. 5 is a sectional view of a main part manufacturing step of the semiconductor device according to the second embodiment of the present invention, following FIG. 4;
【図６】図５に続く、この発明の第２実施例の半導体装
置の要部製造工程断面図FIG. 6 is a sectional view of a main part manufacturing step of the semiconductor device according to the second embodiment of the present invention, following FIG. 5;
【図７】図６に続く、この発明の第２実施例の半導体装
置の要部製造工程断面図FIG. 7 is a cross-sectional view of a main part manufacturing step of the semiconductor device according to the second embodiment of the present invention, following FIG. 6;
【図８】図７に続く、この発明の第２実施例の半導体装
置の要部製造工程断面図FIG. 8 is a sectional view of a main part manufacturing step of the semiconductor device according to the second embodiment of the present invention, following FIG. 7;
【図９】ダイオード動作時の逆回復電流・電圧波形で、
（ａ）は電流波形図、（ｂ）は逆電圧波形図FIG. 9 shows reverse recovery current / voltage waveforms during diode operation.
(A) is a current waveform diagram, (b) is a reverse voltage waveform diagram
【図１０】この発明の第３実施例の半導体装置の要部断
面図FIG. 10 is a sectional view of a main part of a semiconductor device according to a third embodiment of the present invention;
【図１１】この発明の第４実施例の半導体装置の要部製
造工程断面図FIG. 11 is a sectional view showing a main part manufacturing process of a semiconductor device according to a fourth embodiment of the present invention;
【図１２】この発明の第４実施例の半導体装置の要部製
造工程断面図FIG. 12 is a sectional view of a main part manufacturing step of a semiconductor device according to a fourth embodiment of the present invention;
【図１３】従来のプレーナゲート型ＩＧＢＴの要部断面
図FIG. 13 is a sectional view of a main part of a conventional planar gate type IGBT.
【図１４】エピタキシャル基板を使用した従来の逆阻止
型ＩＧＢＴの要部断面図FIG. 14 is a sectional view of a main part of a conventional reverse blocking IGBT using an epitaxial substrate.
【図１５】双方向ＩＧＢＴの等価回路図FIG. 15 is an equivalent circuit diagram of a bidirectional IGBT.
【図１６】ＦＺ基板を使用し、熱拡散で形成した従来の
逆阻止型ＩＧＢＴの要部断面図FIG. 16 is a cross-sectional view of a main part of a conventional reverse blocking IGBT formed by thermal diffusion using an FZ substrate.
【図１７】キャリア分布図FIG. 17 is a carrier distribution diagram.
【図１８】この発明の第５実施例の半導体装置の要部断
面図FIG. 18 is a sectional view showing a main part of a semiconductor device according to a fifth embodiment of the present invention;
【図１９】この発明の第６実施例の半導体装置の制御方
法を説明する図で、（ａ）は等価回路図、（ｂ）は、
（ａ）の第１のＩＧＢＴの要部断面図19A and 19B are diagrams illustrating a method of controlling a semiconductor device according to a sixth embodiment of the present invention, wherein FIG. 19A is an equivalent circuit diagram, and FIG.
FIG. 4A is a cross-sectional view of a main part of the first IGBT.
【図２０】逆漏れ電流と逆バイアス電圧の関係を示す図FIG. 20 is a diagram showing a relationship between a reverse leakage current and a reverse bias voltage.
１、３１ ｎ- ドリフト領域 ２、３２ ｐベース領域 ３、３４ ｎ+ エミッタ領域 ４、２４、３６ ゲート電極 ５、３３ ｐ+ コレクタ領域 ５ａ 裏面のｐ+ コレクタ領域 ６、２６、３５ ゲート酸化膜 ７、３７ 層間絶縁膜 ８、３８ エミッタ電極 ９、３９ コレクタ電極 １１ 初期酸化膜 １２ 開口部 １３ ボロンデポジション領域 １４ 酸化膜 １５ ｐ+ 領域（側面のｐ+ コレクタ領域） １６ 削り面 １７ 切断箇所 ４１ ベベル部 ４２ 保護膜 ４３、４４ ｐｎ接合 ４５ 表面部 ４６ 溝 ４７ 電子 ４８ チャネル ４９ 寄生バイポーラトランジスタ １００、２００、３００ 半導体基板 １０１ ＦＺウエハ1, 31 n - drift region 2, 32 p base region 3,34 n + emitter region 4,24,36 gate electrode 5 and 33 p + collector region 5a rear surface of p + collector region 6,26,35 gate oxide film 7 37, Interlayer insulating film 8, 38 Emitter electrode 9, 39 Collector electrode 11 Initial oxide film 12 Opening 13 Boron deposition region 14 Oxide film 15 P + region (p + collector region on side surface) 16 Shaved surface 17 Cutting point 41 Bevel Part 42 protective film 43, 44 pn junction 45 surface part 46 groove 47 electron 48 channel 49 parasitic bipolar transistor 100, 200, 300 semiconductor substrate 101 FZ wafer
Claims (16)
に選択的に形成される第２導電形ベース領域と、該ベー
ス領域の表面層に選択的に形成される第１導電形エミッ
タ領域と、前記半導体基板と前記エミッタ領域に挟まれ
た前記ベース領域上にゲート絶縁膜を介して形成される
ゲート電極と、前記半導体基板の第２主面の表面層に形
成される第２導電形コレクタ領域と、前記エミッタ領域
上と前記ベース領域上に選択的に形成されるエミッタ電
極と、前記コレクタ領域上に形成されるコレクタ電極と
を有する半導体装置において、 前記第１導電形半導体基板と前記コレクタ領域との境界
に形成されるｐｎ接合の逆方向のアバランシェ電圧が、
前記第１導電形半導体基板と前記第２導電形ベース領域
との境界に形成されるｐｎ接合の順方向のアバランシェ
電圧より、高いことを特徴とする半導体装置。A first conductivity type base region selectively formed on a surface layer of a first main surface of the first conductivity type semiconductor substrate; and a first conductivity type selectively formed on a surface layer of the base region. An emitter region, a gate electrode formed on the base region between the semiconductor substrate and the emitter region via a gate insulating film, and a second electrode formed on a surface layer of a second main surface of the semiconductor substrate. A semiconductor device comprising: a two-conductivity-type collector region; an emitter electrode selectively formed on the emitter region and the base region; and a collector electrode formed on the collector region. The avalanche voltage in the reverse direction of the pn junction formed at the boundary between the substrate and the collector region is:
A semiconductor device, which is higher than a forward avalanche voltage of a pn junction formed at a boundary between the first conductivity type semiconductor substrate and the second conductivity type base region.
に選択的に形成される第２導電形ベース領域と、該ベー
ス領域の表面層に選択的に形成される第１導電形エミッ
タ領域と、前記半導体基板と前記エミッタ領域に挟まれ
た前記ベース領域上にゲート絶縁膜を介して形成される
ゲート電極と、前記ベース領域を取り囲むように、前記
半導体基板の第２主面および前記半導体基板の第１主面
から第２主面に亘って形成される第２導電形コレクタ領
域と、前記エミッタ領域上と前記ベース領域上に選択的
に形成されるエミッタ電極と、前記コレクタ領域上に形
成されるコレクタ電極とを有する半導体装置において、 前記第１導電形半導体基板と、前記第２主面側に形成さ
れる前記コレクタ領域との境界に形成されるｐｎ接合の
逆方向のアバランシェ電圧が、前記第１導電形半導体基
板、前記第２導電形ベース領域との境界に形成されるｐ
ｎ接合の順方向のアバランシェ電圧より、高いことを特
徴とする半導体装置。2. A second conductivity type base region selectively formed on a surface layer of a first main surface of a first conductivity type semiconductor substrate, and a first conductivity type selectively formed on a surface layer of the base region. A second main surface of the semiconductor substrate so as to surround the base region; a gate electrode formed on the base region between the semiconductor substrate and the emitter region via a gate insulating film; A second conductivity type collector region formed from a first main surface to a second main surface of the semiconductor substrate; an emitter electrode selectively formed on the emitter region and the base region; A semiconductor device having a collector electrode formed on a region, wherein a pn junction is formed in a direction opposite to a pn junction formed on a boundary between the first conductivity type semiconductor substrate and the collector region formed on the second main surface side. Avalan A shee voltage is generated at a boundary between the first conductivity type semiconductor substrate and the second conductivity type base region.
A semiconductor device having a higher avalanche voltage in a forward direction of an n-junction.
に選択的に形成される第２導電形ベース領域と、該ベー
ス領域の表面から前記ベース層を貫通し、前記半導体基
板内に到達するように形成されたトレンチ溝と、該トレ
ンチ溝にゲート絶縁膜を介して形成されるゲート電極
と、前記ベース領域の表面層に、前記トレンチ溝と接し
て、選択的に形成される第１導電形エミッタ領域と、前
記ベース領域を取り囲むように、前記半導体基板の第２
主面および前記半導体基板の第１主面から第２主面に亘
って形成される第２導電形コレクタ領域とを有する半導
体装置において、 前記第１導電形半導体基板と、前記第２主面側に形成さ
れる前記コレクタ領域との境界に形成されるｐｎ接合の
逆方向のアバランシェ電圧が、前記第１導電形半導体基
板、前記第２導電形ベース領域との境界に形成されるｐ
ｎ接合の順方向のアバランシェ電圧より、高いことを特
徴とする半導体装置。A second conductive type base region selectively formed on a surface layer of a first main surface of the first conductive type semiconductor substrate; and a semiconductor substrate penetrating the base layer from a surface of the base region. A trench groove formed so as to reach the inside, a gate electrode formed in the trench groove via a gate insulating film, and a surface layer of the base region, which is selectively formed in contact with the trench groove. A second conductivity type emitter region surrounding the base region and a first conductivity type emitter region.
In a semiconductor device having a main surface and a second conductivity type collector region formed from a first main surface to a second main surface of the semiconductor substrate, the first conductivity type semiconductor substrate and the second main surface side The avalanche voltage in the reverse direction of the pn junction formed at the boundary with the collector region formed at the boundary between the first conductivity type semiconductor substrate and the second conductivity type base region
A semiconductor device having a higher avalanche voltage in a forward direction of an n-junction.
に選択的に形成される第２導電形ベース領域と、該ベー
ス領域の表面層に選択的に形成される第１導電形エミッ
タ領域と、前記半導体基板と前記エミッタ領域に挟まれ
た前記ベース領域上にゲート絶縁膜を介して形成される
ゲート電極と、前記ベース領域を取り囲むように、前記
半導体基板の第２主面および前記半導体基板の第１主面
から第２主面に亘って形成される第２導電形コレクタ領
域と、前記エミッタ領域上と前記ベース領域上に選択的
に形成されるエミッタ電極と、前記コレクタ領域上に形
成されるコレクタ電極とを有する半導体装置において、 前記半導体基板の第２主面側に形成され、前記半導体基
板とコレクタ電極との間に位置する前記コレクタ領域の
厚みが、０．１μｍないし１０μｍであることを特徴と
する半導体装置。4. A second conductivity type base region selectively formed on a surface layer of a first main surface of a first conductivity type semiconductor substrate, and a first conductivity type selectively formed on a surface layer of the base region. A second main surface of the semiconductor substrate so as to surround the base region; a gate electrode formed on the base region between the semiconductor substrate and the emitter region via a gate insulating film; A second conductivity type collector region formed from a first main surface to a second main surface of the semiconductor substrate; an emitter electrode selectively formed on the emitter region and the base region; In a semiconductor device having a collector electrode formed on a region, a thickness of the collector region formed on the second main surface side of the semiconductor substrate and located between the semiconductor substrate and the collector electrode is 0.1 μm. To a semiconductor device which is a 10 [mu] m.
に選択的に形成される第２導電形ベース領域と、該ベー
ス領域の表面から前記ベース層を貫通し、前記半導体基
板内に到達するように形成されたトレンチ溝と、該トレ
ンチ溝にゲート絶縁膜を介して形成されるゲート電極
と、前記ベース領域の表面層に、前記トレンチ溝と接し
て、選択的に形成される第１導電形エミッタ領域と、前
記ベース領域を取り囲むように、前記半導体基板の第２
主面および前記半導体基板の第１主面から第２主面に亘
って形成される第２導電形コレクタ領域とを有する半導
体装置において、 前記半導体基板の第２主面側に形成され、前記半導体基
板とコレクタ電極との間に位置する前記コレクタ領域の
厚みが、０．１μｍないし１０μｍであることを特徴と
する半導体装置。5. A second conductivity type base region selectively formed on a surface layer of a first main surface of a first conductivity type semiconductor substrate, and said semiconductor substrate penetrating through said base layer from a surface of said base region. A trench groove formed so as to reach the inside, a gate electrode formed in the trench groove via a gate insulating film, and a surface layer of the base region, which is selectively formed in contact with the trench groove. A second conductivity type emitter region surrounding the base region and a first conductivity type emitter region.
A semiconductor device having a main surface and a second conductivity type collector region formed from a first main surface to a second main surface of the semiconductor substrate, wherein the semiconductor device is formed on a second main surface side of the semiconductor substrate; A semiconductor device, wherein a thickness of the collector region located between a substrate and a collector electrode is 0.1 μm to 10 μm.
に選択的に第２導電形ベース領域を形成し、該ベース領
域の表面層に選択的に第１導電形エミッタ領域を形成
し、前記半導体基板と前記エミッタ領域に挟まれた前記
ベース領域上にゲート絶縁膜を介してゲート電極を形成
し、前記ベース領域を取り囲むように、前記半導体基板
の第２主面および前記半導体基板の第１主面から第２主
面に亘って形成される第２導電形コレクタ領域とを有す
る半導体装置の製造方法において、 前記ベース領域の側面を取り囲むコレクタ領域となる第
２導電形の第１領域を、前記ベース領域より深い深さで
半導体基板の第１主面側から形成する工程と、該半導体
基板の第２主面側を、前記第１領域が露出する深さに削
除する工程と、該第１領域が露出した第２主面の表面層
に０．１μｍないし１０μｍの深さで、前記第１領域に
接して、前記第２主面側のコレクタ領域となる第２導電
形の第２領域を形成する工程とを含むことを特徴とする
半導体装置の製造方法。6. A second conductivity type base region is selectively formed on a surface layer of a first main surface of a first conductivity type semiconductor substrate, and a first conductivity type emitter region is selectively formed on a surface layer of the base region. Forming a gate electrode on the base region interposed between the semiconductor substrate and the emitter region via a gate insulating film; and forming a second main surface of the semiconductor substrate and the semiconductor so as to surround the base region. A method of manufacturing a semiconductor device having a second conductivity type collector region formed from a first main surface to a second main surface of a substrate, wherein the second conductivity type second region is a collector region surrounding a side surface of the base region. Forming one region from the first main surface side of the semiconductor substrate at a depth deeper than the base region; and removing the second main surface side of the semiconductor substrate to a depth where the first region is exposed. And the first region where the first region is exposed. Forming a second region of the second conductivity type in the surface layer of the second main surface at a depth of 0.1 μm to 10 μm in contact with the first region and serving as the collector region on the second main surface side. A method for manufacturing a semiconductor device, comprising:
に選択的に第２導電形ベース領域を形成し、該ベース領
域の表面から該ベース領域を貫通し、前記半導体基板内
に到達するトレンチ溝を形成し、該トレンチ溝にゲート
絶縁膜を介してゲート電極を形成し、前記ベース領域の
表面層に前記トレンチ溝と接して、第１導電形エミッタ
領域を選択的に形成し、前記ベース領域を取り囲むよう
に、前記半導体基板に形成される第２導電形コレクタ領
域を有する半導体装置の製造方法において、 前記ベース領域の側面を取り囲むコレクタ領域となる第
２導電形の第１領域を、前記ベース領域より深い深さで
半導体基板の第１主面側から形成する工程と、該半導体
基板の第２主面側を、前記第１領域が露出する深さに削
除する工程と、該第１領域が露出した第２主面の表面層
に０．１μｍないし１０μｍの深さで、前記第１領域に
接して、前記第２主面側のコレクタ領域となる第２導電
形の第２領域を形成する工程とを含むことを特徴とする
半導体装置の製造方法。7. A second conductivity type base region is selectively formed in a surface layer of a first main surface of a first conductivity type semiconductor substrate, and penetrates through the base region from a surface of the base region. Is formed, a gate electrode is formed in the trench groove via a gate insulating film, and a first conductivity type emitter region is selectively formed in a surface layer of the base region in contact with the trench groove. A method of manufacturing a semiconductor device having a second conductivity type collector region formed on the semiconductor substrate so as to surround the base region, wherein the first of the second conductivity type serving as a collector region surrounding a side surface of the base region; Forming a region from the first main surface side of the semiconductor substrate at a depth deeper than the base region, and removing the second main surface side of the semiconductor substrate to a depth at which the first region is exposed; , The first region is A second region of the second conductivity type, which is a collector region on the second main surface side, is formed on the exposed surface layer of the second main surface at a depth of 0.1 μm to 10 μm in contact with the first region. And a method of manufacturing a semiconductor device.
イオン注入し、３００℃ないし５００℃で熱処理されて
形成されることを特徴とする請求項６または７に記載の
半導体装置の製造方法。8. The method of manufacturing a semiconductor device according to claim 6, wherein said collector region is formed by ion-implanting a second conductivity type impurity and heat-treating at 300 ° C. to 500 ° C. .
ン注入し、レーザーアニール処理で形成されることを特
徴とする請求項６または７に記載の半導体装置の製造方
法。9. The method of manufacturing a semiconductor device according to claim 6, wherein said second region is formed by ion-implanting a second conductivity type impurity and performing laser annealing.
形不純物のピーク濃度が５×１０16ｃｍ-3以上で、１×
１０18ｃｍ-3以下であることを特徴とする請求項６ない
し９に記載の半導体装置の製造方法。10. The method according to claim 1, wherein a peak concentration of the activated second conductivity type impurity in said collector region is 5 × 10 16 cm -3 or more.
10. The method for manufacturing a semiconductor device according to claim 6, wherein the semiconductor device is 10 18 cm −3 or less.
タ領域表面から、前記第２主面側に形成された前記コレ
クタ領域表面までの距離が５０μｍないし２００μｍで
あることを特徴とする請求項６または７に記載の半導体
装置の製造方法。11. The distance from the surface of the emitter region formed on the first main surface side to the surface of the collector region formed on the second main surface side is 50 μm to 200 μm. Item 8. The method for manufacturing a semiconductor device according to item 6 or 7.
層に選択的に形成される第２導電形ベース領域と、該ベ
ース領域の表面層に選択的に形成される第１導電形エミ
ッタ領域と、前記半導体基板と前記エミッタ領域に挟ま
れた前記ベース領域上にゲート絶縁膜を介して形成され
るゲート電極と、前記半導体基板の第２主面の表面層に
形成される第２導電形コレクタ領域と、前記エミッタ領
域上と前記ベース領域上に選択的に形成されるエミッタ
電極と、前記コレクタ領域上に形成されるコレクタ電極
とを有し、前記第１導電形半導体基板と前記コレクタ領
域との境界に形成されるｐｎ接合と、前記第１導電形半
導体基板と前記第２導電形ベース領域との境界に形成さ
れるｐｎ接合とが、前記第１導電形半導体基板の側面に
露出するベベル構造を有する半導体装置において、前記
第１導電形半導体基板と前記コレクタ領域との境界に形
成されるｐｎ接合の逆方向のアバランシェ電圧を、前記
第１導電形半導体基板と前記第２導電形ベース領域との
境界に形成されるｐｎ接合の順方向のアバランシェ電圧
より、高くすることを特徴とする半導体装置。12. A second conductivity type base region selectively formed on a surface layer of a first main surface of a first conductivity type semiconductor substrate, and a first conductivity type selectively formed on a surface layer of the base region. An emitter region, a gate electrode formed on the base region between the semiconductor substrate and the emitter region via a gate insulating film, and a second electrode formed on a surface layer of a second main surface of the semiconductor substrate. A second conductivity type collector region, an emitter electrode selectively formed on the emitter region and the base region, and a collector electrode formed on the collector region; A pn junction formed at a boundary with the collector region and a pn junction formed at a boundary between the first conductivity type semiconductor substrate and the second conductivity type base region are formed on a side surface of the first conductivity type semiconductor substrate. Bevel structure exposed to Wherein the avalanche voltage in the opposite direction of the pn junction formed at the boundary between the first conductivity type semiconductor substrate and the collector region is adjusted by the first conductivity type semiconductor substrate and the second conductivity type base region. A semiconductor device, wherein the voltage is higher than the forward avalanche voltage of a pn junction formed at the boundary of.
層に選択的に形成される第２導電形ベース領域と、該ベ
ース領域の表面層に選択的に形成される第１導電形エミ
ッタ領域と、前記半導体基板と前記エミッタ領域に挟ま
れた前記ベース領域上にゲート絶縁膜を介して形成され
るゲート電極と、前記半導体基板の第２主面の表面層に
形成される第２導電形コレクタ領域と、前記エミッタ領
域上と前記ベース領域上に選択的に形成されるエミッタ
電極と、前記コレクタ領域上に形成されるコレクタ電極
とを有し、前記第１導電形半導体基板と前記コレクタ領
域との境界に形成されるｐｎ接合と、前記第１導電形半
導体基板と前記第２導電形ベース領域との境界に形成さ
れるｐｎ接合とが、前記第１導電形半導体基板の側面に
露出するベベル構造を有する半導体装置において、前記
半導体基板の第２主面側に形成され、前記半導体基板と
コレクタ電極との間に位置する前記コレクタ領域の厚み
が、０．１μｍないし１０μｍであることを特徴とする
半導体装置。13. A second conductivity type base region selectively formed on a surface layer of a first main surface of a first conductivity type semiconductor substrate, and a first conductivity type selectively formed on a surface layer of the base region. An emitter region, a gate electrode formed on the base region between the semiconductor substrate and the emitter region via a gate insulating film, and a second electrode formed on a surface layer of a second main surface of the semiconductor substrate. A second conductivity type collector region, an emitter electrode selectively formed on the emitter region and the base region, and a collector electrode formed on the collector region; A pn junction formed at a boundary with the collector region and a pn junction formed at a boundary between the first conductivity type semiconductor substrate and the second conductivity type base region are formed on a side surface of the first conductivity type semiconductor substrate. Bevel structure exposed to Wherein the thickness of the collector region formed on the second main surface side of the semiconductor substrate and located between the semiconductor substrate and the collector electrode is 0.1 μm to 10 μm. Semiconductor device.
いし２μｍであることを特徴とする請求項４、５および
１３のいづれかに記載の半導体装置。14. The semiconductor device according to claim 4, wherein said collector region has a thickness of 0.1 μm to 2 μm.
２ないし請求項１４のいずれかに記載の半導体装置の制
御方法において、前記エミッタ電極の電位に対して前記
コレクタ電極の電位が低電位にある期間、前記エミッタ
電極に対して前記ゲート電極が、しきい値電圧以上の正
電圧を印加され、前記第２導電型ベース領域の表面層に
第１導電型のチャネルを形成することを特徴とする半導
体装置の制御方法。15. The method according to claim 1, wherein:
15. The method for controlling a semiconductor device according to claim 2, wherein the gate electrode is connected to the emitter electrode while the potential of the collector electrode is lower than the potential of the emitter electrode. A method of controlling a semiconductor device, comprising: applying a positive voltage equal to or higher than a threshold voltage to form a channel of a first conductivity type in a surface layer of a base region of a second conductivity type.
エミッタ電極の電位に対して、コレクタ電極の電位が低
電位にある期間、前記エミッタ電極に対してゲート電極
がしきい値電圧以上の正電圧を印加することを特徴とす
る半導体装置の制御方法。16. A reverse blocking IGBT semiconductor device,
A method for controlling a semiconductor device, wherein a gate electrode applies a positive voltage equal to or higher than a threshold voltage to the emitter electrode during a period in which the potential of the collector electrode is lower than the potential of the emitter electrode.
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| JP2000-241627 | 2001-02-14 | ||
| JP2001-36352 | 2001-02-14 | ||
| JP2001159178A JP4967200B2 (en) | 2000-08-09 | 2001-05-28 | Bidirectional IGBT with reverse blocking IGBTs connected in antiparallel |
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| JP2004336008A (en) * | 2003-04-16 | 2004-11-25 | Fuji Electric Holdings Co Ltd | Reverse blocking insulated gate type bipolar transistor and its fabrication method |
| JP2005101551A (en) * | 2003-08-29 | 2005-04-14 | Fuji Electric Holdings Co Ltd | Semiconductor device, its fabricating process, and bidirectional switch element employing semiconductor device |
| JP2005191160A (en) * | 2003-12-25 | 2005-07-14 | Fuji Electric Holdings Co Ltd | Reverse blocking insulated gate bipolar transistor and its manufacturing method |
| JP2005209843A (en) * | 2004-01-22 | 2005-08-04 | Fuji Electric Holdings Co Ltd | Semiconductor device |
| JP2005252212A (en) * | 2003-04-10 | 2005-09-15 | Fuji Electric Holdings Co Ltd | Reverse blocking type semiconductor device and method of manufacturing the same |
| US7009239B2 (en) | 2003-08-08 | 2006-03-07 | Mitsubishi Denki Kabushiki Kaisha | Vertical semiconductor device and manufacturing method thereof |
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