JP4696451B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a power semiconductor device such as a reverse blocking device used in a power conversion device or the like.

A bidirectional IGBT used in a matrix converter circuit or the like has a configuration in which reverse blocking IGBTs are connected in antiparallel. In order to improve reverse recovery characteristics when the reverse blocking IGBT is operated as a diode, a structure in which a part of the collector side is a Schottky junction (Patent Document 1) and a lifetime killer are localized near the collector junction. A structure (Patent Document 2), a structure in which the collector layer is extremely thin (Patent Document 3), and the like are disclosed. Next, the structure of a conventional reverse blocking IGBT will be described. This structure is described in Japanese Patent Application No. 2003-209709.
9A and 9B are configuration diagrams of a conventional reverse blocking IGBT. FIG. 9A is a plan view of the main part, and FIG. 9B is a cross-sectional view of the main part taken along line XX of FIG. is there. The reverse blocking IGBT includes an n ⁻ drift region 51 as the semiconductor substrate 100, a p base region 53 formed for each cell in the surface layer of the n ⁻ drift region 51, and an n ⁺ formed in the surface layer of the p base region 53. An emitter region 56, a gate electrode 58 formed on the p base region 53 between the n ⁺ emitter region 56 and the n ⁻ drift region 51 via a gate insulating film 57, and the n ⁺ emitter region 56 and the p base region 53 An emitter electrode 60 formed in contact with the contact hole 62, an interlayer insulating film 59 for insulating the gate electrode 58 and the emitter electrode 60, a p ⁺ collector region 65 formed on the back surface of the n ⁻ drift region 51, and this p A p isolation layer (hereinafter referred to as isolation layer 4a) formed on the side surface of the n ⁻ drift region 51 in contact with the ⁺ collector region 65, and a collector layer formed on the p ⁺ collector region 65; It is composed of a Kuta electrode 66.

The surface of the n ⁻ drift region 51 between the cells of the reverse blocking IGBT is covered with a gate insulating film 57 and is electrically separated from the emitter electrode 60. The separation layer structure of this conventional reverse blocking IGBT will be described in more detail.
FIG. 10 is a plan view showing the shape near the corner of the separation layer structure of a conventional reverse blocking IGBT. This plan view is a plan view of the state of the wafer 1 before being formed into chips. The isolation layer 4 (before dicing) diffuses boron from the opening 5 of the mask (opening width is 2 W, and the width W of the half of the opening is shown in the figure) using the oxide film as a mask. It is formed. In this example, the center of curvature of the opening end 8 of the mask of the separation layer 4 coincides with the center of curvature 9 of the active portion end 6. When boron is diffused, the curvature center position of the separation layer pn junction 7 does not move in accordance with the curvature center position 9 of the active portion end 6 (according to actual measurement). Therefore, the diffused separation layer pn junction 7, the opening end 8 of the mask of the separation layer 4, and the curvature center position 9 of the active portion end 6 all coincide with each other and are concentric at the corner. Therefore, if the width of the pressure-resistant structure at the straight portion is Wos, R = Wos + Ro.

When a reverse bias is applied to the separation layer 4a (after the wafer is cut) after the chip is formed, the depletion layer is closer to the n ⁻ layer 15 (the n ⁻ drift region 51 in FIG. 9) side than the straight portion at the corner portion. Makes it easier to stretch. This is because the amount of space charge in the inner peripheral portion is smaller in the corner portion than in the junction generated when the depletion layer extends for a certain distance. In other words, in order to generate the same amount of space charge, the depletion layer at the corner must extend farther from the straight line toward the inner periphery.
As a result, the depletion layer easily punches through to the active portion through the breakdown voltage structure at the corner portion during reverse bias. This is undesirable because it reduces the reverse breakdown voltage. The elongation of the depletion layer at the corner will be described.
FIG. 11 schematically shows the elongation of the depletion layer during reverse bias breakdown. The depletion layer maximum width Dsmax of the straight line portion is given by assuming that the isolation layer pn junction breakdown voltage is Vb.

(Equation 1)
Dsmax = 2Vb / Emax (1)
It is represented by Emax is the critical electric field strength of silicon. Since the separation layer 4a also has a curvature in the depth direction, it is actually a spherical surface at the corner portion, and the depletion layer end 19 is somewhat difficult to extend, but is assumed to be cylindrical for simplicity. The amount of space charge Q per unit length along the pn junction direction is

(Equation 2)
Q = q × Nd × Dsmax (2)
It is. q is the elementary charge amount and Nd is the n-layer doping concentration. The charge amount in the n ⁻ layer 15 and the charge amount in the p layer are the same Q. Further, the separation layer 4a has a much higher concentration than the n ⁻ layer 15 and the depletion layer end 19 extends exclusively in the direction of the n ⁻ layer 15. In the corner portion, the depletion layer end 19 near 45 ° of the corner, in particular, is easy to extend compared to the straight portion due to the shape effect. By the way, the space charge amount per unit length of the corner pn junction 19 is the same Q as that of the straight line portion. (Since the depletion layer hardly extends on the separation layer 4a side, the corner portion is almost straight when viewed on the separation layer 4a side.) Therefore, when the depletion layer width of the corner portion is Dcmax, The amount of space charge per unit length (along the pn junction 7) is

(Equation 3)
Q = q × Nd × π × [R ² − (R−Dcmax) ² ] / 2 × π × R (3)
It is. Therefore, the relationship between the difference Do between the depletion layer width Dcmax at the corner portion and the depletion layer width Dsmax at the straight portion is obtained from the equations (2) and (3):

(Equation 4)
Do = Dcmax−Dsmax = (Dcmax ² / 2R) (4)
This is expressed as Dsmax.

(Equation 5)
Do = R−Dsmax− (R ² −2R × Dsmax) ^0.5 (5)
It becomes.
In the corner portion, the depletion layer end 19 is close to the active portion end 6 by Do, and it is easy to punch through. Actually, Dsmax (or Dcmax) is longer than Equation (1) and Do is further increased due to a withstand voltage structure such as a guard ring or a p-floating ring. That is, the active part end 6 is further approached, and it is difficult to ensure the reverse breakdown voltage.
Therefore, if the width of the pressure-resistant structure 3 in the straight portion is designed to be large so as to have a punch-through margin (by taking a distance between the depletion layer end 19 and the active portion end 6), a margin for the corner portion is naturally created. The depletion layer end 19 at the corner portion can be prevented from approaching the active portion end 6. However, the area of the withstand voltage structure 3 is increased unnecessarily, and the chip area when the same characteristics (that is, the on-voltage) are to be obtained increases, and the chip cost increases.

Next, the cross-sectional structure of the separation layer 4 will be described.
FIG. 12 is a cross-sectional view of the separation layer. The half width of the opening of the mask 17 is W, the separation layer 4 (longitudinal) diffusion depth is Xj, the lateral diffusion depth (distance) is Yj, and the final silicon thickness after wafer back wrapping is t. Yj is in the range of 0.7 to 1.0 of Xj, but may be equal to Xj for safety side evaluation. As shown in FIG. 13, when Xj is equal to or less than t, the n ⁻ layer 15 is exposed to the chip side surface 20 after dicing, and a leakage current is large when a reverse bias is applied, so that a reverse breakdown voltage cannot be obtained. Further, as shown in FIG. 14, when the opening width 2W is smaller than the diffusion depth Xj, impurities are diffused from the narrow opening 5, so that when heat treatment is performed for a long time to obtain sufficient Xj, the silicon crystal defect occurs or a large number, resulting in problems such as rough silicon surfaces. For this reason, it becomes difficult to obtain a sufficiently deep Xj, and Xj becomes t or less, and as described above, the n ⁻ layer 15 is exposed to the chip side surface 20, and a leakage current is large when a reverse bias is applied, The reverse breakdown voltage cannot be obtained. Further, as shown in FIG. 15, the separation layer width appearing on the back surface is approximately equal to W under the condition that the diffusion depth Xj is attached to the very back surface of the chip (corresponding to the wafer surface 18 after grinding) (ie, Xj = t). However, if the size of the chipping 16 (wafer chipping) generated during dicing exceeds W, the n ⁻ layer 15 is exposed to the chip side surface 20 at this portion, and a sufficient reverse breakdown voltage cannot be obtained.

As described above, in the separation layer structure of the conventional reverse blocking IGBT, the extension of the depletion layer end 19 at the corner increases, making it difficult to obtain a sufficient reverse breakdown voltage without increasing the chip size (chip area). Become. Further, the separation layer 4 is partially lost due to the chipping 16 generated at the time of dicing, and the n ⁻ layer 15 is exposed at the chip side surface 20, and the leakage current at this portion increases, thereby obtaining a sufficient reverse breakdown voltage. It can be difficult.
An object of the present invention is to solve the above-described problems and provide a semiconductor device having an isolation layer structure capable of obtaining a sufficient reverse breakdown voltage without increasing the chip size.

In order to achieve the above object, the semiconductor device is a reverse blocking semiconductor device, a breakdown voltage structure region is formed in a low concentration drift region, and an isolation layer having a conductivity type opposite to the drift region is an outer peripheral side surface of the drift region. In the semiconductor device in which the depletion layer extends from the pn junction on the outer peripheral side surface of the isolation layer toward the drift region, the outer peripheral end of the breakdown voltage structure region coincides with the inner peripheral end of the isolation layer, and the breakdown voltage structure region inner and peripheral edge and the outer edge has a straight portion and a corner portion opposing a width that faces the corner portion than the width of opposing the straight portions widely, and the corner portion of the pressure-resistant structure area circle It is an arc, and the distance obtained by shifting the center of curvature of the outer end of the corner portion from the position of the center of curvature of the inner end of the corner portion is L (unit: μm), and from the outer end of the corner portion of the pressure-resistant structure region Towards the inner edge The maximum extension amount of the extending depletion layer is Dcmax (unit: μm), the width of the straight portion of the breakdown voltage structure region is Wos (unit: μm), and the radius of curvature of the inner end of the corner portion of the breakdown voltage structure region is Ro (unit: μm)

(Equation 6)
^{0.3L ≧ Dcmax 2/2 (Wos} + Ro)
To satisfy the requirements.
Further, the vertical diffusion depth of the separation layer formed by diffusing impurities from the opening of the separation layer formation mask formed on one main surface of the semiconductor substrate is Xj, and the final thickness of the semiconductor substrate is t. When

(Equation 7)
Xj ≧ t
The configuration is as follows.
When the width of one side of the opening is W and the maximum value of chipping is Lo,

(Equation 8)
Xj ≧ t
Meet

(Equation 9)
Xj (Xj−t) ^0.5 + W ≧ Lo
To satisfy the requirements.
The maximum chipping value Lo is set as the maximum distance from the center line of the opening to the tip of the chipping.
With the above configuration, in the reverse blocking IGBT having the separation layer according to the present invention, punch-through to the active portion of the depletion layer does not easily occur at the corner portion during reverse bias, and a sufficient reverse breakdown voltage can be obtained. Even if chipping occurs during dicing, the separation layer width is sufficiently large and the n ⁻ layer is not exposed on the side surface of the chip, so that a sufficient reverse breakdown voltage can be ensured.

  According to the present invention, a sufficient reverse breakdown voltage can be ensured in the reverse blocking device by moving the center of curvature of the corner portion so that the separation layer width of the corner portion is wider than the separation layer width of the straight portion.

The best mode for carrying out the present invention will be described.
FIG. 1 is a plan view of an essential part showing a shape of a separation layer of a chip corner portion according to the present invention. This corresponds to FIG. 10 described above. In addition, the same code | symbol was attached | subjected to the same site | part as FIG.
The curvature center position 10 of the corner portion of the separation layer pn junction 7 is set to the outer side (chip outer peripheral direction) than the curvature center position 9 of the active portion end 6. By doing in this way, the distance from the separation layer pn junction 7 to the active part end 6 in the corner part (arc-drawing part) becomes larger than that in the straight part. Note that the separation layer pn junction 7 coincides with the outer peripheral end of the breakdown voltage structure 3, and the active portion end 6 coincides with the inner peripheral end of the breakdown voltage structure 3.
As described in the background section above, the depletion layer is easily extended by the shape effect in the corner portion, and the depletion layer width in the corner portion is larger than the depletion layer width in the straight portion.

(Equation 10)
Do = (Dcmax ² / 2R)
Only big. If the width of the pressure-resistant structure in the straight portion is Wos, as described above, R = Wos + Ro. The depletion layer width is a width from the separation layer pn junction 7.
However, if the amount of movement L of the separation layer pn junction 7 to the outside of the center of curvature 10 is designed to be sufficiently large, even if the depletion layer is easily extended due to the shape effect at the corner, the punch-through margin at the corner is It becomes larger than the margin of the straight line portion, and punch-through at the corner portion is prevented. This will be described in more detail.
FIG. 2 shows how much the punch-through margin (distance between the depletion layer end and the active portion end) is improved when the center of curvature position 10 of the separation layer pn junction 7 is moved by L (in the direction of 45 degrees in the corner). It is a figure for demonstrating what to do. In the figure, reference numeral 13 denotes a separation layer pn junction before movement, and reference numeral 14 denotes an opening end before movement.

  The radius of curvature when the curvature center position 10 of the separation layer pn junction 7 is not moved (when the curvature center position 9 of the active portion end 6 is set) is R, and the curvature radius after the curvature center position 10 is moved by L is r. Then, the improvement value L1 of the punch through margin is

(Equation 11)
L1 = r + LR
It is. Where R is

(Equation 12)
R = r + (L / 2 ^0.5 )
Therefore, the punch-through margin improvement value L1 is

(Equation 13)
L1 = r + L− (r + (L / 2 ^0.5 )) = (1−1 / 2 ^0.5 ) L = 0.3L
It is.
Since the depletion layer extends by Do at the corner from the straight line, the center of curvature 10 is moved so as to eliminate this elongation, and the punch through margin at the corner is made larger than the punch through margin at the straight line. Can prevent punch-through at the corner.
Therefore, the punch-through margin improvement value L1 may be made larger than Do (difference in the depletion layer width between the corner portion and the straight portion). That is, if 0.3L> Do, punch-through at the corner can be avoided.

Thus, by selecting L so that 0.3L> Do is satisfied, the width of the pressure-resistant structure of the linear portion is not increased, that is, without increasing the chip size (chip area), The width Woc of the breakdown voltage structure can be increased, and a sufficient reverse breakdown voltage can be obtained.
Next, the design of the cross-sectional structure of the separation layer will be described.
FIG. 3 is a sectional view of a separation layer structure according to the present invention. By grinding the wafer 1 so that the final silicon thickness t is thinner than the separation layer diffusion depth Xj (longitudinal diffusion depth), the n ⁻ layer 15 is not exposed on the side surface of the chip when the wafer 1 is chipped. Thus, it is possible to suppress reverse leakage current from flowing through the side surface when a reverse bias is applied.
That is, by setting Xj> t, the n ⁻ layer 4 is not exposed on the side surface, and the reverse leakage current is suppressed when a reverse bias is applied.

Further, by making the opening width 2W (separation layer window width) larger than Xj, a sufficient Xj can be obtained by the boron diffusion heat treatment, and the bottom surface of the separation layer 4 immediately below the opening 5 becomes flat, and the dicing is performed. Even when there is chipping 16 (chips), the tip of the chipping 16 does not reach the n ⁻ layer 15 by making W larger than the maximum value Lo of chipping, and the reverse leakage current does not increase. Note that Lo is the distance from the center line 11 of the opening 5 to the tip A of the maximum chipping.
That is, when Xj> t and 2W> Xj, by setting W> Lo, the tipping tip A does not reach the n ⁻ layer 15 and the reverse leakage current does not increase.
Next, the above will be described in detail using mathematical expressions. Considering the coordinate system as shown in FIG. 4, the vertical position Y of the separation layer pn junction 7 can be approximated by the following equation.

(Equation 14)
Y = X ² / Xj (6)
Here, Y is a vertical coordinate axis, and X is a horizontal coordinate axis. In this approximate expression, Yj = Xj, where Yj is the lateral diffusion depth on the surface. That is, the vertical diffusion depth Xj and the horizontal diffusion depth Yj on the surface are the same.
Yjt is obtained by substituting Yjt for the lateral layer junction distance X in the final silicon thickness t and substituting (Xj-t) for Y in equation (6).

(Equation 15)
Yjt = (Xj (Xj−t)) ^0.5 (7)
It becomes. Therefore, so that Lo <Yjt + W, that is,

(Equation 16)
Lo <(Xj (Xj−t)) ^0.5 + W (8)
Thus, when the final silicon thickness is t, by determining Lo, Xj, and W, the n ⁻ layer 15 is not exposed to the side surface of the chip even when there is chipping 16, and the reverse is sufficient. A breakdown voltage can be obtained. Lo is determined by the cutting characteristics of the dicing saw (blade width, material, degree of wear, etc. of the dicing saw).
Further, by satisfying the expression (8), even when the tip D of the maximum chipping 16 shown in FIG. 5 is located on the back surface (corresponding to the reference numeral 18) of the semiconductor substrate, the tip D of the chipping is in the separation layer 4. The n ⁻ layer 15 is not exposed to the side surface of the chip without contacting the separation layer pn junction position E on the back surface.

  Next, an embodiment of the present invention manufactured based on the above design will be described.

6A and 6B are configuration diagrams of a semiconductor device according to an embodiment of the present invention, in which FIG. 6A is a plan view of relevant parts and FIG. 6B is a cross-sectional view of relevant parts. The semiconductor device is a reverse blocking IGBT. FIG. 4A is a plan view showing a state of the wafer before being formed into chips, and FIG. 4B is a cross-sectional view of the wafer before dicing. The end surface of the chip after dicing is indicated by reference numeral 20 in FIG.
A case where the rated breakdown voltage is 600 V and the wafer specific resistance is 28 Ωcm will be described.
In FIG. 6A, the radius of curvature R of the separation layer pn junction 7 when the center is not moved is 800 μm, the half width W of the opening of the mask is 200 μm, the lateral junction depth Yj is 120 μm, and the active portion end 6 The curvature radius Ro is 100 μm.
The depletion layer width at the time of reverse breakdown (Vce = −700 V) is 70 μm from Eq. (1) (Emax = 2 × 10 ⁵ V / cm). However, this is a value when there is no guard ring or the like (55 and 54 in FIG. 9), and in a simulation of an actual structure with a guard ring or the like, Dsmax = 200 μm and Dcmax is 234 μm.

Therefore, Do is 34 μm from the formula (5), and 0.3L> Do can be satisfied by setting L to 110 μm or more (in the example, 200 μm). The curvature radius r of the separation layer pn junction 7 after moving the curvature center position 10 is 659 μm, and Ro is 100 μm. The distances from the depletion layer end 19 to the curvature center position 9 are 600 μm for A1 (straight line portion) and 625 μm for A2 (corner portion).
In the corner portion, the depletion layer end 7 extends by 34 μm (= Do) compared to the straight portion. However, by setting the moving distance L of the curvature center position 10 to 200 μm, the punch-through margin improvement value L1 (A2-A1) ) Can be improved by 60 μm, and as a result, the neutral region (region where the depletion layer does not spread) in the corner portion is 26 μm (L1-Do = 60 μm−34 μm) compared to the neutral region in the straight portion. Become wider. By moving the curvature center position 10 in this way, it is possible to prevent the corner portion from being punched through before the straight portion without increasing the chip size.

In FIG. 6B, when the vertical junction depth Xj of the separation layer is 120 μm and the final Si thickness t is 90 μm, the maximum chipping value Lo during dicing is usually about 40 μm, so W is Lo. The n ⁻ layer 15 is not exposed by chipping.
Further, when Xj is 120 μm and t is 90 μm as described above, even if the maximum chipping value Lo during dicing is 100 μm, W is set to 40 μm or more, thereby satisfying the formula (8), and n due to occurrence of chipping. ^- exposure of the layer 15 will not occur in theory.
Next, a bidirectional switch element manufactured using the semiconductor device of the above embodiment will be described.
7A and 7B are configuration diagrams of the bidirectional switch element. FIG. 7A is a cross-sectional view of the main part, and FIG. 7B is a circuit diagram. The first and second reverse blocking IGBTs 41 and 42 used in the bidirectional switch element employ the separation layer structure shown in FIGS.

The collector electrodes 16a and 16b of the first and second reverse blocking IGBTs 41 and 42 are fixed to the first and second conductive patterns 44 and 45 formed on the insulating substrate 43, respectively, and the emitter electrode 10a of the first reverse blocking IGBT 41 is secured. And the second conductive pattern 45 to which the collector electrode 16b of the second reverse blocking IGBT 42 is fixed are connected by a bonding wire 46a, and the emitter electrode 10b of the second reverse blocking IGBT 42 and the collector electrode of the first reverse blocking IGBT 41 The first conductive pattern 44 to which the 16a is fixed is connected by a bonding wire 46b, and connected to the emitter electrodes 10a and 10b of the first and second reverse blocking IGBTs 41 and 42 and the first and second main terminals T1 and T2. The gate pads 8a and 8b of the first and second reverse blocking IGBTs 41 and 42 are connected to the first and second gate terminals G1 and G2.
This bidirectional switch element has a structure in which reverse blocking IGBTs 41 and 42 of the present invention are connected in antiparallel as shown in the circuit diagram of FIG.

Further, as shown in the circuit diagram of FIG. 8, the gate drive circuits 47a and 47b can be connected to the reverse blocking IGBTs 41 and 42 of the present invention to form a bidirectional switch circuit. In the circuits shown in FIGS. 7 and 8, the reverse blocking diode required in the conventional bidirectional switch circuit is not required, and electrical loss (forward voltage drop, reverse recovery loss, etc.) can be reduced.
Therefore, by using the reverse blocking IGBT of the present invention, it is possible to provide a matrix converter with low loss while sufficiently reducing the leakage current at the time of reverse bias.

The principal part top view which shows the separation layer shape of the chip | tip corner part by this invention Explains how much the punch-through margin (distance between the depletion layer end and the active portion end) is improved when the center of curvature 10 of the separation layer pn junction 7 is moved by L (in the direction of 45 degrees in the corner). Illustration to do Separation layer structure sectional view according to the present invention The figure which shows the coordinate system showing isolation | separation pn junction The figure when the tip A of the largest chipping 16 is located on the back surface of the semiconductor substrate (corresponding to reference numeral 18) BRIEF DESCRIPTION OF THE DRAWINGS It is a block diagram of the semiconductor device of one Example of this invention, (a) is a principal part top view, (b) is principal part sectional drawing. It is a block diagram of a bidirectional switch element, (a) is a fragmentary sectional view, (b) is a circuit diagram Circuit diagram of bidirectional switch element It is a block diagram of the conventional reverse blocking IGBT, (a) is a principal part top view, (b) is principal part sectional drawing cut | disconnected by the XX line of (a). The top view which shows the shape of the corner part vicinity of the separation layer structure of the conventional reverse block IGBT Diagram showing depletion layer elongation during reverse bias breakdown Cross section of separation layer Cross-sectional view of separation layer where Xj is t or less Sectional view of the separation layer when the opening width 2W is smaller than the diffusion depth Xj Cross-sectional view of the separation layer under the condition that the diffusion depth Xj is at the very back of the chip (ie, Xj = t)

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Wafer 2 Active part 3 Pressure | voltage resistant structure 4 Separation layer (before cutting)
4a Separation layer (after cutting)
5 Opening 6 Active part edge (main joint edge)
7 Separation layer pn junction 8 Open end 8a, 8b Gate pad 9 Curvature center position before movement 10 Curvature center position after movement 10a, 10b First and second emitter electrodes 11 Dicing line center line (opening center line)
12 Chip edge 13 Separation layer pn junction before movement 14 Opening edge before movement 15 n ⁻ layer 16 Chipping 16a, 16b First and second collector electrodes 17 Mask 18 Wafer surface after grinding (back surface)
19 End of depletion layer 20 End face after cutting 41, 42 First and second reverse blocking IGBT
43 Insulating substrate 44, 45 First and second conductive patterns 46a, 46b Bonding wires 47a, 47b Gate drive circuit W Half of opening width Xj Longitudinal diffusion depth Yj Lateral diffusion depth (distance)
R Curvature radius before movement r Curvature radius after movement L Movement distance Ro Curvature radius of active part end Width of Wos pressure-resistant structure (straight line part)
Woc pressure resistant structure width (corner)
t Final wafer thickness

Claims (4)

The semiconductor device is a reverse blocking semiconductor device, in which a breakdown voltage structure region is formed in a low concentration drift region, a separation layer having a conductivity type opposite to that of the drift region is formed on the outer peripheral side surface of the drift region, and the depletion layer is separated from this In the semiconductor device extending from the pn junction on the outer peripheral side surface of the layer toward the drift region, the outer peripheral end of the breakdown voltage structure region coincides with the inner peripheral end of the isolation layer, and the inner peripheral end and the outer peripheral end of the breakdown voltage structural region are and a straight portion facing the corner portion, the width of opposing the corner portion than the width of opposing the straight portions widely, and the corner portion of the breakdown withstanding region is arcuate, outer of the corner portion The distance of the center of curvature of the end from the position of the center of curvature of the inner end of the corner portion is L (unit: μm), and the depletion layer extends from the outer end of the corner portion of the pressure-resistant structure region toward the inner end. Maximum elongation cmax (in [mu] m), width Wos of the linear portion of the breakdown withstanding region (unit [mu] m), when the inner end curvature radius of the corner portion of the breakdown withstanding region was Ro (in [mu] m),
(Equation 1)
^{0.3L ≧ Dcmax 2/2 (Wos} + Ro)
A semiconductor device characterized by satisfying When the vertical diffusion depth of the separation layer formed by diffusing impurities from the opening of the separation layer formation mask formed on one main surface of the semiconductor substrate is Xj and the final thickness of the semiconductor substrate is t (Equation 2)
Xj ≧ t
The semiconductor device according to claim 1, wherein: When the width of the opening is 2 W and the maximum value of chipping is Lo,
(Equation 3)
[Xj (Xj−t)] ^0.5 + W ≧ Lo
The semiconductor device according to claim 2 , wherein: 4. The semiconductor device according to claim 3 , wherein the maximum chipping value Lo is a maximum distance from a center line of the opening to a tip of the chipping.

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