JPH02298073A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To acquire a high breakdown strength and to realize a large diameter of a substrate by making a P-N junction side on a first semiconductor substrate flat at a peripheral section thereof forming a mesa structure with a specified incline and by coating the incline with an insulator layer which consists of a thermal oxidation film. CONSTITUTION:At first, a mirror surface 1a of a first semiconductor substrate 1 of high resistance N<->-type is provided with a mesa groove 3 which is formed crosswise having an incline 3a and opens to a substrate edge. The semiconductor substrate and a low resistance second semiconductor substrate 2 of N<+>-type are fully cleaned to remove a spontaneous oxide film thereon. Then, an amount of water on the surface is controlled, and mirrors 1a, 2a are tightly bonded each other and dried. The substrates 1, 2 are directly bonded at a bonding side through heat treatment to acquire a completely integrated substrate 5. The substrate 5 is thermally treated to protect the incline 3a of the mesa groove 3 by an oxide film 6. The substrate surface 1b is lap-polished, a P-N junction surface 7 and a P-layer are formed, a mask is applied, an N<+>-layer is formed, and an aluminum wiring is applied to a specified position of the element surface. Dicing is carried out at a position of the mesa groove 3.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a semiconductor device and a method for manufacturing the same, which enable high breakdown voltage and a large diameter substrate.

[Conventional technology]

In the Brehner type semiconductor device shown in FIG.
When a reverse voltage is applied to the junction, electric field concentration occurs at the curved portion rather than at the flat portion. Therefore, the avalanche breakdown voltage at the curved part is lower, so devices that require a high withstand voltage of 600 µm or more are conventionally constructed with a mesa structure (see Figure 5 (a).
), (b)) or guard ring structure (6th
A pressure-resistant structure (see figure) is adopted.

The mesa structure shown in Figure 5 is created by mechanically polishing or etching the sides of the device diagonally to make the PN junction surface flat.
Local electric field concentration as described above does not occur, and a high withstand voltage can be obtained. However, when considering the electric field at the end of the PN junction, the inverted mesa structure as shown in FIG. 5(b) is superior. That is, according to the structure shown in FIG. 5(1)), the electric field at the end of the PN junction is weakened, making it easier to obtain a higher breakdown voltage.

Conventionally, in the case of the inverted mesa structure shown in FIG. 5(b),
The step of forming the side surfaces of the element obliquely is a post-process, and the amount of mesa etching increases as the substrate becomes thicker due to the structure. Therefore, when attempting to increase the diameter of the substrate in order to increase the degree of integration of elements, it is necessary to increase the thickness of the substrate, and as a result, there is a problem in that it becomes difficult to increase the diameter of the substrate.

On the other hand, in the case of the guard ring structure shown in FIG. 6, the surface of the PN junction end is protected by an oxide film, and the process is simple. However, the higher the breakdown voltage is required, the more it is necessary to increase the number of guard rings to alleviate the electric field at the curved portion of the PN junction, and the longer the depletion layer needs to be extended in the horizontal direction. Therefore, there is a problem that the area required for this increases and the element size increases. Furthermore, since the curved portion cannot be eliminated, there is a problem that the withstand voltage is lower than that of flat bonding.

[Problem to be solved by the invention]

The present invention has been made in view of the various problems mentioned above.
It is an object of the present invention to provide a semiconductor device and a method for manufacturing the same that can easily achieve a high breakdown voltage and increase the diameter of a substrate.

[Means for Solving the Problems] In order to achieve the above object, the invention of a semiconductor device according to claim 1 has one surface and the other surface, and a semiconductor layer with a predetermined concentration on the other surface side. with PN inside
a first semiconductor substrate forming a bonding surface; and a second semiconductor bonded to the other surface of the first semiconductor substrate and having a concentration higher than that of a semiconductor layer existing on the other surface of the first semiconductor substrate. a substrate; and a bonding layer formed in the first semiconductor substrate due to a concentration difference between the semiconductor layer and the second semiconductor substrate by bonding the first semiconductor substrate and the second semiconductor substrate, In the first semiconductor substrate, the P
A predetermined inclined side surface is formed passing through the N junction surface, and the predetermined inclined side surface has a thickness that increases as it approaches one surface of the first semiconductor substrate at a peripheral portion of the P N junction surface. It is characterized by being sloped so that it becomes thinner.

Furthermore, in addition to the above configuration, the semiconductor device according to the third aspect of the present invention employs a technical means of covering the predetermined inclined side surface with an insulating layer made of a thermal oxide film.

Further, in the invention of the method for manufacturing a semiconductor device according to claim 5, a first step of arranging a mesa groove having a predetermined inclined side surface opening on the mirror side of the mirror-polished first semiconductor substrate; and mirror polishing. a second step of directly bonding the mirror surface of the second semiconductor substrate and the mirror surface of the first semiconductor substrate to form a bonded substrate; and the mesa of the first semiconductor substrate formed on the bonded substrate. a third step of covering the inner surface of the space formed by the groove and the mirror surface of the second semiconductor substrate with an insulating layer; and in the first semiconductor substrate in the bonded substrate,
A fourth step of forming a PN junction surface having a peripheral edge portion on the inclined side surface, and manufacturing a semiconductor device is characterized in that the method includes manufacturing a semiconductor device.

[Action and effect]

In the invention according to claim 1, the PN junction surface formed on the first semiconductor substrate has a predetermined inclined side surface, which eliminates a curved portion at the peripheral edge and is made flat, and forms an inverted mesa structure, so that the PN junction surface has a high height. This has the excellent effect of providing a semiconductor device with a small area and a high breakdown voltage.

In the invention according to claim 3, since the inclined side surface is covered with an insulating layer made of a thermal oxide film, the peripheral edge of the PN junction surface is protected by the thermal oxide film, so that it does not deteriorate over time. This has the excellent effect of providing a semiconductor device that can obtain a stable high breakdown voltage with little change.

In the present invention according to claim 5, the semiconductor substrate necessary for obtaining a predetermined semiconductor device is formed by using a mirror surface of a first semiconductor substrate in which a mesa groove having a predetermined inclined side surface is formed in the first step; In a second step, the mirror surfaces of the two semiconductor substrates are directly bonded to form a bonded substrate, and in a third step, the inner surface of the space constituted by the mesa groove and the mirror surface of the second semiconductor substrate is coated with an insulating material layer. The fourth
Since the semiconductor device is manufactured by forming a PN junction surface having a peripheral edge on the inclined side surface covered with an insulating material layer in the step of step 1, the semiconductor device obtained by the manufacturing method of the present invention has a high withstand voltage. The periphery of the PN junction surface is protected by an insulator layer and has an inverted mesa-type breakdown voltage structure with sloped side surfaces, which has the excellent effect of providing a semiconductor device with a stable high breakdown voltage that does not change over time and has a small area. . Furthermore, even if the thickness of the second semiconductor substrate, which is the high concentration region, is increased, the depth of the mesa groove forming the inverted mesa structure does not change, which has the excellent effect of making it easy to increase the diameter of the substrate. be.

〔Example〕

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention shown in the drawings will be described.

FIG. 1 is a sectional view showing the manufacturing process of a semiconductor device according to an embodiment of the present invention. The manufacturing process will be explained by taking the NPN type high voltage bipolar transistor shown in FIG. 2 as an example.

First, as shown in FIG. 1(a), a mesa groove 3 having an inclined side surface 3a and opening at the edge of the substrate is formed on the mirror surface 1a of a high-resistance N-type first semiconductor substrate 1 by mechanical polishing or chemical etching. are formed in a cross direction (only one direction is shown in FIG. 1(a)). The first semiconductor substrate 1 and the low resistance N-type second degree semiconductor substrate 2 are thoroughly cleaned to remove the natural oxide film on the surface. For example, H! A thin oxide film of 15 Å or less is formed on the surfaces of these substrates using a solution of SOs: HtOz-3:1 to make them hydrophilic, and then washed with pure water. Next, the amount of moisture adsorbed on the surface of these substrates is controlled by dry nitrogen blowing or spin drying, and the difference between the mirror surfaces of the two substrates is
Place la and 2a in close contact as shown in Figure 1).

As a result, the two substrates 1 and 2 are bonded together by hydrogen bonds between the silanol substrate formed on the surface and the water molecules adsorbed on the surface. Furthermore, in order to remove excess moisture remaining on the adhesive surface 4, it is dried in a vacuum. At this time, the previously formed mesa groove 3 also serves as a channel for removing excess water from the bonding surface 4, improving the uniformity of bonding. Also, at this time,
In order to improve the adhesion of the substrate, a load of 30 g/cd or more may be applied. After this, the adhesive substrate l.

2 to 1 in an inert gas atmosphere such as nitrogen, argon, etc.
Heat treatment is performed at 100°C or higher for 1 hour or more.

As a result, a dehydration condensation reaction occurs on the adhesive surface 4,
Junction of silicon (St) and oxygen (0) (S-O-3i)
Oxygen is further diffused into the substrate, bonding between silicones (Si-3T) is formed, and the two substrates 1.2 are directly bonded and completely integrated (the code for this integrated substrate is (newly set as 5). However, the mesa groove 3 is hollow, and the forming bonding layer 4a is formed in the vicinity of the direct bonding surface 4 of the first semiconductor substrate 1. Next, as shown in FIG. 1(C), this integrated substrate 5 is dried, for example. Heat treatment is performed at 900"C or higher for 1 hour or more in an oxidizing atmosphere such as Ot, Hz, 02 mixed combustion gas to oxidize the inclined side surface 3a of the mesa groove 3 inside the substrate 5. As a result, the mesa groove The inclined side surface 3a of No. 3 is protected by the oxide film 6, but in order to further protect the inclined side surface 3a completely, the surface is coated with an insulating material such as a nitride film or silicate glass by, for example, a low pressure CVD method. Next, as shown in FIG. 1(d), the substrate surface 1b on the side where the P layer will be formed in the step of FIG. 1(e) to be described later is lap-polished. the first of
In Figure (e), the thickness is set so that the PN junction surface 7, which determines the withstand voltage of the element, reaches the mesa groove inclined side surface 3a, and the mesa groove 3 is not exposed to the substrate surface 1b. Furthermore, in the next step shown in FIG. 1(e), a PN junction surface 7 is formed on this substrate 5. In FIG. 1(e), the P layer is formed by diffusing an acceptor impurity such as boron.

Then, a mask is applied to form an emitter region in a predetermined region, a donor impurity such as phosphorus is diffused to form an N layer, and aluminum wiring is further applied to a predetermined position on the element surface (see Fig. 1 (f). ), and as shown in FIG. 1 (9), by dicing at the mesa groove 3 position,
The NPN type high voltage bipolar transistor shown in FIG. 2 is manufactured.

Note that in the above embodiment, the oxide film and insulating film forming process on the side surface 3a of FIG. 1C shown in FIG. 1C was performed before the lapping process shown in FIG. The step may be performed at the time of forming the section, that is, at the time of the step shown in FIG. 1 [e].

The NPN type high breakdown voltage bipolar transistor shown in FIG. 2 manufactured in the above embodiment has an inverted mesa structure having an inclined side surface 3a protected by an oxide film 6. In Fig. 2, PN junction of base B1 collector C! j7 is flat and has an inverted mesa structure, so P
The electric field at the end of the N-junction surface 7 is weakened, making it possible to achieve a theoretically high breakdown voltage corresponding to the substrate concentration. Furthermore, in the conventional inverted mesa structure shown in FIG. 5(b), the step of forming the inclined side surface as described above is a later step, that is, when the electric scraping is completed and the dicing step is performed. Heat treatment cannot be applied to cover the sloped side surface with an oxide film, leaving the PN junction end exposed on the side surface. Although protective films such as glass are used to protect the side surfaces, There was a problem in that pressure resistance was likely to become unstable due to problems with adhesion. However, in the first embodiment of the semiconductor device according to the present invention shown in FIG. 2, a step of forming a protective film on the inclined side surface can be provided before element formation instead of in the final step. It can be formed from an oxide film, and therefore, it is possible to obtain a stable breakdown voltage with little surface leakage current caused by moisture absorption, etc., and little change over time.

Furthermore, since there is no curved part in the PN junction surface 7, there is no need to widen the depletion layer in the horizontal direction to alleviate the electric field as in the conventional guard ring structure, which is necessary to improve the breakdown voltage in regions other than the base-emitter region. It is unnecessary in the structure area, and therefore it is possible to reduce the area of the element. For example, 1500
In a V breakdown voltage device, the width of the guard ring region is approximately 500 μm, but in this embodiment, the etching region is approximately 200 μm. Note that due to the inverted mesa structure, there is a part where the mesa groove end enters inside the device and the area becomes smaller, but since the on-current mainly flows in the emitter region, at least if the mesa trench end is outside the emitter region, , there is no decrease in current supply ability. In addition, since the depth of the mesa groove is determined only by the thickness of the N-coder layer 8, which determines the withstand voltage, even if the substrate becomes thicker due to a larger diameter substrate, it will not work like the conventional inverted mesa structure. The mesa groove depth, that is, the mesa etching amount does not increase.

In addition, although the manufacturing process of the NPN type bipolar transistor was shown as one example above, the conductivity type is P.

N may be reversed, and the present invention can also be implemented with element structures such as diodes, MOS transistors, and thyristors.

Next, FIG. 3 shows a conductive modulation type M manufactured according to the present invention.
A cross-sectional view of an O3FET is shown.

In FIG. 3, there is a curved part on the PN junction surface 17, but normally the distance between adjacent curved parts is set to such a distance that the depletion layer in the off state is connected and a breakdown voltage close to that of a flat junction is obtained. As can be seen from Figure 3, P in the peripheral area of the element
Since there is no curved portion at the end of the N junction, a high breakdown voltage can be achieved similar to the NPN type high breakdown voltage bipolar I-transistor shown in FIG.

Note that in the semiconductor devices shown in FIGS. 2 and 3 described above, the mesa groove having a predetermined inclined side surface is constituted by a V-shaped groove; At the periphery of the PN junction formed on the upper side in FIG. Any type of material may be used as long as it is inclined so that the material becomes thinner, for example, it has a predetermined radius of curvature (it may also be an intermediate material).

In addition, in the inverted mesa structure, the electric field relaxation at the periphery of the PN junction surface is as described above.
Although the electric field at the PN-junction between the collectors is the highest, the lateral cross-sectional area of the semiconductor device increases from the collector to the base at the periphery of the PN-junction, so the inside of the semiconductor device Electric field concentration is less likely to occur than at the PN-junction, and as a result, the electric field is inevitably relaxed. However, as the cross-sectional area on the collector side becomes smaller, the electric field at the interface between the high-resistance collector and the low-resistance collector, that is, the N--N interface, concentrates. Therefore, depending on the angle of the inverted mesa, breakdown may occur at the N--N'' interface before the inside of the semiconductor device.

In order to consider the dependence of the breakdown voltage on the angle of the inclined side surface, the inventors of the present invention set out the method shown in FIG.

The electric field strength at each site B and C was calculated by simulation. The simulation results are shown in FIG.

In Fig. 8, curves A, B, and C represent portions A, B, and C, respectively.
This is the angle-dependent characteristic of breakdown voltage at . Portion A is a PN-junction inside the semiconductor device, and the angle dependence characteristic of the breakdown voltage at portion A takes a constant value regardless of the inverse mesa angle θ, as shown by curve A in FIG. On the other hand, P
At part B of the N-junction end, as shown in curve B in Figure 8, the reverse mesa angle is one side (that is, mesa structure), and part A is
The electric field becomes higher, indicating that this part breaks down before part A.

Further, when the reverse mesa angle is on the positive side, the electric field becomes smaller as the angle increases. Furthermore, for site C, the electric field increases as the reverse mesa angle increases on the + side, and when the reverse mesa angle becomes 45 degrees or more, it becomes higher than site A, indicating that it breaks down before site A. Therefore,
The optimal reverse mesa angle is 0 to 45 degrees.

By setting the reverse mesa angle to 0 to 45 degrees, it is possible to ensure that portions B and C break down before portion A in Fig. 7 without any special adjustment of the impurity concentration and thickness of N-15. can be prevented.

[Brief explanation of the drawing]

FIG. 1 is a process diagram of each manufacturing process showing an example of the manufacturing method according to the present invention, FIG. 2 is a cross-sectional view of an NPN type high voltage bipolar transistor manufactured by the steps shown in FIG. 1, and FIG. A cross-sectional view of a conductivity modulation type MO3FET showing a second embodiment of the semiconductor device according to the present invention, FIG. 4 is a cross-sectional structural view of a planar semiconductor device 1, and FIG. 6 is a sectional view of a guard ring type semiconductor device, FIG. 7 is a sectional view of an inverted mesa type semiconductor device showing a simulation part, and FIG. 8 is a diagram of angle dependence characteristics of electric field strength based on simulation.1. ...First semiconductor substrate 12...Second semiconductor substrate, 1
a, 2a... mirror surface, 3... mesa groove, 3a... inclined side surface. 4... Direct bonding surface, 4a... Forming bonding layer, 5...
Bonded substrate, 6... Oxide film, 7... PN junction surface, 8.
...High resistance collector layer, 13a...Slanted side surface, 14.
・Directly bonded surface. 14a... Forming bonding layer, 16... Oxide film, 17...
・PN junction surface. Representative Patent Attorney Takashi Okabe (and 1 other person) Figure 1 Figure 4 (a) (b) Figure 5 Figure 6

Claims (7)

[Claims] (1) A first semiconductor substrate having one surface and another surface and having a semiconductor layer of a predetermined concentration on the other surface side to form a PN junction surface therein; and the other side of the first semiconductor substrate. a second semiconductor substrate that is bonded to a surface of the semiconductor substrate and has a concentration higher than that of a semiconductor layer existing on the other surface of the first semiconductor substrate; a bonding layer formed in the first semiconductor substrate due to a concentration difference between the semiconductor layer and the second semiconductor substrate;
A predetermined inclined side surface is formed passing through the N junction surface, and the predetermined inclined side surface has a thickness that increases as it approaches one surface of the first semiconductor substrate at a peripheral portion of the P N junction surface. 1. A semiconductor device characterized in that the semiconductor device is tilted so that the thickness becomes thinner. (2) The semiconductor device according to claim 1, wherein the predetermined inclined side surface is covered with an insulating layer. (3) The semiconductor device according to claim 2, wherein the insulating layer covering the inclined side surface is a thermal oxide film. (4) The semiconductor device according to claim 2, wherein the insulating layer covering the inclined side surface is a multilayer film including a thermal oxide film and another insulating material. (5) a first step of arranging a mesa groove having a predetermined inclined side surface opening on the mirror side of the mirror-polished first semiconductor substrate; a mirror-polished second semiconductor substrate; a second step of directly bonding the mirror surface of the semiconductor substrate to form a bonded substrate; and forming the mesa groove of the first semiconductor substrate and the mirror surface of the second semiconductor substrate formed in the bonded substrate. a third step of coating the inner surface of the space to be formed with an insulating layer; and in the first semiconductor substrate in the bonded substrate,
A method for manufacturing a semiconductor device, comprising: forming a PN junction surface having a peripheral edge on the inclined side surface; and manufacturing a semiconductor device. (6) The semiconductor device according to claim 5, wherein the third step is a step of heat-treating the bonded substrate to cover the inner surface of the space formed in the bonded substrate with a thermal oxide film. manufacturing method. (7) The semiconductor device according to claim 5 or 6, further comprising a fifth step of dicing the bonded substrate along the mesa groove to separate it into chips after the fourth step. manufacturing method.