KR100505561B1 - Manufacturing method of high breakdown voltage transistor - Google Patents
Manufacturing method of high breakdown voltage transistor Download PDFInfo
- Publication number
- KR100505561B1 KR100505561B1 KR1019980002406A KR19980002406A KR100505561B1 KR 100505561 B1 KR100505561 B1 KR 100505561B1 KR 1019980002406 A KR1019980002406 A KR 1019980002406A KR 19980002406 A KR19980002406 A KR 19980002406A KR 100505561 B1 KR100505561 B1 KR 100505561B1
- Authority
- KR
- South Korea
- Prior art keywords
- forming
- mesa portion
- trench
- manufacturing
- semiconductor substrate
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 21
- 230000015556 catabolic process Effects 0.000 title claims abstract description 16
- 238000000034 method Methods 0.000 claims abstract description 39
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 239000004065 semiconductor Substances 0.000 claims abstract description 21
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 17
- 230000001681 protective effect Effects 0.000 claims abstract description 12
- 229920005591 polysilicon Polymers 0.000 claims abstract description 8
- 238000001020 plasma etching Methods 0.000 claims abstract description 6
- 239000011521 glass Substances 0.000 description 18
- 239000000843 powder Substances 0.000 description 9
- 239000012535 impurity Substances 0.000 description 6
- 238000005245 sintering Methods 0.000 description 6
- 238000005520 cutting process Methods 0.000 description 4
- 238000004070 electrodeposition Methods 0.000 description 3
- 239000002245 particle Substances 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000001962 electrophoresis Methods 0.000 description 1
- 239000003344 environmental pollutant Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 231100000719 pollutant Toxicity 0.000 description 1
- 239000011148 porous material Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000001179 sorption measurement Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66363—Thyristors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3215—Doping the layers
- H01L21/32155—Doping polycristalline - or amorphous silicon layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/87—Thyristor diodes, e.g. Shockley diodes, break-over diodes
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Plasma & Fusion (AREA)
- Bipolar Transistors (AREA)
Abstract
본 발명은 반도체 장치의 제조방법에 관한 것으로, 특히 메사 공정을 이용한 고내압 트랜지스터 제조방법에 관한 것이다. 트렌치 메사부를 가드링 형성을 위한 영역의 반도체 기판에 반응성 이온 식각방식으로 형성한다. 트렌치 메사부의 내벽에 보호막을 형성한다. 그 내벽에 보호막이 형성되어 있는 트렌치 메사부 내부를 다결정실리콘으로 채운다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a high breakdown voltage transistor using a mesa process. The trench mesa portion is formed on the semiconductor substrate in the region for forming the guard ring by reactive ion etching. A protective film is formed on the inner wall of the trench mesa portion. The inside of the trench mesa portion having the protective film formed on the inner wall thereof is filled with polysilicon.
Description
본 발명은 반도체 장치의 제조방법에 관한 것으로, 특히 메사 공정을 이용한 고내압 트랜지스터 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a high breakdown voltage transistor using a mesa process.
고내압 트랜지스터(high voltage transistor)를 제조하는 방법은 일반적으로 플레너(planer) 공정과 메사(MESA) 공정으로 구분되어 진다. 메사 공정은 베이스 마스크(base mask)를 쓰지 않아도 되므로 사진 공정을 1스텝 줄일 수 있고, 플래너 구조에 비해 BVCEO 전압 효율이 좋아 에피텍셜층의 저항과 두께를 줄일 수 있어 소자의 Vce(sat) 값을 줄일 수 있으며, 스위칭(switching) 특성 향상과 SOA 영역을 확장시킬 수 있다는 장점이 있다. 또한, 플래너 구조보다 적정내압을 얻기위한 에지 터미네이션(edge termination) 처리부의 길이를 작게 가져갈 수 있으므로 칩 크기를 줄일 수 있다.The method of manufacturing a high voltage transistor is generally divided into a planer process and a mesa process. The mesa process eliminates the need for a base mask, which reduces the photo process by one step, and the BV CEO voltage efficiency is better than the planar structure, which reduces the resistance and thickness of the epitaxial layer. It has the advantage of reducing the power supply, improving the switching characteristics, and extending the SOA area. In addition, since the length of the edge termination processing unit for obtaining the proper breakdown voltage can be made smaller than the planar structure, the chip size can be reduced.
도 1은 종래 일방법에 의한 메사 공정을 이용한 고내압 트랜지스터 제조방법을 설명하기 위해 도시한 단면도이다.1 is a cross-sectional view illustrating a method of manufacturing a high breakdown voltage transistor using a mesa process according to the related art.
N+ 반도체 기판(10) 상에 N- 에피텍셜층(12)을 형성하고, 그 상부에 P- 베이스층(14)과 N+ 에미터층(16)을 형성한 후, 가드링이 형성될 영역의 반도체 기판을 블레드(blade)로 하프 컷팅(half cutting)하여 컷팅부(18)을 형성한다. 이후, 노출된 베이스층(14)와 에미터층(16)의 접합부(A)를 보호하기 위해 글래스 파우더(glass powder)를 전기영동법으로 전착시킨 후 소결공정을 통하여 글래스 보호막(20)을 상기 컷팅부(18) 내에 형성한다.After the N- epitaxial layer 12 is formed on the N + semiconductor substrate 10, and the P- base layer 14 and the N + emitter layer 16 are formed thereon, the semiconductor of the region where the guard ring is to be formed. The cutting part 18 is formed by half cutting a substrate with a blade. Subsequently, in order to protect the junction A between the exposed base layer 14 and the emitter layer 16, glass powder is electrodeposited by electrophoresis and then the glass protective film 20 is cut through the sintering process. It forms in (18).
이때, 상기 하프 컷팅 시 컷팅부(18)에 미세 균열이 발생하지 않도록 주의해야 하고, 노출된 베이스층(14)과 에미터층(16)의 접합부(A)를 보호하기 위한 글래스 보호막(20)을 형성하기 위해 글래스 파우더를 전착시킨 후 소결공정을 행할 때 글래스 파우더로 사용되는 PbO, ZnO 계열의 수 ㎛크기의 금속산화물이 타 공정진행시 파티클(particle) 및 금속오염원으로 작용되기 때문에 별도의 전착 룸(room)이 마련되어야 하며, 글래스 전용 소결 퍼니스(furnace)가 구비되어야 하므로 클린 룸(clean room) 설비와 퍼니스 및 전착장비에 대한 투자가 있어야 한다.At this time, care should be taken not to cause micro cracks in the cutting portion 18 during the half-cutting, and the glass protective film 20 for protecting the exposed portion A of the base layer 14 and the emitter layer 16 is exposed. Electrodeposited glass powder is formed in a separate electrodeposition room because PbO and ZnO-based metal oxides of several μm in size are used as particles and metal pollutants during other processes. A room must be provided and a dedicated glass furnace must be provided, so there must be an investment in clean room equipment, furnaces and electrodeposition equipment.
또한, 글래스 소결시 글래스와 반도체 기판(실리콘)의 열팽창계수 차이에 의하여 글래스와 반도체 기판 사이에 응력이 발생되어 웨이퍼가 휘어지거나(wafer bending) 파손되는 경우가 발생한다. 더하여, 글래스 소결시 발생하는 기공(24)이 소자도통시 열에 의한 부피 팽창이 일어나 소자파괴를 유도한다.In addition, when the glass is sintered, a stress is generated between the glass and the semiconductor substrate due to a difference in the coefficient of thermal expansion of the glass and the semiconductor substrate (silicon), thereby causing the wafer to bend or break. In addition, the pores 24 generated during the sintering of the glass may cause volume breakdown due to heat during device conduction, leading to device destruction.
도 2는 종래 다른 방법에 의한 메사 공정을 이용한 고내압 트랜지스터 제조방법을 설명하기 위해 도시한 단면도로, 반도체 기판을 습식 식각하여 메사부를 제조한 경우를 도시한다. 도 2에 있어서, 도면부호 "26"은 메사부를 나타내며, 상기 도 1에서 설명한 도면부호와 동일한 도면부호는 동일 부재를 의미한다.FIG. 2 is a cross-sectional view illustrating a method of manufacturing a high breakdown voltage transistor using a mesa process according to another conventional method, and illustrates a case where a mesa portion is manufactured by wet etching a semiconductor substrate. In Fig. 2, reference numeral 26 denotes a mesa portion, and the same reference numerals as those described in Fig. 1 mean the same members.
본 발명의 목적은 글래스 파우더 전착과 소결 공정이 필요없고 메사폭을 줄일 수 있는 고내압 트랜지스터 제조방법을 제공하는데 있다.SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a high breakdown voltage transistor which does not require glass powder electrodeposition and sintering process and can reduce mesa width.
상기 목적을 달성하기 위한, 본 발명에 의한 고내압 트랜지스터 제조방법은, 가드링 형성을 위한 영역의 반도체 기판에 반응성 이온 식각방식으로 트렌치 메사부를 형성하는 공정과, 상기 트렌치 메사부의 내벽에 보호막을 형성하는 공정과, 그 내벽에 보호막이 형성되어 있는 상기 트렌치 메사부 내부를 다결정실리콘으로 채우는 공정을 포함하는 것을 특징으로 한다.In order to achieve the above object, a method of manufacturing a high breakdown voltage transistor according to the present invention includes forming a trench mesa portion in a reactive ion etching method on a semiconductor substrate in a region for forming a guard ring, and forming a protective film on an inner wall of the trench mesa portion. And filling the inside of the trench mesa portion in which the protective film is formed on the inner wall thereof with polycrystalline silicon.
이때, 상기 반도체 기판은 N+형 반도체 기판일 경우, 상기 트렌치 메사부를 형성하기 전에, 상기 N+ 반도체 기판 상에 N- 에피텍셜층을 형성하는 공정과, 상기 N- 에피텍셜층 상에 P- 베이스층을 형성하는 공정과, 상기 P- 베이스층 상에 N+ 에미터층을 형성하는 공정을 더 포함하고, 상기 트렌치는 상기 N+ 반도체 기판이 노출될 정도의 깊이로 형성하는 것이 바람직하다.At this time, when the semiconductor substrate is an N + type semiconductor substrate, before forming the trench mesa portion, forming a N- epitaxial layer on the N + semiconductor substrate, and a P- base layer on the N- epitaxial layer. And forming a N + emitter layer on the P− base layer, wherein the trench is preferably formed to a depth such that the N + semiconductor substrate is exposed.
상기 보호막을 형성하는 공정은 상기 트렌치 메사부 내벽에 열산화막을 성장시키는 공정이고, 상기 다결정실리콘은 불순물이 도우프되지 않은 다결정실리콘이다.The forming of the protective film is a step of growing a thermal oxide film on the inner wall of the trench mesa portion, and the polycrystalline silicon is polycrystalline silicon which is not doped with impurities.
이하, 첨부한 도면을 참조하여, 본 발명에 의한 고내압 트랜지스터 제조방법을 더욱 상세하게 설명하고자 한다.Hereinafter, a high voltage withstand transistor manufacturing method according to the present invention will be described in detail with reference to the accompanying drawings.
도 3 내지 도 6은 본 발명에 의한 메사 공정을 이용한 고내압 트랜지스터 제조방법을 설명하기 위해 도시한 단면도들이다.3 to 6 are cross-sectional views illustrating a method of manufacturing a high breakdown voltage transistor using a mesa process according to the present invention.
먼저, 도 3은 N- 에피텍셜층(32), P- 베이스층(34) 및 N+ 에미터층(36)을 형성하는 공정을 설명하기 위해 도시한 단면도로서, 이 공정은, N+ 반도체 기판(30) 상에 에피텍셜 공정을 행하여 N- 에피텍셜층(32)을 형성하는 단계, 상기 에피텍셜층(32)에 P형 불순물을 저농도로 도우프하여 P- 베이스층(34)을 형성하는 단계, 및 상기 P- 베이스층(34) 내에 N형 불순물을 고농도로 도우프하여 N+ 에미터층(36)을 형성하는 단계로 진행한다. 이후, 상기 에미터층(36)까지 형성되어 있는 기판 전면에 제1 산화막(38)을 형성한다.First, FIG. 3 is a cross-sectional view illustrating a process of forming the N− epitaxial layer 32, the P− base layer 34, and the N + emitter layer 36, which is a N + semiconductor substrate 30. Forming an N- epitaxial layer 32 by performing an epitaxial process on the N-doped layer, doping P-type impurities in the epitaxial layer 32 at low concentration, and forming a P-base layer 34; And doping N-type impurities in the P-base layer 34 at a high concentration to form an N + emitter layer 36. Thereafter, a first oxide film 38 is formed on the entire surface of the substrate formed up to the emitter layer 36.
도 4는 트렌치 메사부(40) 및 보호막(42)을 형성하는 공정을 설명하기 위해 도시한 단면도로서, 이 공정은, 가드링이 형성될 영역의 반도체 기판을, 예컨대 반응성 이온 식각(RIE) 방식으로 상기 N+ 반도체 기판(30)이 부분적으로 노출될 때까지 식각하여 상기 트렌치 메사부(40)를 형성하는 단계, 상기 트렌치 메사부(40) 내벽에, 에컨대 열산화 방식으로 산화막을 성장시킴으로써 상기 에피텍셜층(32)과 베이스층(34) 사이의 접합부(A)를 보호하기 위한 보호막(42)을 형성하는 단계, 및 결과물 기판 전면에, 예컨대 불순물이 도우프되지 않은 다결정실리콘막(44)을 상기 트렌치 메사부(40)를 매립(filling)할 수 있을 정도로 증착하는 단계로 진행한다.FIG. 4 is a cross-sectional view illustrating a process of forming the trench mesa portion 40 and the passivation layer 42. The process includes a semiconductor substrate in a region where a guard ring is to be formed, for example, a reactive ion etching (RIE) method. Forming the trench mesa portion 40 by etching until the N + semiconductor substrate 30 is partially exposed, by growing an oxide film on the inner wall of the trench mesa portion 40 by, for example, thermal oxidation. Forming a protective film 42 for protecting the junction A between the epitaxial layer 32 and the base layer 34, and the polysilicon film 44, for example, which is not doped with impurities, on the entire surface of the resultant substrate. The deposition proceeds to the step of depositing enough to fill the trench mesa portion 40.
이때, 상기 트렌치 메사부(40)는 오픈비(open ratio)가 1% 이내이므로 트랜치 메사부의 깊이와 프로파일에 제약을 받지않는다.At this time, since the trench mesa portion 40 has an open ratio within 1%, the trench mesa portion 40 is not limited to the depth and profile of the trench mesa portion.
도 1 및 도 2에서 설명한 종래의 고내압 트랜지스터의 경우, 메사폭의 크기가 150㎛ ∼ 300㎛ 정도이나, 본 발명의 경우, 상기 트렌치 메사부(40)의 폭은 5㎛ ∼ 6㎛ 정도이므로 칩 사이즈를 종래에 비해 상대적으로 줄일 수 있다.In the case of the conventional high breakdown voltage transistor described with reference to FIGS. 1 and 2, the mesa width is about 150 μm to 300 μm, but in the present invention, the width of the trench mesa portion 40 is about 5 μm to 6 μm. The chip size can be relatively reduced compared to the prior art.
도 5는 상기 트렌치 메사부(40) 이외의 영역에 증착되어 있는 다결정실리콘을 건식식각 방식으로 제거하여 상기 트렌치 메사부(40) 내에 다결정실리콘 플럭층(44a)을 형성한 후의 단면도이다.FIG. 5 is a cross-sectional view after the polysilicon deposited in regions other than the trench mesa portion 40 is removed by dry etching to form the polysilicon floc layer 44a in the trench mesa portion 40.
도 1에서 설명한 종래 방식에 의하면, 에피텍셜층과 베이스층 사이의 PN 접합부를 보호하기 위하여 글래스 파우더를 전착한 후 소결하는 방식을 채용하였다. 그러나, 본 발명에서는 글래스 파우더 대신 불순물이 도우프되지 않는 다결정실리콘으로 상기 트렌치 메사부(40)를 채우므로 글래스 파우더를 소결하는 것과 같은 열처리 공정이 불필요하기 때문에 다결정실리콘막(44)과 산화막(즉, 보호막(42))의 경계면에 응력이 발생되지 않아, 웨이퍼 본딩과 파손이 발생되지 않는다. 또한 상기 다결정실리콘막(44)을 형성하는 단계는 기존 제조 설비를 그대로 이용하여 진행되기 때문에 별도의 장비투자와 별도의 클린 룸이 필요치 않고, 타 공정 진행시 활성영역에 글래스 파우더와 같은 파티클 흡착이 없으므로 미세 패턴으로 형성된 MOSFET, IGBT와 같은 소자에도 응용이 가능하다.According to the conventional method described in FIG. 1, in order to protect the PN junction portion between the epitaxial layer and the base layer, a method of electrodepositing the glass powder and then sintering was employed. However, in the present invention, since the trench mesa portion 40 is filled with polycrystalline silicon that is not doped with impurities instead of glass powder, a heat treatment process such as sintering the glass powder is unnecessary, so that the polycrystalline silicon film 44 and the oxide film (that is, No stress is generated at the interface of the protective film 42, and wafer bonding and breakage do not occur. In addition, the step of forming the polysilicon film 44 does not require a separate equipment investment and a separate clean room because the existing manufacturing equipment is used as it is, and adsorbing particles such as glass powder to the active region during other processes is performed. Therefore, it can be applied to devices such as MOSFET and IGBT formed in a fine pattern.
도 6은 베이스 전극(48) 및 에미터 전극(50)을 형성하는 공정을 설명하기 위해 도시한 단면도로서, 이 공정은, 다결정실리콘 플럭층(44a)까지 형성되어 있는 기판 전면에, 예컨대 인이 도우프된 글래스(PSG)와 같은 절연물질을 도포하여 제2 산화막(46)을 형성하는 단계, 상기 제1 및 제2 산화막(38 및 46)을 부분적으로 식각하여 베이스층(34)과 에미터층(36)을 부분적으로 노출시키기 위한 접촉창을 형성하는 단계, 및 상기 접촉창을 채우도록 금속 물질을 도포한 후 이를 패터닝함으로써 상기 베이스층(34)과 접속하는 베이스 전극(48)과 상기 에미터층(36)과 접속하는 에미터 전극(50)을 형성하는 단계로 진행한다.FIG. 6 is a cross-sectional view for explaining a process of forming the base electrode 48 and the emitter electrode 50. The process is performed by, for example, phosphorus on the entire surface of the substrate formed up to the polysilicon floc layer 44a. Forming a second oxide film 46 by applying an insulating material such as doped glass (PSG), and partially etching the first and second oxide films 38 and 46 to form a base layer 34 and an emitter layer. Forming a contact window for partially exposing the 36, and applying and patterning a metal material to fill the contact window, thereby patterning the base electrode 48 and the emitter layer in contact with the base layer 34. Proceeding to the step of forming the emitter electrode 50 to be connected to 36.
본 발명은 상기 실시예에 한정되지 않으며, 많은 변형이 본 발명의 기술적 사상내에서 당 분야에서 통상의 지식을 가진 자에 의하여 가능함은 명백하다.The present invention is not limited to the above embodiments, and it is apparent that many modifications are possible by one of ordinary skill in the art within the technical idea of the present invention.
본 발명에 의한 고내압 트랜지스터 제조방법에 의하면, 첫째, 반응성 이온 식각방식을 이용하여 트렌치 메사부를 형성하므로 트렌치 메사부의 폭을 5㎛ ∼ 6㎛로 줄일 수 있으므로 칩 사이즈를 종래와 비교하여 상대적으로 줄일 수 있다. 둘째, 글래스 파우더 대신 불순물이 도우프되지 않은 다결정실리콘을 사용하여 상기 트렌치 메사부를 채우므로 글래스 소결과 같은 열처리 공정이 불필요하고, 다결정 실리콘막과 산화막의 경계면에서 응력이 발생되지 않아, 웨이퍼가 휘어지거나 파손되는 현상이 발생하지 않는다. 셋째, 다결정실리콘으로 트렌치 메사부를 채우기 때문에 기존 제조 설비를 그대로 이용할 수 있어 별도의 장비투자와 별도의 클린 룸이 필요치 않고, 타 공정 진행 시 활성영역부에 글래스 파우더와 같은 파티클 흡착이 없으므로 미세 패턴으로 형성된 MOSFET, IGBT와 같은 소자에도 응용이 가능하다.According to the method of manufacturing a high breakdown voltage transistor according to the present invention, first, since the trench mesa portion is formed using the reactive ion etching method, the width of the trench mesa portion can be reduced to 5 μm to 6 μm, thereby reducing the chip size relatively. Can be. Second, since the trench mesa portion is filled using polycrystalline silicon without impurities doped instead of glass powder, a heat treatment process such as glass sintering is unnecessary, and stress is not generated at the interface between the polycrystalline silicon film and the oxide film, so that the wafer is bent or Breakage does not occur. Third, since the trench mesa part is filled with polysilicon, the existing manufacturing equipment can be used as it is, and no separate equipment investment and a separate clean room are required, and there is no particle adsorption such as glass powder in the active area during other processes. It can also be applied to devices such as formed MOSFETs and IGBTs.
도 1은 종래 일방법에 의한 메사 공정을 이용한 고내압 트랜지스터 제조방법을 설명하기 위해 도시한 단면도이다.1 is a cross-sectional view illustrating a method of manufacturing a high breakdown voltage transistor using a mesa process according to the related art.
도 2는 종래 다른 방법에 의한 메사 공정을 이용한 고내압 트랜지스터 제조방법을 설명하기 위해 도시한 단면도이다.2 is a cross-sectional view illustrating a method of manufacturing a high breakdown voltage transistor using a mesa process according to another method.
도 3 내지 도 6은 본 발명에 의한 메사 공정을 이용한 고내압 트랜지스터 제조방법을 설명하기 위해 도시한 단면도들이다.3 to 6 are cross-sectional views illustrating a method of manufacturing a high breakdown voltage transistor using a mesa process according to the present invention.
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980002406A KR100505561B1 (en) | 1998-01-26 | 1998-01-26 | Manufacturing method of high breakdown voltage transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980002406A KR100505561B1 (en) | 1998-01-26 | 1998-01-26 | Manufacturing method of high breakdown voltage transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR19990066467A KR19990066467A (en) | 1999-08-16 |
| KR100505561B1 true KR100505561B1 (en) | 2005-10-19 |
Family
ID=37305384
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019980002406A KR100505561B1 (en) | 1998-01-26 | 1998-01-26 | Manufacturing method of high breakdown voltage transistor |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100505561B1 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100886809B1 (en) * | 2002-07-22 | 2009-03-04 | 페어차일드코리아반도체 주식회사 | High voltage semiconductor device having deep trench terminations and method for fabricating the same |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR0155861B1 (en) * | 1995-07-25 | 1998-12-01 | 김광호 | Semiconductor device and manufacture thereof |
-
1998
- 1998-01-26 KR KR1019980002406A patent/KR100505561B1/en not_active IP Right Cessation
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR0155861B1 (en) * | 1995-07-25 | 1998-12-01 | 김광호 | Semiconductor device and manufacture thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| KR19990066467A (en) | 1999-08-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP0777910B1 (en) | Process for manufacture of mos gated device with reduced mask count | |
| JP3365984B2 (en) | MOS gate device and its manufacturing process | |
| EP1255302B1 (en) | Method for fabricating forward and reverse blocking devices | |
| US5672889A (en) | Vertical channel silicon carbide metal-oxide-semiconductor field effect transistor with self-aligned gate for microwave and power applications, and method of making | |
| JPH03142972A (en) | Closure type cell transistor having built-in voltage clamp | |
| JPH07312372A (en) | Accumulation edge structure for high-voltage semiconductor device and its preparation | |
| JP4490094B2 (en) | Method of manufacturing trench metal oxide semiconductor field effect transistor device | |
| JP2003318399A (en) | Semiconductor device and manufacturing method therefor | |
| CN110277439B (en) | MOSFET device with silicon carbide inverted T-shaped masking layer structure and preparation method thereof | |
| TWI818228B (en) | High voltage edge termination structure for power semicondcutor devices and manufacturing method thereof | |
| GB2306249A (en) | Termination structure for semiconductor device and process for manufacture thereof | |
| US6207974B1 (en) | Process for manufacture of a p-channel MOS gated device with base implant through the contact window | |
| US5952679A (en) | Semiconductor substrate and method for straightening warp of semiconductor substrate | |
| JP3869580B2 (en) | Semiconductor device | |
| JPH0286136A (en) | Semiconductor element and manufacture thereof | |
| CN111986991A (en) | Groove etching method, silicon carbide device preparation method and silicon carbide device | |
| JP2018133493A (en) | Semiconductor device | |
| KR100505561B1 (en) | Manufacturing method of high breakdown voltage transistor | |
| JP2005051111A (en) | Mesa type semiconductor device | |
| KR100505271B1 (en) | MOS-Gate Semiconductor Devices | |
| JPH0286171A (en) | Semiconductor element and its manufacture | |
| CN114628525A (en) | Groove type SiC MOSFET device and manufacturing method thereof | |
| JPH08274351A (en) | Dielectric isolation semiconductor device and its manufacture | |
| JP3917202B2 (en) | Manufacturing method of semiconductor devices | |
| CN210379054U (en) | MOSFET device with silicon carbide inverted-T-shaped masking layer structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| N231 | Notification of change of applicant | ||
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20130628 Year of fee payment: 9 |
|
| FPAY | Annual fee payment |
Payment date: 20140701 Year of fee payment: 10 |
|
| LAPS | Lapse due to unpaid annual fee |