JP2005051111A - Mesa type semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a mesa type semiconductor device capable of realizing very high reliability which can prevent an increase of a leakage current and a decrease of withstand voltage, and of realizing a low cost due to a groove structure made fine. <P>SOLUTION: A mesa type npn bipolar transistor of the present invention comprises an n-type semiconductor region 1 as a collector region, an n<SP>+</SP>-type semiconductor region 2, a p-type semiconductor region 3 as a base region, and an n<SP>+</SP>-type semiconductor region 4 as an emitter region. A mesa groove 6 is provided around the base region 3 and the emitter region 4 to expose a pn junction. The surface of the mesa groove is covered with a thermal oxide film 7 and an aluminum field plate 8. Further, the mesa groove 6 undergoes wet etching to the depth of ≥1.0×10<SP>17</SP>cm<SP>-3</SP>impurity concentration in the n<SP>+</SP>-type semiconductor region 2, and impurity concentration at a mesa bottom is set to ≤1.0×10<SP>18</SP>cm<SP>-3</SP>. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a high-breakdown-voltage semiconductor device, and more particularly to a semiconductor device that achieves high breakdown voltage, high reliability, and low price.

  Various techniques for increasing the breakdown voltage and reliability of a mesa semiconductor device have been proposed.

  For example, a technique described in Patent Document 1 is known as a technique related to increasing the breakdown voltage of a mesa semiconductor device. According to this prior art, in a method for manufacturing a semiconductor device in which the inner wall of a mesa groove is coated with glass, a high breakdown voltage can be obtained by moving the pn junction from the initial position by heat treatment after the mesa groove is formed. .

  Further, as another conventional technique related to increasing the breakdown voltage of a mesa type semiconductor device, a technique described in Patent Document 2 is known. In this prior art, two adjacent mesa grooves are provided within a certain width, a convex part is provided in the middle of the two communication mesa grooves, and the convex part is made lower than the surface of the semiconductor substrate. By forming by etching, cracks are prevented from entering the glass during dicing, thereby improving the reliability of the semiconductor device and increasing the breakdown voltage.

  Further, as another conventional technique related to high reliability of a mesa semiconductor device, a technique described in Patent Document 3 is known. In this conventional technique, when a glass coating of the first layer is formed by electrophoretic glass powder deposition and firing in the mesa groove, a second glass coating is deposited again by electrophoresis and firing. It is supposed that a glass coating without any problem can be obtained and high reliability can be realized.

Furthermore, a technique described in Patent Document 4 is known as a conventional technique related to high breakdown voltage and high reliability of a mesa semiconductor device. This conventional technique adjusts the charge density in the glass coating by having a region in which the Group III element in the glass coating is diffused on the surface of the mesa semiconductor region, and reduces the leakage current and leakage current in the reverse bias high temperature test. Reduction is supposed to be realized.
JP 60-186071 A Japanese Unexamined Patent Publication No. 7-2221049 JP-A-8-222558 JP-A-10-27917

  However, in the above prior art, most of the semiconductor devices have glass on the semiconductor surface of the groove, and the semiconductor devices having glass are complicated and costly.

  Furthermore, in the prior art described in Patent Documents 1 to 3, no consideration is given to problems relating to increase in leakage current and breakdown voltage degradation due to a high temperature reverse bias test, so-called high reliability with respect to lifetime.

  The present invention realizes a reduction in cost by miniaturizing a groove structure that can prevent an increase in leakage current and a decrease in breakdown voltage due to a life test such as a reverse bias test (hereinafter referred to as a BT test) at a high temperature and realize high reliability. It is an object of the present invention to provide a semiconductor device capable of performing the above.

  In order to solve the above-described problem, a mesa semiconductor device of the present invention has a conductivity type opposite to the substrate from the surface of the substrate in a one conductivity type semiconductor substrate having a high-concentration impurity layer of one conductivity type on the back surface. A pn junction is formed by diffusing the impurities, and a mesa type or trench type groove having an opening is provided on the substrate surface so that the pn junction is exposed in a predetermined region of the substrate, And a field plate made of a conductive electrode is formed on a part of the oxide film and a part of the substrate surface not covered with the oxide film. .

It is preferable that the bottom surface of the groove reaches a region where the impurity concentration in the high conductivity impurity layer of one conductivity type is 1.0 × 10 ¹⁷ cm ⁻³ or more.

  More preferably, the groove is filled with a polyimide film or resin.

  According to the present invention, a mesa semiconductor device can be manufactured without using a glass coating, and the process can be simplified, and a low-cost, high-reliability high-voltage mesa semiconductor device can be provided.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 1 is a cross-sectional view of a mesa semiconductor device according to a first embodiment of the present invention. In this embodiment, an npn bipolar transistor is shown. An n-type semiconductor region 1 serving as a collector region, an n ⁺ -type semiconductor region 2, a p-type semiconductor region 3 serving as a base region, and an n ⁺ -type semiconductor region 4 serving as an emitter region, and the periphery of the base region 3 and the emitter region 4 A mesa groove 6 is provided so that the pn junction is exposed, and its surface is covered with a thermal oxide film 7 and an aluminum field plate 8. The field plate may use another conductive electrode such as polysilicon as shown in FIG.

  FIG. 3 is an explanatory diagram of the manufacturing process of the mesa semiconductor device shown in FIG. 1, and the manufacturing method will be described below with reference to FIG.

First, phosphorus is diffused from one side of an n-type silicon substrate having a specific resistance of 60 Ωcm and a thickness of 305 μm to form an n ⁺ -type semiconductor region 2 having a diffusion depth of 180 μm and a surface concentration of 2.0 × 10 ²⁰ cm ⁻³ . Thereafter, a silicon oxide film 5 is formed on the surface of the silicon substrate, and then boron, aluminum, etc. are diffused from the side opposite to the n ⁺ type semiconductor region 2 to obtain a surface concentration of 5.0 × 10 ^{17 to} 5.0 × 10 ^18. A p − type semiconductor region 3 of cm ⁻³ is formed (FIG. 3A).

Next, phosphorous is selectively doped into a portion to be an emitter region (FIG. 3B). After that, a part of the silicon oxide film 5 is removed, and an etching process is performed in a mixed solution of hydrofluoric acid: nitric acid: acetic acid = 3: 6: 2 (volume ratio) cooled to 7 ° C. ± 2 ° C. A mesa groove 6 having a depth of 180 μm and a width of 440 μm is formed. This mesa groove 6 is wet-etched to a depth of not less than 1.0 × 10 ¹⁷ cm ⁻³ in the n ⁺ -type semiconductor region 2, and the impurity concentration at the bottom of the mesa is not more than 1.0 × 10 ¹⁸ cm ^−3. (FIG. 3C). Thereafter, thermal diffusion is performed to form an emitter region 4 having a surface concentration of 4.0 × 10 ¹⁹ cm ⁻³ or more. Then, a silicon oxide film 5 'is newly formed on the base region 3, the emitter region 4, and the mesa portion (FIG. 3D).

  After that, the silicon oxide film 5 'at a portion to be a contact region with the base and emitter aluminum electrodes is selectively removed (FIG. 3E).

  Finally, a base electrode 9, an emitter electrode 10, and a collector electrode 11 are formed on an n-type semiconductor substrate, and an aluminum field plate 8 is formed to cover the side surface of the groove 6 (FIG. 3 (f)). Thereafter, a polyimide film 12 is selectively formed in the groove 6 in order to improve the reliability (FIG. 3G). This may be a polyimide resin.

  Thereafter, the center of the mesa groove 6 is diced to separate the elements, and a high-voltage, high-reliability mesa semiconductor device is obtained (FIG. 3 (h)).

  According to the present embodiment, by forming the field plate in the mesa groove, high breakdown voltage and high reliability can be realized more efficiently from the resistance of the semiconductor substrate without using glass. In addition, with this action, the characteristics of the semiconductor device can be further improved, and the area of the semiconductor device can be further reduced in order to obtain equivalent characteristics. In addition, since the resistance at the bottom of the mesa portion having a relatively low impurity concentration can be used, high breakdown voltage can be realized efficiently, and the size of the semiconductor device can be further reduced. This is particularly effective for downsizing a semiconductor device of 600V or higher.

  FIG. 4 is a diagram comparing reliability test results between the mesa semiconductor device of the present invention and a conventional mesa semiconductor device. A BT test was conducted as a reliability test.

  As can be seen, after 100 hours of testing, the leakage current between the collector and the emitter has increased by about an order of magnitude in the conventional device, whereas the device of the present invention hardly increases and has high reliability. I understand.

  In this embodiment, the mesa groove is formed. However, as shown in FIG. 5, a trench groove may be formed and a conductive film such as polysilicon 13 may be embedded in the trench groove.

  Although the embodiment of the present invention has been described with respect to a high-breakdown-voltage mesa npn bipolar transistor, the same effect can be obtained for a MOSFET, IGBT, thyristor, diode, and the like that are mesa-type and have a glass film.

  According to the present invention, a mesa semiconductor device can be manufactured without using a glass coating, and the process can be simplified, and a low-cost, high-reliability high-voltage mesa semiconductor device can be provided.

Sectional drawing of the mesa type semiconductor device in the 1st Embodiment of this invention Sectional drawing of the modification of the mesa type semiconductor device in the 1st Embodiment of this invention Manufacturing process explanatory drawing of the mesa type semiconductor device in the first embodiment of the present invention The figure which shows the comparison of the reliability test result of the mesa type semiconductor device in this invention and the prior art Sectional drawing of another modification of the mesa type semiconductor device in the 1st Embodiment of this invention

Explanation of symbols

1 n-type semiconductor region (collector region)
2 n ⁺ type semiconductor region (collector region)
3 p-type semiconductor region (base region)
4 n ⁺ type semiconductor region (emitter region)
5, 5 'silicon oxide film 6 mesa groove 7 silicon oxide film on side of mesa groove 8 aluminum field plate 9 base electrode 10 emitter electrode 11 collector electrode 12 polyimide resin 13 polysilicon field plate

Claims (3)

A pn junction is formed by diffusing impurities of a conductivity type opposite to the substrate from the surface of the substrate in a semiconductor substrate of one conductivity type having a high-concentration impurity layer of one conductivity type on the back surface. A mesa-type or trench-type groove having an opening is provided on the surface of the substrate so that the pn junction is exposed in the region, and the bottom and side surfaces of the groove are covered with an oxide film. A mesa-type semiconductor device, wherein a field plate made of a conductive electrode is formed on a portion and a part of the substrate surface not covered with the oxide film. 2. The mesa semiconductor device according to claim 1, wherein the bottom surface of the groove reaches a region where an impurity concentration in the high-concentration impurity layer of one conductivity type is 1.0 × 10 ¹⁷ cm ⁻³ or more. 3. The mesa semiconductor device according to claim 1, wherein the groove is filled with a polyimide film or resin.

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