JP3371763B2 - Silicon carbide semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a silicon carbide semiconductor device.

[0002]

2. Description of the Related Art Silicon carbide (hereinafter abbreviated as SiC) has a large band gap and is a chemically stable material, so that it is expected to have various semiconductor devices that can be used under high temperature and radiation as compared with silicon. Has been researched. Up to 150 ° C for conventional silicon devices
Although the extent of its operation is considered to be the limit, in SiC, element devices such as pn junction diodes and MOSFETs (metal-oxide-semiconductor field-effect transistors) have already been prototyped and confirmed to operate even at high temperatures of 400 ° C or higher. Has been done. If it can be used at such a high temperature, robots, computers, etc. can be used in environments where the environment such as nuclear reactors and space is harsh and inaccessible to humans. In addition, the conventional silicon device needs to be equipped with cooling equipment to suppress the temperature rise due to heat generation due to the loss generated during operation, and the cooling fin and the cooling equipment increase the overall size of the device. I will end up. With SiC, these cooling facilities can be significantly downsized and simplified. If the semiconductor device that occupies many parts can be downsized as described above, for example, in an automobile, fuel consumption can be significantly improved, and a great effect can be expected for environmental protection. As described above, SiC semiconductor devices are expected in many application fields.

The vertical MOSFET is an important device when considering application of SiC to a power semiconductor device. The reason is that it is a voltage drive type device, so that elements can be driven in parallel and the drive circuit can be simplified, and because it is a unipolar element, high speed switching is possible. Unlike SiC, it is difficult to diffuse deep impurities in SiC, but epitaxial growth is relatively easy. Therefore, a trench MOSFET having a trench 5 as shown in FIG. 5 is generally used. FIG. 5 is a cross-sectional view of an essential part of a SiC trench MOSFET that has been prototyped so far. 5, lower it than the impurity concentration on the n ⁺ substrate 1 n ^- drift layer 2 and the p-type p base layer 3 on the surface layer of the SiC substrate epitaxially grown selectively high concentrations of n ⁺ source region 4 is formed, and in a part of the n ⁺ source region 4, a groove (hereinafter referred to as a trench) 5 reaching the n ⁻ drift layer 2 from the surface is formed. Inside the trench 5, the gate electrode 1 is provided via the gate insulating film 6.
3 is provided, and the source electrode 12 is in contact with the surface of the n ⁺ source region 4 and the exposed surface of the p base layer 3 in common.
Drain electrodes 11 are provided on the back surface of the n ⁺ substrate 1, respectively. In SiC, a silicon oxide film formed by thermally oxidizing SiC can be used as the gate insulating film.

The operation of this MOSFET is such that when a positive voltage higher than a certain value is applied to the gate electrode 13 in the state where a voltage is applied between the drain electrode 11 and the source electrode 12, the p-base on the side of the gate electrode 13 is applied. An inversion layer is formed on the surface layer of the layer 3, and an electron current flows from the source electrode 12 to the drain electrode 11 through the inversion layer.

[0005]

When the electric field of the insulating film is Ei and the electric field of the semiconductor is Es at the interface between the insulating film and the semiconductor, the following equation holds: εi · Ei = εs · Es. Where εs is the relative dielectric constant of the semiconductor,
εi is the relative dielectric constant of the insulating film. Therefore, Ei / Es = εs / εi. This value will be calculated for silicon and SiC.

Εs = 11.7 (silicon) εs = 10.0 (SiC). Now, assuming that the insulating film is a silicon oxide film and its dielectric constant εi = 3.8 is substituted, Ei / Es = 3.1. (Silicon) Ei / Es = 2.6 (SiC). That is, in the conventional structure of FIG. 5, a much larger electric field is applied to the gate insulating film than the semiconductor portion. FIG. 6 shows the electric field distribution in the gate portion along the line XX ′ in FIG. The vertical axis represents electric field strength, and the horizontal axis represents depth. The electric field strength Ei of the insulating film is about three times as large as the electric field strength Es of the semiconductor.

Further, the maximum electric field Esmax of the semiconductor is Esmax = 2 × 10 ⁵ V / cm (silicon) Esmax = 2 × 10 ⁶ V / cm (SiC). Therefore, the maximum electric field Eimax of the insulating film is Eimax = 6 × 10 ⁵ V / cm (silicon) Eimax = 5 × 10 ⁶ V / cm (SiC). Dielectric breakdown voltage of silicon oxide film is 8 × 10 ⁶ V
Considering about / cm 2, when avalanche breakdown starts inside the semiconductor, in the case of SiC, a large electric field close to the dielectric breakdown voltage is applied to the gate insulating film.

Normally, a power device is required to withstand a constant current when an avalanche current flows, but in a conventional SiC trench MOSFET, avalanche breakdown starts in the trench of the gate portion, so that the avalanche withstand capability is the gate. It is defined by the dielectric breakdown of the insulating film, and the high dielectric breakdown electric field strength of SiC cannot be utilized. In view of the above problems, it is an object of the present invention to provide a SiC trench MOSFET having a large avalanche withstanding capacity, in which dielectric breakdown of a gate insulating film does not occur.

[0009]

In order to solve the above problems, a silicon carbide semiconductor device according to the present invention is a silicon carbide having a lower impurity concentration than a substrate sequentially formed on a first conductivity type silicon carbide semiconductor substrate. First conductivity type drift layer, a second conductivity type base layer of silicon carbide, a first conductivity type source region formed in a part of a surface layer of the second conductivity type base layer, and a first conductivity type source thereof. A first trench that reaches the first conductivity type drift layer from the surface of the region is provided with an electrode that applies a voltage through an insulating film in the first trench, and a second trench that is deeper than the trench, And a second conductivity type region along the second trench.

According to the above means, by providing the second trench deeper than the first trench filled with the gate electrode and the second conductivity type region along the second trench, the insulating film and the first trench are provided. The electric field strength at the interface of the conductivity type drift layer can be relaxed and the avalanche withstand capability can be increased.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a SiC according to an embodiment of the present invention.
FIG. 4 is a cross-sectional view of a main part of a trench MOSFET. FIG. 1 shows an active region for turning on / off a current. In addition to this, the MOSFET mainly has a peripheral portion for withstanding voltage, but that portion is a portion related to the essence of the present invention. Since it is not, the description is omitted. In FIG. 1, in a SiC substrate in which an n ⁻ drift layer 2 having a lower impurity concentration and ap type p base layer 3 are epitaxially grown on an n ⁺ substrate 1, a high concentration is selectively applied to a surface layer of the p base layer 3. N ⁺ source region 4 of is formed, and in a part of the n ⁺ source region 4,
A trench 5 reaching the n ⁻ drift layer 2 from the surface is formed. Inside the trench 5, a gate electrode 13 made of polycrystalline silicon is provided via a gate insulating film 6 made of a silicon oxide film.
Is provided. A drain electrode 11 of Ni film is provided on the back surface of the n ⁺ substrate 1. This MOSF
In the ET, a second trench 8 deeper than the surface of the p base layer 3 than the trench 5 in the gate portion, and a p ⁺ type region 7 are formed along the side surface and the bottom surface of the second trench 8. Then, from the p ⁺ type region 7 to the p base layer 3,
A source electrode 12 made of Ti—Al that reaches the surface of the n ⁺ source region 4 is provided. The operation of the MOSFET of FIG. 1 is such that when a positive voltage higher than a certain value is applied to the gate electrode 13 in the state where a voltage is applied between the drain electrode 11 and the source electrode 12, the p base layer beside the gate electrode 13 is applied. An inversion layer is formed on the surface layer of No. 3, and an electron current flows from the source electrode 12 to the drain electrode 11 through the inversion layer. In the MOSFET of FIG. 1, the second trench 8 is deeper than the trench 5 in the gate portion. Therefore, when a voltage is applied between the drain electrode 11 and the source electrode 12 and the voltage is increased, the depletion that spreads from the pn junction composed of the p ⁺ type region 7 and the n ⁻ drift layer 2 to the n ⁻ drift layer 2. The layer relaxes the electric field strength at the interface between the gate insulating film 6 and the n ⁻ drift layer 2.

FIG. 2 is a result of simulating the electric field strength along the line XX 'of the conventional MOSFET shown in FIG. 5 and the MOSFET according to the present invention shown in FIG. The horizontal axis represents the distance from the bottom of the gate insulating film 6 (the distance from the upper surface in the XX ′ direction), and the vertical axis represents the electric field strength. As can be seen from FIG. 3, the electric field strength on the n ⁻ drift layer 2 side of the interface between the gate insulating film 6 and the n ⁻ drift layer 2 is 2.0 in the conventional technique, whereas it is 1.2 in the present invention. Can be reduced to That is, a pn formed of the p ⁺ type region 7 and the n ⁻ drift layer 2
By the depletion layer extending from the junction to the n ⁻ drift layer 2,
Since the electric field strength at the interface between the gate insulating film 6 and the n ⁻ drift layer 2 is relaxed, avalanche breakdown does not occur at the corners of the trench 5 in the gate portion and the gate insulating film 6 is not destroyed. That is, it is possible to obtain a MOSFET having a large avalanche withstand capability in which the gate insulating film does not undergo dielectric breakdown when a voltage is applied.

FIGS. 3A to 3D are sectional views of respective steps for explaining the method of manufacturing the trench MOSFET of the embodiment shown in FIG. An n ⁻ drift layer 2 having a lower impurity concentration and ap type p base layer 3 are formed on the n ⁺ substrate 1 by epitaxial growth [FIG. 3 (a)]. Next, nitrogen ions of high concentration are selectively implanted into the surface layer of the p base layer 3 to form the n ⁺ source region 4. Next, the trench 5 in the gate portion is formed by patterning the photoresist and performing plasma etching using a mixed gas of fluorine and oxygen. Next, the gate insulating film 6 is formed in the trench 5 in the gate portion by thermal oxidation, and polycrystalline silicon is filled by the low pressure CVD method to form the gate electrode 13 [FIG. 3 (b)]. Next, the second trench 8 is formed by patterning the photoresist and performing plasma etching using a mixed gas of fluorine / oxygen. Next, high-concentration boron ions are implanted to form the p ⁺ type region 7, and heat treatment for defect recovery is performed. It is important that the depth of the second trench 8 is deeper than that of the trench 5 in the gate portion [FIG. 3 (c)]. Finally, Ni is vapor-deposited to form the drain electrode 11, and Ti-Al is vapor-deposited to form the source electrode 12 [FIG. 3 (d)].

FIG. 4 is a sectional view of another embodiment of the present invention. The second trench 8 deeper than the trench 5 in the gate portion from the surface of the p base layer 3 and the p ⁺ type region 7 formed along the bottom surface and the side surface of the second trench 8 are the same as in FIG. 1. Is. However, in the MOSFET, that there are a plurality of trenches 5 during other p ⁺ -type region 7 adjacent the p ⁺ -type region 7 different. P ⁺ type region 7 during forward conduction
Since a dead space in which a current does not flow is generated, the on-voltage increases. However, with the structure shown in FIG. 4, the area occupied by the p ⁺ type region 7 can be reduced and the on-voltage can be reduced.

FIG. 7 is a sectional view of another embodiment in which the effect of electric field relaxation is further improved with respect to FIG. In FIG. 7, in the SiC substrate in which the n ⁻ drift layer 2 having a lower impurity concentration and the p-type p base layer 3 are epitaxially grown on the n ⁺ substrate 1, a high concentration is selectively formed on the surface layer of the p base layer 3. N ⁺ source region 4 is formed, and a trench 5 reaching the n ⁻ drift layer 2 from the surface is formed in a part of the n ⁺ source region 4. Inside the trench 5, a polycrystalline silicon gate electrode 13 is provided via a gate insulating film 6 of a silicon oxide film. Also, the drain electrode 1 of Ni film is formed on the back surface of the n ⁺ substrate 1.
1 is provided. A second trench 8 deeper than the gate portion trench 5 is formed from the surface of the p base layer 3, and a p ⁺ type region 7 is provided along the side surface and the bottom surface of the second trench 8. Then, Ti− that reaches the surface of the p base layer 3 and the n ⁺ source region 4 from the p ⁺ type region 7
A source electrode 12 made of Al is provided. The feature of FIG. 7 is that the position where the p ⁺ -type region 7 is most widened in the lateral direction is located inside the substrate surface, and is of an inverse taper type. When a voltage is applied between the drain electrode 11 and the source electrode 12 to increase the voltage, the p ⁺ type region 7
And n ^- from the pn junction consisting of the drift layer 2, n ^- depletion layer that spreads in the drift layer 2 becomes wider toward the interior than the substrate surface. Therefore, with the structure shown in FIG. 7, p ⁺
The depletion layer extending in the direction of the n ⁻ drift layer 2 from the other p ⁺ type region 7 adjacent to the type region 7 has a lower source than that in FIG.
For contacting the drain voltage, the gate insulating film 6 and n ^-
The effect of relaxing the electric field at the interface of the drift layer 2 is great.

FIG. 8 is a sectional view of another embodiment of the present invention. In FIG. 8, in the SiC substrate in which the n ⁻ drift layer 2 having a lower impurity concentration and the p-type p base layer 3 are epitaxially grown on the n ⁺ substrate 1, a high concentration is selectively applied to the surface layer of the p base layer 3. N ⁺ source region 4
And a trench 5 reaching the n ⁻ drift layer 2 from the surface is formed in a part of the n ⁺ source region 4. Inside the trench 5, a polycrystalline silicon gate electrode 13 is provided via a gate insulating film 6 of a silicon oxide film. A drain electrode 11 of Ni film is provided on the back surface of the n ⁺ substrate 1. In this MOSFET, a second trench 8 deeper than the trench 5 in the gate portion from the surface of the p base layer 3 and ap ⁺ type region 7 are formed so as to intersect the trench 5. Then, a source electrode 12 made of Ti—Al that extends from the p ⁺ type region 7 to the surfaces of the p base layer 3 and the n ⁺ source region 4 is provided. Also in the structure of FIG. 8, when a voltage is applied between the drain electrode 11 and the source electrode 12 and the voltage is increased,
The depletion layer extending from the pn junction formed of the p ⁺ type region 7 and the n ⁻ drift layer 2 to the n ⁻ drift layer 2 relaxes the electric field strength at the interface between the gate insulating film 6 and the n ⁻ drift layer 2. Therefore, the avalanche resistance of MOSFET is SiC
Gate insulation film 6 defined by the dielectric breakdown field strength of
Can't be destroyed. That is, it is possible to obtain a MOSFET having a large avalanche withstand capability in which the gate insulating film does not undergo dielectric breakdown when a voltage is applied.

FIG. 9 shows an example of a main circuit of a power inverter device using a MOSFET as a switching element according to the present invention. The MOSFET according to the present invention is applied to a portion surrounded by a broken line in the figure, that is, an antiparallel circuit portion of the MOSFET and the diode. This inverter device includes a pair of DC terminals 121 and 12
2 and three AC terminals 131 to 3 equal to the number of AC phases
It is equipped with 133, DC power supply is connected to the DC terminal, and MOSFET 10
By switching 1 to 106, DC power is converted to AC power and output to the AC terminal. Between the DC terminals,
Set of MOSFETs 101 and 102, 103 and 1 connected in series
Both ends of 04, 105 and 106 are connected. Each MOSFET
An AC terminal is taken out from the series connection point of the two MOSFETs in the group.

With the SiC MOSFET according to the present invention,
MOSFET with much lower loss than silicon can be realized, module loss can be reduced, and the efficiency of the inverter device can be improved. Further, by using a SiC Schottky diode as the diode, both the switching device and the diode become a unipolar type. Therefore, the speed of the inverter device can be further increased.

FIG. 10 is a sectional view of an embodiment of a trench type insulated gate bipolar transistor (hereinafter referred to as an IGBT) according to the present invention. In FIG. 10, in a SiC substrate in which an n ⁻ drift layer 2 and a p-type p base layer 3 are epitaxially grown on a p ⁺ substrate 9, a high concentration n ⁺ source region 4 is selectively formed on the surface layer of the p base layer 3. Is formed, and in a part of the n ⁺ source region 4, n ⁻ from the surface is formed.
A trench 5 reaching the drift layer 2 is formed. Inside the trench 5, a gate insulating film 6 made of a silicon oxide film is formed.
A gate electrode 13 of polycrystalline silicon is provided via the. A Ti—Al collector electrode 14 is provided on the back surface of the p ⁺ substrate 9. In this IGBT, a second trench 8 deeper than the surface of the p base layer 3 than the trench 5 in the gate portion, and a p ⁺ type region 7 are formed along the side surface and the bottom surface of the second trench 8. Then, from the p ⁺ type region 7 to the p base layer 3, n ⁺
An emitter electrode 15 made of Ti—Al that reaches the surface of the source region 4 is provided. The operation of the IGBT shown in FIG. 10 is such that when a positive voltage higher than a certain value is applied to the gate electrode 13 in a state where a voltage is applied between the collector electrode 14 and the emitter electrode 15, the p base layer next to the gate electrode 13 is applied. An inversion layer is formed on the surface layer of No. 3, and an electron current is injected from the emitter electrode 15 to the p base layer 3 through the inversion layer. This electron current causes the p base layer 3, the n ⁻ drift layer 2,
It becomes the base current of the bipolar transistor composed of the p ⁺ substrate 9, and the IGBT operates. I of FIG.
In the GBT, when a voltage is applied between the collector electrode 14 and the emitter electrode 15 and the voltage is increased, the p ⁺ type region 7
And the n ⁻ drift layer 2 and the depletion layer extending to the n ⁻ drift layer 2, the gate insulating film 6 and the n ⁻ drift layer 2 are formed.
The electric field strength at the interface of the drift layer 2 is relaxed. Therefore, the avalanche resistance of the IGBT is defined by the dielectric breakdown electric field strength of SiC, and the gate insulating film 6 is not destroyed. In other words, an IGB having a large avalanche withstanding capability that does not cause dielectric breakdown of the gate insulating film when a voltage is applied
It can be T.

In general, it is difficult to form a p-type region having low resistivity with SiC. This is aluminum,
This is because the p-type impurity such as boron has a deep impurity level of 200 meV to 300 meV, so that the activation rate of the impurity is extremely low. Therefore, the SiC IGBT has a drawback that it easily latches up. However, with the structure shown in FIG. 10, since a current flows through the p ⁺ type region 7, latch-up hardly occurs.

FIG. 11 shows an example of a main circuit of a power inverter device using the IGBT as a switching element according to the present invention. The IGBT of the present invention is applied to a portion surrounded by a broken line in the figure, that is, an antiparallel circuit portion of the IGBT and the diode. This inverter device has a pair of DC terminals 121 and 1
22 and three AC terminals 131 to 3 equal to the number of AC phases
133, the DC power supply is connected to the DC terminal, and the IGBT141
By switching ~ 146, DC power is converted into AC power and output to the AC terminal. Between the DC terminals,
Both ends of the series-connected IGBT pairs 101 and 102, 103 and 104, 105 and 106 are connected. Each IG
An alternating current terminal is taken out from the series connection point of two IGBTs in the set of BTs.

By using the SiC IGBT of the present invention, an IGBT having a much lower loss than that of silicon can be realized, the loss of the module can be reduced, and the efficiency of the inverter device can be improved.

[0023]

As described above, according to the SiC semiconductor device of the present invention, by providing the second trench deeper than the gate portion and the p-type region along the second trench, the p-type when voltage is applied. The depletion layer extending from the region relaxes the electric field strength applied to the gate insulating film. Therefore, it is possible to obtain a SiC trench MOSFET having a large avalanche withstanding capability in which the gate insulating film does not cause dielectric breakdown.

[Brief description of drawings]

FIG. 1 is a sectional structural view of a trench MOSFET according to an embodiment of the present invention.

FIG. 2 is an electric field strength distribution along XX ′ of the trench MOSFETs of FIGS. 1 and 5.

3A to 3C are cross-sectional structural views in the order of manufacturing steps for explaining the method for manufacturing the trench MOSFET in FIG.

FIG. 4 is a cross-sectional view of a trench MOSFET having a plurality of trench gates provided between second trenches.

FIG. 5 is a sectional structural view of a conventional trench MOSFET.

6 is an electric field strength distribution along XX ′ of the trench MOSFET of FIG.

FIG. 7 is a cross-sectional structure diagram of a trench MOSFET in which an electric field relaxation effect is enhanced.

FIG. 8 is a sectional structural view of a trench MOSFET arranged so that a p-type region intersects with a trench gate.

FIG. 9 is an example of a main circuit of a power inverter device to which the trench MOSFET of the present invention is applied.

FIG. 10 is a sectional view of a trench IGBT according to an embodiment of the present invention.

FIG. 11 is an embodiment of a main circuit of a power inverter device to which the trench IGBT of the present invention is applied.

[Explanation of symbols]

1 ... n ⁺ substrate, 2 ... n ^- drift layer, 3 ... p
Base layer, 4 ... N ⁺ source region, 5 ... Trench, 6 ... Gate insulating film, 7 ... P ⁺ type region, 8 ... Second trench, 9
... p ⁺ substrate, 11 ... drain electrode, 12 ... source electrode, 13 ... gate electrode, 14 ... collector electrode, 1
5 ... Emitter electrode, 101-106 ... MOSFET, 111-
116 ... Diode, 121, 122 ... DC terminal, 13
1-133 ... AC terminals, 141-146 ... IGBT.

─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-7-161983 (JP, A) JP-A-2-298073 (JP, A) JP-A-8-264772 (JP, A) (58) Field (Int.Cl. ⁷ , DB name) H01L 29/78 H01L 21/336

Claims (3)

(57) [Claims] 1. A silicon carbide semiconductor substrate of the first conductivity type,
A first conductivity type drift layer and a second conductivity type base layer formed in order, a first conductivity type source region formed in the second conductivity type base layer, and a first conductivity type from the surface of the first conductivity type source region. A first trench reaching the type drift layer, a gate electrode is provided in the first trench via an insulating film, and a second trench deeper than the first trench is provided. Tei comprising a second conductivity type region along the inner surface
Between the second trench adjacent to the second trench
Having at least two said first trenches
A silicon carbide semiconductor device characterized by: 2. A silicon carbide semiconductor substrate of the first conductivity type,
A first conductivity type drift layer and a second conductivity type layer formed in this order.
Source layer and the first conductivity type formed on the second conductivity type base layer
The source region and the surface of the first conductivity type source region are
Has a first trench reaching the electric drift layer,
A gate electrode is provided in the trench through an insulating film,
A second trench deeper than the first trench
Features a second conductivity type region along the inner surface of the trench
Te, wherein the first trench and, silicon carbide semiconductor device, characterized in that said deeper than the first trench a second trench is arranged in a direction intersecting. 3. The odor according to claim 1 or claim 2.
And that the silicon carbide semiconductor device is a MOSFET.
And a silicon carbide semiconductor device.