JP5439856B2 - Insulated gate field effect transistor - Google Patents

Description

  The present invention relates to an insulated gate field effect transistor, and more particularly to an insulated gate field effect transistor having excellent switching speed.

  In recent years, with the improvement in performance of devices in which insulated gate field effect transistors (MISFETs) are used, MISFETs are required to have improved breakdown voltage and reduced loss. In response to this, many studies have been made and various countermeasures have been proposed (for example, see Patent Document 1).

Here, the structure of a conventional MISFET will be described. FIG. 25 is a schematic plan view showing the structure of a conventional MISFET. FIG. 26 is a schematic cross-sectional view taken along line XXVI-XXVI in FIG. FIG. 27 is a schematic sectional view taken along line XXVII-XXVII in FIG. Referring to FIGS. 26 and 27, conventional MISFET 100 is made of a semiconductor and has an n ⁺ substrate 110 that is an n-type substrate, an n ⁻ semiconductor layer 120 that has an n-type conductivity, and a conductivity type that is n-type. p body 121 which is p type, n ⁺ source region 122 whose conductivity type is n type, p ⁺ region 123 whose conductivity type is p type, gate oxide film 130, gate electrode 140, and contact electrode 180. A source electrode 160 and a drain electrode 170. The n ⁻ semiconductor layer 120 is formed on one main surface of the n ⁺ substrate 110 and has an n-type conductivity by containing an n-type impurity (an impurity whose conductivity type is n-type).

In the n ⁻ semiconductor layer 120, the p body 121 is formed so as to include a second main surface 120B that is a main surface opposite to the first main surface 120A that is the main surface on the n ⁺ substrate 110 side, By including p-type impurities (impurities whose conductivity type is p-type), the conductivity type is p-type. N ⁺ source region 122 includes second main surface 120 ^</ b ^> B and is formed inside p body 121 so as to be surrounded by p body 121. The n ⁺ source region 122 contains an n-type impurity at a higher concentration than the n-type impurity contained in the n ⁻ semiconductor layer 120.

P ⁺ region 123 is formed inside p body 121 so as to include second main surface 120 ^</ b> B and to be surrounded by n ⁺ source region 122. The p ⁺ region 123 contains a p-type impurity at a higher concentration than the p-type impurity contained in the p body 121.

Gate oxide film 130 is in contact with second main surface 120B, from a region covering n ⁺ source region 122 to a region covering p body 121 (a region where n ⁺ source region 122 is not formed) and n ^−. It is formed so as to extend to a region covering the semiconductor layer 120 (a region where the p body 121 is not formed). Gate electrode 140 is in contact with gate oxide film 130, from a region covering n ⁺ source region 122 to a region covering p body 121 (a region where n ⁺ source region 122 is not formed) and n ⁻ semiconductor layer 120. It is formed to extend to a region covering the top (region where p body 121 is not formed).

Contact electrode 180 is formed on second main surface 120B so as to be in contact with n ⁺ source region 122 and p ⁺ region 123. In plan view, referring to FIG. 25, contact electrode 180 is formed in n ⁺ source region 122 and p ⁺ region 123 formed inside p body 121 in contact region 121 A surrounded by p body 121. In contact. More specifically, contact electrode 180 is in contact with p ⁺ region 123 in contact region 121 ^</ b ^> C located at the center of p body 121. Referring to FIGS. 26 and 27, source electrode 160 is formed on contact electrode 180 on second main surface 120 </ b> B so as to be in contact with contact electrode 180. Drain electrode 170 is formed in contact with the main surface of n ⁺ substrate 110 opposite to the side on which n ⁻ semiconductor layer 120 is formed.

Next, the operation of the MISFET 100 will be described. Referring to FIG. 26, in a state where the voltage of gate electrode 140 is equal to or lower than a threshold value, that is, in an off state, a reverse bias is applied between p well 121 located immediately below gate oxide film 130 and n ⁻ semiconductor layer 120, It becomes a conductive state. On the other hand, when a positive voltage is applied to the gate electrode 140, an inversion layer is formed in the channel region 121D in the vicinity of the p well 121 in contact with the gate oxide film 130. As a result, the n ⁺ source region 122 and the n ⁻ semiconductor layer 120 are electrically connected, and a current flows between the source electrode 160 and the drain electrode 170.

International Publication No. 02/43157 Pamphlet

  Referring to FIGS. 25 to 27, when the current of MISFET 100 rises (when switching from the off state to the on state), electrons serving as carriers are paths of source electrode 160, contact electrode 180, and p body 121. Are sequentially supplied to the channel region 121D. On the other hand, when the current of MISFET 100 falls (when switching from the on state to the off state), electrons as carriers disappear in the order of channel region 121D, p body 121, contact electrode 180, and source electrode 160.

Here, referring to FIG. 25, in conventional MISFET 100, contact electrode 180 contacts p ⁺ region 123 in contact region 121C located at the center of p body 121 (center of the cell), while channel region 121D. Is formed near the outer periphery of the p body 121 (near the outer periphery of the cell). Therefore, the path from the region where electrons are supplied by the contact electrode 180 to the channel region 121D is relatively long. In addition, the resistivity of the p body 121 including the path is relatively high. As a result, the movement of electrons (carriers) at the time of rising and falling of the current is restricted, and improvement in switching speed is hindered. That is, the conventional MISFET has a problem in that since the distance between the region where the carrier is supplied from the electrode and the channel region is large, the time required for carrier movement becomes long and the switching speed is not sufficiently improved.

  Accordingly, an object of the present invention is to provide an insulated gate field effect transistor in which the switching speed is sufficiently improved by suppressing the time required for carrier movement.

An insulated gate field effect transistor according to the present invention includes a substrate, a semiconductor layer of a first conductivity type formed on the substrate, a second conductivity type region of a second conductivity type different from the first conductivity type, A high-concentration first conductivity type region containing a first conductivity-type impurity at a higher concentration than the semiconductor layer, a first electrode, and a second electrode are provided. The semiconductor layer is formed on a substrate. The second conductivity type region is formed so as to include a second main surface which is a main surface opposite to the first main surface which is the main surface on the substrate side in the semiconductor layer. The second conductivity type is different from the type. The high-concentration first conductivity type region includes the second main surface and is formed inside the second conductivity type region. The first electrode is in contact with the high concentration first conductivity type region in the first contact region included in the second main surface in the high concentration first conductivity type region. The second electrode is in contact with the second conductivity type region in the second contact region which is on the outer peripheral side of the first contact region and is included in the second main surface in the second conductivity type region. ing. Further, the insulated gate field effect transistor according to the present invention is formed so as to include the second main surface inside the second conductivity type region and on the outer peripheral side of the high concentration first conductivity type region. The semiconductor device further includes a first high-concentration second conductive type region containing a second conductive type impurity having a higher concentration than the conductive type region. The first high-concentration second conductivity type region is formed at a distance from the high-concentration first conductivity type region. And in the 2nd main surface, the 2nd contact field has overlapped with the 1st high concentration 2nd conductivity type field.

The insulated gate field effect transistor of the present invention includes a second electrode in contact with the second conductivity type region in the second contact region located on the outer peripheral side of the first contact region. Accordingly, carriers are supplied from the second electrode in the vicinity of the outer periphery of the second conductivity type region where the channel region is formed. Therefore, the path from the region to which the carrier is supplied to the channel region can be shortened. As a result, according to the insulated gate field effect transistor of the present invention, it is possible to provide an insulated gate field effect transistor in which the switching speed is sufficiently improved by suppressing the time required for carrier movement. Further, since the second electrode comes into contact with the first high concentration second conductivity type region that is easy to secure an ohmic contact by containing a high concentration second conductivity type impurity, It becomes easy to maintain the two conductivity type region at a desired potential.

  In the insulated gate field effect transistor of the present invention, preferably, the second conductivity type region has a polygonal shape having three or more vertices on the second main surface. The second contact region is arranged on the second main surface so as to include a region on the center of gravity side as viewed from the vertex on a straight line connecting the center of gravity of the polygon and the vertex.

  In a plan view, when the second conductivity type region has a polygonal shape, the channel along the side of the second conductivity type region is defined as a channel region so that the channel length is stable. A gate type field effect transistor can be easily manufactured. At this time, by arranging the second contact area on the straight line so as to include the area on the center of gravity side when viewed from the vertex of the polygon, the second contact area is arranged near the vertex of the polygon. Thus, the second electrode can be formed while avoiding interference with the channel region.

  In the insulated gate field effect transistor of the present invention, the second conductivity type region may have a quadrangular shape on the second main surface. Thereby, an insulated gate field effect transistor with a stable channel length can be more easily manufactured. In particular, a plurality of insulated gate field effect transistors are arranged without gaps by making the shape of the second conductivity type region on the second main surface a square having sides parallel to each other, such as a square, a rectangle, a parallelogram, and a trapezoid. Therefore, a large-area insulated gate field effect transistor chip capable of switching a large current can be easily manufactured.

  In the insulated gate field effect transistor of the present invention, the second conductivity type region may have a hexagonal shape on the second main surface. Thereby, it becomes easy to provide more second contact regions, and the switching speed can be further improved. In particular, by making the shape of the second conductivity type region on the second main surface a regular hexagon, a plurality of insulated gate field effect transistors can be arranged without gaps, and the electric field concentration at the apex of the second conductivity type region Therefore, it is possible to easily manufacture an insulated gate field effect transistor chip having a large area and high withstand voltage capable of switching a large current.

An insulated gate field effect transistor according to the present invention includes a substrate, a semiconductor layer of a first conductivity type formed on the substrate, a second conductivity type region of a second conductivity type different from the first conductivity type, A high-concentration first conductivity type region containing a first conductivity-type impurity at a higher concentration than the semiconductor layer, a first electrode, and a second electrode are provided. The semiconductor layer is formed on a substrate. The second conductivity type region is formed so as to include a second main surface which is a main surface opposite to the first main surface which is the main surface on the substrate side in the semiconductor layer. The second conductivity type is different from the type. The high-concentration first conductivity type region includes the second main surface and is formed inside the second conductivity type region. The first electrode is in contact with the high concentration first conductivity type region in the first contact region included in the second main surface in the high concentration first conductivity type region. The second electrode is in contact with the second conductivity type region in the second contact region which is on the outer peripheral side of the first contact region and is included in the second main surface in the second conductivity type region. ing. The insulated gate field effect transistor according to the present invention further includes a third electrode in contact with the second conductivity type region in the third contact region included in the second main surface surrounded by the first contact region. And a second high-concentration second conductive type region that is formed in the second conductive type region and is in contact with the third electrode, the second conductive type region including a second conductive type impurity at a higher concentration than the second conductive type region. Is further provided.

  Thereby, the withstand voltage of the insulated gate field effect transistor can be stabilized. Here, the third electrode and the first electrode may be separate from each other or may be integrally formed.

  In the insulated gate field effect transistor of the present invention, preferably, the semiconductor layer is made of silicon carbide or gallium nitride. By using silicon carbide or gallium nitride, which is a wide band gap semiconductor having a larger band gap than silicon, as the material of the semiconductor layer, it is possible to achieve high breakdown voltage and low loss of the insulated gate field effect transistor. However, when a wide band gap semiconductor with a large band gap and a low intrinsic carrier density is used as the material of the semiconductor layer, there is a problem with the switching speed due to the large distance between the region to which the carrier is supplied and the channel region. It becomes even more prominent. Therefore, the insulated gate field effect transistor of the present invention that can alleviate the problem is suitable for an insulated gate field effect transistor that employs silicon carbide or gallium nitride as the material of the semiconductor layer.

  As is apparent from the above description, according to the insulated gate field effect transistor of the present invention, there is provided an insulated gate field effect transistor in which the switching speed is sufficiently improved by suppressing the time required for carrier movement. can do.

FIG. 3 is a schematic plan view showing the arrangement of MOSFET electrodes in the first embodiment. It is a schematic sectional drawing in alignment with line segment II-II of FIG. It is a schematic sectional drawing in alignment with line segment III-III of FIG. 3 is a flowchart showing an outline of a method for manufacturing a MOSFET in the first embodiment. FIG. 6 is a schematic cross sectional view for illustrating the method for manufacturing the MOSFET in the first embodiment. FIG. 6 is a schematic cross sectional view for illustrating the method for manufacturing the MOSFET in the first embodiment. FIG. 6 is a schematic cross sectional view for illustrating the method for manufacturing the MOSFET in the first embodiment. FIG. 6 is a schematic cross sectional view for illustrating the method for manufacturing the MOSFET in the first embodiment. FIG. 6 is a schematic cross sectional view for illustrating the method for manufacturing the MOSFET in the first embodiment. FIG. 6 is a schematic cross sectional view for illustrating the method for manufacturing the MOSFET in the first embodiment. FIG. 6 is a schematic cross sectional view for illustrating the method for manufacturing the MOSFET in the first embodiment. FIG. 6 is a schematic cross sectional view for illustrating the method for manufacturing the MOSFET in the first embodiment. FIG. 6 is a schematic cross sectional view for illustrating the method for manufacturing the MOSFET in the first embodiment. FIG. 6 is a schematic cross sectional view for illustrating the method for manufacturing the MOSFET in the first embodiment. FIG. 6 is a schematic cross sectional view for illustrating the method for manufacturing the MOSFET in the first embodiment. FIG. 6 is a schematic cross sectional view for illustrating the method for manufacturing the MOSFET in the first embodiment. FIG. 10 is a schematic plan view showing the arrangement of MOSFET electrodes in the second embodiment. It is a schematic sectional drawing in alignment with line segment XVIII-XVIII of FIG. It is a schematic sectional drawing in alignment with line segment XIX-XIX of FIG. FIG. 10 is a schematic cross sectional view for illustrating the method for manufacturing the MOSFET in the second embodiment. FIG. 10 is a schematic cross sectional view for illustrating the method for manufacturing the MOSFET in the second embodiment. FIG. 10 is a schematic cross sectional view for illustrating the method for manufacturing the MOSFET in the second embodiment. FIG. 10 is a schematic cross sectional view for illustrating the method for manufacturing the MOSFET in the second embodiment. FIG. 10 is a schematic plan view showing the arrangement of MOSFET electrodes in the third embodiment. It is a schematic plan view which shows the structure of the conventional MISFET. FIG. 26 is a schematic sectional view taken along line XXVI-XXVI in FIG. 25. It is a schematic sectional drawing in alignment with line segment XXVII-XXVII of FIG.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following drawings, the same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated.

(Embodiment 1)
First, an oxide film field effect transistor (MOSFET), which is an insulated gate field effect transistor in the first embodiment, will be described with reference to FIGS.

1 to 3, MOSFET 1 according to the first embodiment is made of SiC (silicon carbide) which is a wide band gap semiconductor, and is an n ⁺ SiC which is an n-type (first conductivity type) substrate. A substrate 10, an n ⁻ SiC layer 20 as a semiconductor layer whose conductivity type is n-type (first conductivity type), and a p body 21 as a second conductivity-type region whose conductivity type is p-type (second conductivity type). The n ⁺ source region 22 as a high-concentration first conductivity type region having a conductivity type of n-type (first conductivity type) and a first high-concentration second conductivity type having a conductivity type of p-type (second conductivity type) And a p ⁺ region 23 as a region. The n ⁺ SiC substrate 10 is made of, for example, hexagonal SiC and includes a high concentration of n-type impurities (impurities whose conductivity type is n-type). The n ⁻ SiC layer 20 is formed on one main surface of the n ⁺ SiC substrate 10 and has an n-type conductivity by including an n-type impurity. The n-type impurity contained in the n ⁻ SiC layer 20 is N (nitrogen), for example, and is contained at a lower concentration than the n-type impurity contained in the n ⁺ SiC substrate 10.

The p body 21 is formed to include a second main surface 20B that is a main surface opposite to the first main surface 20A that is the main surface on the n ⁺ SiC substrate 10 side in the n ⁻ SiC layer 20. , P-type impurities (impurities whose conductivity type is p-type) are included, so that the conductivity type is p-type (second conductivity type). The p-type impurity contained in the p body 21 is, for example, aluminum (Al), boron (B) or the like, and is contained at a lower concentration than the n-type impurity contained in the n ⁺ SiC substrate 10.

N ⁺ source region 22 includes second main surface 20 ^</ b ^> B and is formed inside p body 21 so as to be surrounded by p body 21. Here, n ⁺ source region 22 is formed immediately below first contact region 21 ^</ b ^{> A} included in second main surface 20 ^</ b ^> B in p body 21. The n ⁺ source region 22 contains an n-type impurity such as P, As, etc. at a higher concentration than the n-type impurity contained in the n ⁻ SiC layer 20.

P ⁺ region 23 is formed inside p body 21 and on the outer peripheral side of n ⁺ source region 22 so as to include second main surface 20B. Here, referring to FIG. 1, p body 21 has a quadrangular (square) shape on second main surface 20B. Then, the p ⁺ region 23 includes a region on the centroid α side of the second main surface 20B on the straight line β connecting the centroid α and each vertex of the p body 21 having a quadrangular shape as viewed from the vertex. Is formed immediately below the second contact region 21B. In addition, p ⁺ region 23 contains a p-type impurity, such as Al or B, at a higher concentration than the p-type impurity contained in p body 21.

  1 to 3, MOSFET 1 includes a gate oxide film 30 as an insulating film, a gate electrode 40, an interlayer insulating film 50, a contact electrode 80, a source electrode 60, and a drain electrode 70. It has.

Gate oxide film 30 is in contact with second main surface 20B, from a region covering n ⁺ source region 22 to a region covering p body 21 (a region where n ⁺ source region 22 is not formed) and n ^−. It is formed to extend to a region (region where p body 21 is not formed) covering SiC layer 20. Gate oxide film 30 is made of, for example, silicon dioxide (SiO ₂ ).

Gate electrode 40 is in contact with gate oxide film 30, from a region covering n ⁺ source region 22 to a region covering p body 21 (a region where n ⁺ source region 22 is not formed) and n ⁻ SiC layer 20. It is formed to extend to a region covering the top (region where p body 21 is not formed). The gate electrode 40 is made of a conductor such as polysilicon or Al. That is, the gate oxide film 30 as a gate insulating film made of an insulator covers the region other than the first contact region 21A and the second contact region 21B in the p body 21 on the second main surface 20B. , Formed on the second main surface 20B. The gate electrode 40 is made of a conductor and is disposed on the gate oxide film 30.

Contact electrode 80 is formed in contact with n ⁺ source region 22 and p ⁺ region 23 on second main surface 20B. More specifically, referring to FIG. 1 and FIG. 3, contact electrode 80 has n ⁺ in p body 21 in first contact region 21 ^</ b> A included in second main surface 20 ^</ b ^> B in p body 21. In the first contact electrode 80A in contact with the source region 22 and the second contact region 21B on the outer peripheral side of the first contact region 21A and included in the second main surface 20B in the p body 21, p And a second contact electrode 80B in contact with the p ⁺ region 23 in the body 21. Contact electrode 80 is made of a material capable of ohmic contact with n ⁺ source region 22 and p ⁺ region 23 such as NiSi (nickel silicide), for example.

  Source electrode 60 is formed on contact electrode 80 on second main surface 20 </ b> B so as to be in contact with contact electrode 80. The source electrode 60 is made of a conductor such as Al.

Drain electrode 70 is formed in contact with the main surface of n ⁺ SiC substrate 10 opposite to the side on which n ⁻ SiC layer 20 is formed. The drain electrode 70 is made of a material capable of ohmic contact with the n ⁺ SiC substrate 10 such as NiSi, and is electrically connected to the n ⁺ SiC substrate 10.

Interlayer insulating film 50 is arranged on gate oxide film 30 so as to surround gate electrode 40. The interlayer insulating film 50 is made of an insulator such as SiO ₂ . Thereby, the gate electrode 40 and the source electrode 60 are insulated.

That is, MOSFET 1 as an insulated gate field effect transistor in the first embodiment includes n ⁺ SiC substrate 10, n ⁻ SiC layer 20 as an n-type semiconductor layer formed on n ⁺ SiC substrate 10, n ^- in SiC layer ^20, n + SiC first major surface 20A and formed p-type p body to include second main surface 20B which is the main surface opposite to a main surface of the substrate 10 side 21. Further, MOSFET 1 includes first contact electrode 80A that contacts p body 21 and the outer peripheral side of first contact region 21A in first contact region 21A included in second main surface 20B in p body 21. In the second contact region 21B included in the second main surface 20B in the p body 21, a second contact electrode 80B that contacts the p body 21 is provided.

  Further, p body 21 has a polygonal quadrangular shape on second main surface 20B. The second contact region 21B is arranged on the second main surface 20B so as to include a region on the centroid α side as viewed from the vertex on the straight line β connecting the centroid α and the vertex of the square. Yes.

Next, the operation of MOSFET 1 will be described. Referring to FIG. 2, in a state where the voltage of gate electrode 40 is equal to or lower than a threshold value, that is, in an off state, a reverse bias is applied between p body 21 and n ⁻ SiC layer 20 located immediately below gate oxide film 30, It becomes a conductive state. On the other hand, when a positive voltage is applied to the gate electrode 40, an inversion layer is formed in the channel region 21 </ b> D in the vicinity of contacting the gate oxide film 30 of the p body 21. As a result, n ⁺ source region 22 and n ⁻ SiC layer 20 are electrically connected, and a current flows between source electrode 60 and drain electrode 70.

Here, referring to FIGS. 1 to 3, MOSFET 1 of the present embodiment includes p ⁺ region 23 in p body 21 in second contact region 21 ^</ b ^> B located on the outer peripheral side of first contact region 21 ^</ b ^> A. The second contact electrode 80B is provided in contact with. That is, in MOSFET 1 of the present embodiment, second contact electrode 80B is in contact with p ⁺ region 23 in p body 21 in second contact region 21B arranged so as to sandwich channel region 21D. . Thus, electrons as carriers are supplied from the second contact electrode 80B in the vicinity of the outer periphery of the p body 21 where the channel region 21D is located. Therefore, the path from the region to which electrons are supplied to the channel region 21D can be shortened. As a result, the MOSFET 1 of the present embodiment is an insulated gate field effect transistor with improved switching speed because the time required for movement of electrons as carriers is suppressed.

  In MOSFET 1 of the present embodiment, p body 21 has a quadrangular shape on second main surface 20B. Since the region along the side of the p body 21 is the channel region 21D, it is easy to stabilize the channel length during manufacturing. Furthermore, since the second contact region 21B is arranged on the straight line β connecting the center of gravity α and the apex of the p body 21 having a quadrangular shape so as to include the region on the side of the center of gravity α when viewed from the apex, the channel The second contact electrode 80B is formed while avoiding interference with the region 21D.

  Next, with reference to FIGS. 4-16, the manufacturing method of MOSFET in Embodiment 1 which is one Embodiment of the manufacturing method of the insulated gate field effect transistor according to this invention is demonstrated. 5 to 16, the figures assigned with odd number numbers correspond to the same cross section as in FIG. 2 described above, and the figures assigned with even number figure numbers correspond to the same cross section as in FIG. 3 described above. Correspond.

Referring to FIG. 4, in the method of manufacturing an insulated gate field effect transistor in the first embodiment, first, a substrate preparation step is performed as a step (S10). In this step (S10), a first conductivity type substrate is prepared. Specifically, referring to FIG. 5 and FIG. 6, an n ⁺ SiC substrate 10 made of, for example, hexagonal SiC and containing an n-type impurity and having an n-type conductivity and having an n-type conductivity of (0001) plane is 8 ° off. Be prepared.

Next, with reference to FIG. 4, an n ⁻ layer forming step is performed as a step (S20). In this step (S ^< b> 20), a first conductivity type semiconductor layer is formed on n ⁺ SiC substrate 10. Specifically, referring to FIG. 5 and FIG. 6, n ⁻ SiC layer 20 is formed on n ⁺ SiC substrate 10 by epitaxial growth. Epitaxial growth can be performed, for example, by using a mixed gas of SiH ₄ (silane) and C ₃ H ₈ (propane) as a source gas. At this time, for example, nitrogen is introduced as an n-type impurity. Thereby, the n ⁻ SiC layer 20 containing the n-type impurity having a lower concentration than the n-type impurity contained in the n ⁺ SiC substrate 10 can be formed. The impurity concentration to be introduced may be about 1.0 × 10 ¹⁶ cm ⁻³ , for example, and the thickness of the n ⁻ SiC layer 20 to be grown may be about 10 μm.

Next, referring to FIG. 4, a p body forming step is performed as a step (S30). In this step (S30), the n ⁻ SiC layer 20 includes the second main surface 20B that is the main surface opposite to the first main surface 20A that is the main surface on the n ⁺ SiC substrate 10 side. A second conductivity type region of the second conductivity type is formed. Specifically, referring to FIGS. 7 and 8, first, oxide film 93 made of SiO ₂ is formed on second main surface 20B by, for example, CVD (Chemical Vapor Deposition). Then, after a resist is applied on oxide film 93, exposure and development are performed, and a resist film having an opening in a region corresponding to the shape of p body 21 as a desired second conductivity type region is formed. . Then, using the resist film as a mask, the oxide film is partially removed by, for example, RIE (Reactive Ion Etching), whereby oxide film 93 having an opening pattern on n ⁻ SiC layer 20. A mask layer is formed. Thereafter, after removing the resist film, ion implantation is performed on the n ⁻ SiC layer 20 using the mask layer as a mask, whereby the p body 21 is formed in the n ⁻ SiC layer 20. Here, in ion implantation, for example, Al is adopted as a p-type impurity, and a p body 21 having a depth of about 0.8 μm and an impurity concentration of about 5.0 × 10 ¹⁶ cm ⁻³ can be formed.

Next, with reference to FIG. 4, an n ⁺ region forming step is performed as a step (S40). In this step (S40), a high concentration first conductivity type region containing a first conductivity type impurity having a concentration higher than that of n ⁻ SiC layer 20 is formed in a region including second main surface 20B in p body 21. Is done. Specifically, referring to FIG. 9 and FIG. 10, first, according to the same procedure as in the above-described step (S30), the n ⁺ source region 22 as the desired high-concentration first conductivity type region is formed. A mask layer made of oxide film 93 having an opening pattern is formed. Then, n-type impurities are introduced into the n ⁻ SiC layer 20 by ion implantation using the mask layer as a mask. As a result, the n ⁺ source region 22 as the high concentration first conductivity type region is formed. Here, in the ion implantation, for example, P is adopted as the n-type impurity, and the n ⁺ source region 22 having a depth of about 0.3 μm and an impurity concentration of about 1.0 × 10 ¹⁹ cm ⁻³ can be formed.

Next, referring to FIG. 4, a p ⁺ region forming step is performed as a step (S50). In this step (S50), a high-concentration second conductivity type region containing a second conductivity type impurity having a concentration higher than that of p body 21 is formed in a region including second main surface 20B in p body 21. . Specifically, referring to FIG. 11 and FIG. 12, an opening pattern corresponding to the shape of p ⁺ region 23 as a desired high-concentration second conductivity type region by the same procedure as in the step (S30). A mask layer made of the oxide film 93 having the above is formed. Then, using the mask layer as a mask, p-type impurities are introduced into the n ⁻ SiC layer 20 by ion implantation. As a result, ap ⁺ region 23 is formed as a high concentration second conductivity type region. Here, in ion implantation, for example, Al is adopted as a p-type impurity, and a p ⁺ region 23 having a depth of about 0.4 μm and an impurity concentration of about 1.0 × 10 ¹⁹ cm ⁻³ can be formed.

Next, referring to FIG. 4, an activation annealing step is performed as a step (S60). In this step (S60), activation annealing, which is a heat treatment for activating the introduced impurities, is performed by heating the n ⁻ SiC layer 20 subjected to the ion implantation in steps (S30) to (S50). The The activation annealing can be performed, for example, by performing a heat treatment that is held at a temperature of about 1700 ° C. for about 30 minutes in an argon gas atmosphere.

Next, referring to FIG. 4, an oxide film forming step is performed as a step (S70). In this step (S70), with reference to FIGS. 13 and 14, steps (S10) to (S60) are performed, and the n ⁺ SiC substrate on which n ⁻ SiC layer 20 including a desired ion implantation layer is formed is formed. 10 is thermally oxidized. Thereby, a thermal oxide film 92 made of silicon dioxide (SiO ₂ ) and to be the gate oxide film 30 (see FIGS. 2 and 3) is formed so as to cover the second main surface 20B. This thermal oxidation can be performed, for example, by heating the n ⁺ SiC substrate 10 to 1300 ° C. in an oxygen atmosphere and holding it for 30 minutes.

Next, referring to FIG. 4, an ohmic electrode forming step is performed as a step (S80). In this step (S80), referring to FIG. 2 and FIG. 3, contact electrode 80 in contact with n ⁺ source region 22 and p ⁺ region 23 on second main surface 20B and n ⁺ SiC substrate 10 has n ^- a drain electrode 70 in contact with the main surface on the opposite side is formed to the side where the SiC layer 20 is formed. Specifically, referring to FIGS. 15 and 16, after a resist is applied on second main surface 20 </ b> B, exposure and development are performed, and an opening is formed in a region corresponding to the shape of desired contact electrode 80. A resist film 91 is formed. Then, using the resist film 91 as a mask, the thermal oxide film 92 is partially removed by RIE, for example. As a result, the thermal oxide film 92 remains in the region where the gate oxide film 30 is to be formed.

Thereafter, as shown in FIGS. 15 and 16, Ni film 94 made of Ni is formed on second main surface 20B and the main surface opposite to n ⁻ SiC layer 20 of n ⁺ SiC substrate 10, for example, It is formed by a vapor deposition method. Further, by removing resist film 91, Ni film 94 on resist film 91 is removed (lifted off), and on second main surface 20B exposed from thermal oxide film 92 and n ⁺ SiC substrate 10 n ^The Ni film 94 remains on the main surface opposite to the SiC layer 20. Further, the n + SiC substrate 10 on which the Ni film 94 is formed is heated to, for example, 950 ° C. for 2 minutes in an inert gas atmosphere such as Ar, whereby the Ni film 94 is silicided. Through the above steps, the contact electrode 80 and the drain electrode 70 (see FIGS. 2 and 3) made of NiSi are completed.

  Next, with reference to FIG. 4, a gate electrode formation process is implemented as process (S90). In this step (S90), gate electrode 40 (see FIGS. 2 and 3) made of, for example, polysilicon, which is a conductor, or the like is formed on gate oxide film 30 so as to be in contact with gate oxide film 30. The Specifically, referring to FIGS. 2 and 3, first, a polysilicon film is formed on second main surface 20B by, for example, CVD. Then, for example, a resist film having an opening in a portion other than the shape of the desired gate electrode is formed on the polysilicon film by photolithography. Then, the polysilicon film is partially removed by RIE using the resist film as a mask, whereby the gate electrode 40 is formed.

Next, referring to FIG. 4, an interlayer insulating film forming step is performed as a step (S100). In this step (S100), an interlayer insulating film 50 (see FIGS. 2 and 3) made of, for example, SiO ₂ that is an insulator is formed on the gate oxide film 30 so as to surround the gate electrode 40. Specifically, referring to FIG. 2 and FIG. 3, a SiO ₂ film to be interlayer insulating film 50 is formed on second main surface 20B by, for example, plasma CVD.

Next, with reference to FIG. 4, a wiring formation process is implemented as process (S110). In this step (S110), a source electrode 60 (see FIGS. 2 and 3) made of, for example, Al as a conductor is formed on contact electrode 80 so as to be in contact with contact electrode 80. Specifically, referring to FIGS. 2 and 3, first, an opening is formed in a region on contact electrode 80 by photolithography on SiO ₂ film to be interlayer insulating film 50 formed in the step (S100). A resist film is formed. Then, the SiO ₂ film is partially removed by RIE using the resist film as a mask. Thereafter, an Al film made of Al is formed by sputtering, for example, and etched to have a desired shape, whereby the source electrode 60 is formed. Through the above steps (S10) to (S110), the manufacturing process of MOSFET 1 as the insulated gate field effect transistor in the first embodiment is completed, and MOSFET 1 in the first embodiment (see FIGS. 1 to 3) is completed. .

(Embodiment 2)
Next, a second embodiment of the present invention will be described. 17 to 19, MOSFET 1 in the second embodiment and MOSFET 1 in the first embodiment described with reference to FIGS. 1 to 3 basically have the same configuration and operate in the same manner. And has the same effect. However, MOSFET 1 in the second embodiment is different from MOSFET 1 in the first embodiment in the arrangement of p ⁺ region 23.

That is, referring to FIGS. 17 to 19, in MOSFET 1 according to the second embodiment, the first contact is formed in third contact region 21 </ b> C formed in p body 21 and surrounded by first contact region 21 </ b> A. A p ⁺ region 23 is further provided as a second high-concentration second conductivity type region in contact with the electrode 80A. That is, MOSFET 1 in the second embodiment contacts p body 21 as the second conductivity type region in third contact region 21C included in second main surface 20B surrounded by first contact region 21A. A first contact electrode 80A serving as a third electrode, and a p ⁺ region 23 containing a p-type impurity at a higher concentration than p body 21 and formed in p body 21 and in contact with first contact electrode 80A; Is further provided.

  Thereby, compared with the case of the first embodiment, the withstand voltage of the MOSFET 1 of the second embodiment is stable. Here, in the present embodiment, the first contact electrode 80A is arranged to serve as both the third electrode and the first electrode of the present invention.

  Next, with reference to FIGS. 20-23, the manufacturing method of MOSFET in Embodiment 2 which is one Embodiment of the manufacturing method of the insulated gate field effect transistor according to this invention is demonstrated. 20 and 22 correspond to the same cross section as FIG. 18 described above, and FIGS. 21 and 23 correspond to the same cross section as FIG. 19 described above.

The MOSFET manufacturing method according to the second embodiment can be basically performed in the same manner as in the first embodiment described with reference to FIGS. However, the MOSFET manufacturing method in the second embodiment is different from the first embodiment in the formation of the p ⁺ region 23.

That is, referring to FIG. 4, in the MOSFET manufacturing method in the second embodiment, first, steps (S10) to (S40) are performed in the same manner as in the first embodiment. Thereafter, in step (S50), referring to FIGS. 20 and 21, according to the same procedure as in step (S30), depending on the shape of p ⁺ region 23 as a desired high-concentration second conductivity type region. A mask layer made of oxide film 93 having an opening pattern is formed. At this time, in the second embodiment, a mask layer having an opening is also formed on the second main surface 20B on the region surrounded by the n ⁺ source region 22 in the p body 21. Then, using the mask layer as a mask, p-type impurities are introduced into the n ⁻ SiC layer 20 by ion implantation. As a result, the p ⁺ region 23 as the high-concentration second conductivity type region is also formed in the n ⁺ source region 22.

  Next, in the MOSFET manufacturing method in the second embodiment, steps (S60) and (S70) are performed in the same manner as in the first embodiment. Thereafter, in step (S80), referring to FIG. 22 and FIG. 23, after a resist is applied onto second main surface 20B, exposure and development are performed, depending on the desired shape of contact electrode 80. A resist film 91 having an opening in the region is formed. Then, using the resist film 91 as a mask, the thermal oxide film 92 is partially removed by RIE, for example. As a result, the thermal oxide film 92 remains in the region where the gate oxide film 30 is to be formed.

Thereafter, as shown in FIGS. 22 and 23, Ni film 94 made of Ni is formed on second main surface 20B and on the main surface opposite to n ⁻ SiC layer 20 of n ⁺ SiC substrate 10, for example, It is formed by a vapor deposition method. Further, by removing resist film 91, Ni film 94 on resist film 91 is removed (lifted off), and on second main surface 20B exposed from thermal oxide film 92 and n ⁺ SiC substrate 10 n ^The Ni film 94 remains on the main surface opposite to the SiC layer 20. At this time, in the second embodiment, the first contact electrode is in contact with the p body 21 in the third contact region 21C included in the second main surface 20B surrounded by the first contact region 21A. A Ni film 94 to be 80A is formed. Then, the Ni film 94 is silicided as in the first embodiment, whereby the contact electrode 80 and the drain electrode 70 (see FIGS. 18 and 19) are completed. Thereafter, referring to FIG. 4, steps (S90) to (S110) are performed in the same manner as in the first embodiment, thereby completing MOSFET 1 in the second embodiment (see FIGS. 17 to 19). To do.

(Embodiment 3)
Next, a third embodiment of the present invention will be described. MOSFET 1 in the third embodiment and MOSFET 1 in the first embodiment have basically the same configuration, operate in the same way, and produce the same effect. However, referring to FIG. 24 and FIG. 1, MOSFET 1 in the third embodiment is different from MOSFET 1 in the first embodiment in the planar shape of p body 21.

  That is, referring to FIG. 24, p body 21 of MOSFET 1 in the third embodiment has a hexagonal shape on second main surface 20B. The second contact region 21B is arranged on the second main surface 20B so as to include a region on the centroid α side as viewed from the vertex on the straight line β connecting the hexagonal centroid α and the vertex. ing.

  Thereby, the second contact region 21B is arranged more densely on the second main surface 20B, so that the switching speed of the MOSFET 1 can be further improved. Note that MOSFET 1 in the third embodiment can be manufactured by the same procedure as in the first embodiment.

  In the above embodiment, the case where the substrate and the semiconductor layer are made of SiC has been described as an example of the insulated gate field effect transistor of the present invention. However, the insulated gate field effect transistor of the present invention is not limited to this. As a material for the substrate and the semiconductor layer in the insulated gate field effect transistor of the present invention, various wide band gap semiconductors such as GaN (gallium nitride) can be adopted in addition to Si.

  The embodiment disclosed this time is to be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  The insulated gate field effect transistor of the present invention can be particularly advantageously applied to an insulated gate field effect transistor that requires an improvement in switching speed.

1 MOSFET, 10 n ⁺ SiC substrate, 20A first main surface, 20B second main surface, 20 n ⁻ SiC layer, 21 p body, 21A first contact region, 21B second contact region, 21C third Contact region, 21D channel region, 22 n ⁺ source region, 23 p ⁺ region, 30 gate oxide film, 40 gate electrode, 50 interlayer insulating film, 60 source electrode, 70 drain electrode, 80 contact electrode, 80A first contact Electrode, 80B second contact electrode, 91 resist film, 92 thermal oxide film, 93 oxide film, 94 Ni film.

Claims (7)

A substrate,
A first conductivity type semiconductor layer formed on the substrate;
In the semiconductor layer, a second conductivity different from the first conductivity type formed so as to include a second main surface that is a main surface opposite to the first main surface that is the main surface on the substrate side. A second conductivity type region of the mold;
A high-concentration first conductivity type region that includes the second main surface and is formed inside the second conductivity type region, and includes a first conductivity type impurity having a concentration higher than that of the semiconductor layer;
In a first contact region included in the second main surface in the high concentration first conductivity type region, a first electrode that contacts the high concentration first conductivity type region;
A second electrode that is in contact with the second conductivity type region in a second contact region that is on the outer peripheral side of the first contact region and is included in the second main surface in the second conductivity type region. When,
The second conductivity type region is formed so as to include the second main surface inside the second conductivity type region and on the outer peripheral side of the high concentration first conductivity type region, and has a second concentration higher than that of the second conductivity type region. A first high-concentration second conductivity type region containing a type impurity ,
The first high-concentration second conductivity type region is formed at a distance from the high-concentration first conductivity type region,
The insulated gate field effect transistor , wherein the second contact region overlaps the first high-concentration second conductivity type region on the second main surface . The second conductivity type region has a polygonal shape having three or more vertices on the second main surface;
The second contact region is disposed on the second main surface so as to include a region on the centroid side as viewed from the vertex on a straight line connecting the centroid of the polygon and the vertex. The insulated gate field effect transistor according to claim 1 . The insulated gate field effect transistor according to claim 2 , wherein the second conductivity type region has a quadrangular shape on the second main surface. The insulated gate field effect transistor according to claim 2 , wherein the second conductivity type region has a hexagonal shape on the second main surface. A substrate,
A first conductivity type semiconductor layer formed on the substrate;
In the semiconductor layer, a second conductivity different from the first conductivity type formed so as to include a second main surface that is a main surface opposite to the first main surface that is the main surface on the substrate side. A second conductivity type region of the mold;
A high-concentration first conductivity type region that includes the second main surface and is formed inside the second conductivity type region, and includes a first conductivity type impurity having a concentration higher than that of the semiconductor layer;
In a first contact region included in the second main surface in the high concentration first conductivity type region, a first electrode that contacts the high concentration first conductivity type region;
A second electrode that is in contact with the second conductivity type region in a second contact region that is on the outer peripheral side of the first contact region and is included in the second main surface in the second conductivity type region. And
A third electrode in contact with the second conductivity type region in a third contact region included in the second main surface surrounded by the first contact region;
A second high-concentration second conductive type region that contains a second conductive type impurity at a higher concentration than the second conductive type region, is formed in the second conductive type region, and is in contact with the third electrode; further Ru comprising a insulation gate type field effect transistor. An insulator formed on the second main surface so as to cover the region other than the first contact region and the second contact region in the second conductivity type region on the second main surface. A gate insulating film comprising:
The insulated gate field effect transistor according to claim 1 , further comprising a gate electrode made of a conductor and disposed on the gate insulating film. The insulated gate field effect transistor according to any one of claims 1 to 6 , wherein the semiconductor layer is made of silicon carbide or gallium nitride.

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