JP3855386B2 - Semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device, and more particularly to a U-shaped gate MOSFET (hereinafter referred to as UMOSFET).
[0002]
[Prior art]
FIG. 8 is a plan view showing a pattern arrangement of a conventional UMOSFET, and FIG. 9 is a cross-sectional view taken along the line DD ′ shown in FIG.
First, the pattern arrangement shown in FIG. 8 will be described. U-shaped gate electrodes 200 are arranged in a mesh pattern. In each square section surrounded by the U-shaped gate electrode 200, a high-concentration n-type source region 201 is formed so as to contact the U-shaped gate electrode 200, and a high-concentration p-type base contact region 202 is formed at the center thereof. Is formed. Each region surrounded by the U-shaped gate electrode 200 is referred to as a source cell 203.
[0003]
Further, as shown in the cross-sectional view of FIG. 9, the U-shaped gate electrode 200 is oxidized in a U-shaped groove provided so as to penetrate the high-concentration n-type source region 201 and the p-type base region 204. It is composed of polycrystalline silicon 206 insulated from the outside by films 205 and 207.
[0004]
The operation of the conventional UMOSFET will be described below with reference to FIG. The source electrode 208 is set to 0 potential and the drain electrode 211 is set to positive potential. When a positive potential equal to or higher than the threshold value is applied to the U-shaped gate electrode 200 in this state, an inversion layer is formed in the vicinity of the U-shaped gate electrode 200 in the p-type base region 204. Then, a current flows from the drain electrode 211 to the source electrode 208 via the high concentration n-type semiconductor substrate 210, the low concentration n-type epitaxial layer 209, the inversion layer formed as described above, and the high concentration n-type source region 201. This is the case when the UMOSFET is turned on.
[0005]
On the other hand, when the UMOSFET is turned off, a potential lower than the threshold value is applied to the U-shaped gate electrode 200. Then, the inversion layer is not formed and the off state is obtained.
In such a UMOSFET structure, since the JFET resistance of a MOSFET having a gate electrode formed in a planar shape does not exist, it is possible to miniaturize the element and thus reduce the on-resistance.
In the above example, the vertical UMOSFET whose drain electrode is on the side opposite to the source electrode has been described. However, a horizontal UMOSFET whose drain electrode is on the same side as the source electrode can be considered similarly.
[0006]
[Problems to be solved by the invention]
However, in the conventional device as described above, as can be seen from the planar structure of FIG. 8, each source cell 203 has a high-concentration p-type base contact region 202 in the middle of the high-concentration n-type source region 201, and the contact resistance is reduced. In order not to increase, it is difficult to reduce this area. For this reason, there is a limit in reducing the size of each source cell, and therefore there is a problem that miniaturization is limited and there is a limit in reducing on-resistance.
[0007]
The present invention has been made to solve the problems of the conventional techniques as described above, and provides a semiconductor device capable of further reducing the on-resistance, which is an important issue in the characteristics of the power MOSFET. Objective.
[0008]
[Means for Solving the Problems]
In order to achieve the above object, the present invention adopts a configuration as described in the claims. That is, in claim 1, a plurality of polygonal source regions in a planar shape are arranged in a cell shape at a predetermined interval, and the U-shaped gate is arranged between the source regions arranged in a cell shape at the predetermined interval. In the U-shaped gate MOSFET in which electrodes are arranged in a mesh pattern, the base contact region is formed across the corners of a plurality of adjacent source regions, and the U-shaped gate electrode is the base It is configured so as to be arranged in a mesh pattern except for the portion where the contact region is formed .
[0009]
And forming a base contact region over the corner portion of the plurality of source regions adjacent to the above one another, for example, as shown in later Figure 1, the corners of the four source regions of the rectangle adjacent to each other One common base contact region is provided across. 1 may be provided with a common base contact region straddling two source regions . The planar shape of the source region may be another polygon such as a triangle or a hexagon. Basically, it is only necessary to provide a base contact region at one location for one source region . In FIG. 1, one base contact region is provided for four source regions . The base contact region is not provided overlapping the region . However, it can be provided so as to overlap across the corners of all adjacent source regions .
The above configuration corresponds to, for example, a first embodiment described later.
[0010]
According to a second aspect of the present invention, there is provided a U-shaped gate MOSFET similar to the above, wherein a base contact region is formed only at each corner of each polygonal source region . The base contact region is formed only at each corner of each source region . For example, as shown in FIG. 5 to be described later, the base contact region is formed only at the four corners of all the source regions , and the U-shaped gate electrode is formed. It is completely formed in a mesh shape. Note that the number of corners varies depending on the shape of the source region .
The above configuration corresponds to, for example, a second embodiment described later.
[0011]
According to a third aspect of the present invention, the present invention is applied to a lateral UMOSFET in which a source electrode and a drain electrode are formed on the same surface side of a semiconductor substrate.
The above configuration corresponds to, for example, FIGS. 3 and 4 to be described later.
[0012]
According to a fourth aspect of the present invention, the side surface of the U-shaped gate electrode is formed so that the crystal orientation of the semiconductor material is the {100} plane.
[0013]
With the configuration as described above, in the structure of the present invention, since a common base contact region is provided at each corner of a plurality of source cells, the channel width per unit area can be increased. Therefore, when compared with elements having the same area, the channel width of the entire element is increased, thereby further reducing the on-resistance.
[0014]
Also, since the vicinity of the corner of the source cell has an arc shape in terms of manufacturing technology, in the case of a square source cell in which the side surface of the U-shaped gate electrode is formed to be a {100} plane, Electron mobility is reduced, which is not very effective as a channel current path. In the present invention, since a contact region is provided in this portion, a portion having little effect as a channel can be used effectively, and thereby each source cell can be further miniaturized.
[0015]
In the structure of the present invention, since the base contact region is formed in the vicinity of the U-shaped gate electrode, the base resistance is reduced when a surge voltage is applied. Therefore, when the surge voltage is applied, the potential of the base region is reduced. Therefore, surge resistance is improved because the parasitic bipolar transistor is difficult to turn on.
[0016]
Further, by forming the U-shaped gate electrode so that the side surface of the U-shaped gate electrode is the {100} plane, the U-shaped gate electrode is formed so that the channel current flows in the direction in which the electron mobility is large. This can reduce the on-resistance.
[0017]
【The invention's effect】
According to the present invention, since the channel width per unit area of the UMOSFET increases, the on-resistance of the entire device can be reduced.
In addition, when the source cell is a square and the side surface of the U-shaped gate electrode is a {100} plane, the area can be effectively used by using a region that is not very effective as a current path as a base contact region. Miniaturization is possible.
In addition, since the high-concentration p-type base contact region is formed in the vicinity of the U-shaped gate electrode, the parasitic bipolar transistor is difficult to turn on, so that the surge withstand capability can be improved. It is done.
[0018]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
1 is a plan view showing a pattern arrangement of a UMOSFET according to the first embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along the plane AA′-A ″ shown in FIG. This embodiment corresponds to the first aspect.
[0019]
First, the plan view shown in FIG. 1 will be described. Square source cells 103 are regularly arranged in a square shape at predetermined intervals as shown in the figure. A U-shaped gate electrode 100 is formed between adjacent source cells 103. Further, the high-concentration p-type base contact region 102 is formed across the corner portion of the adjacent source cell 103. That is, one common base contact region is provided across the corners of the four rectangular source cells. 1 may be provided with one common base contact region straddling two source cells. Similarly, in the case of source cells such as triangles and hexagons, a common base contact region may be provided across the corners of a plurality of adjacent source cells. Further, basically, it is only necessary to provide a base contact region at one location for one source cell. Therefore, in FIG. 1, one base contact region is provided for four source cells. The base contact region is not duplicated for the cell. However, it can be provided so as to overlap across the corners of all adjacent source cells.
[0020]
Next, the sectional view shown in FIG. 2 will be described. A low concentration n-type epitaxial layer 109 is formed on the surface of the first main surface of the high concentration n-type semiconductor substrate 110. A p-type base region 104 is formed on the surface of the low-concentration n-type epitaxial layer 109, and a high-concentration n-type source region 101 and a high-concentration p-type base contact region 102 are formed on the surface of the p-type base region 104. Further, a U-shaped groove is formed so as to penetrate the high-concentration n-type source region 101 and the p-type base region 104, an oxide film 105 is formed on the bottom surface and the side surface of the U-shaped groove, and further inside the U-shaped groove Is embedded with polycrystalline silicon 106 (or other conductive material). An oxide film 107 is formed on the upper surface of the polycrystalline silicon 106. These oxide films 105 and 107 and polycrystalline silicon 106 form U-shaped gate electrode 100. A source electrode 108 is connected to the n-type source region 101 and the p-type base contact region 102. A drain electrode 111 is formed on the second main surface (back surface side) of the high concentration n-type semiconductor substrate 110.
[0021]
The above configuration has the following effects.
First, the first effect is that the channel width per unit area can be made larger than in the case where a high-concentration p-type base contact region is formed at the center of each source cell as in the prior art.
[0022]
Details thereof will be described below. First, in the conventional pattern layout shown in FIG. 8, the width of the high concentration p-type base contact region 202 is a, the width of the high concentration n-type source region 201 is b, and the width of the U-shaped gate electrode 200 is c. Then, the channel width W ₁ and the area S ₁ (the sum of the areas of the source cell and the U-shaped gate electrode) per source cell are shown as follows.
[0023]
Channel width W ₁ = 4 (a + 2b)
Area S ₁ = (a + 2b + c) ²
Therefore, the ratio (W ₁ / S ₁ ) between the channel width per unit area and the area is as shown in the following (Equation 1).
W ₁ / S ₁ = 4 (a + 2b) / (a + 2b + c) ² (Equation 1)
On the other hand, in the pattern arrangement of the first embodiment of the present invention shown in FIG. 1, when the above sizes are made to correspond, the channel width W ₂ and the area S ₂ per four source cells are as follows: Become.
[0024]
Channel width W ₂ = 4 (c + 8b−a)
Area S ₂ = 4 (2b + c) ²
Therefore, the ratio (W ₂ / S ₂ ) between the channel width per unit area and the area is as shown in the following (Equation 2).
[0025]
W ₂ / S ₂ = (c + 8b−a) / (2b + c) ² (Equation 2)
In the above formulas (1) and (2), for example, the channel width per unit area when a = 1.5 μm, b = 1.5 μm, and c = 1.0 μm is
Conventional pattern: 0.595 μm
Pattern of the present invention: 0.719 μm
It becomes. Comparing the two,
[(0.719−0.595) /0.595] × 100% = 20.8%
Thus, in the present invention, the channel width per unit area is increased by about 20% compared to the conventional case. Therefore, if the comparison is made with the same area, the on-resistance of the entire element can be reduced by the amount described above.
[0026]
The second effect is that the area can be used effectively in the pattern arrangement of the present invention. In a normal UMOSFET, in order to reduce the on-resistance, a U-shaped gate electrode is formed so that a channel current flows in a direction in which the electron mobility is large. That is, the U-shaped gate electrode is formed so that the side surface of the U-shaped gate electrode is a {100} plane. However, since the corner portion of the source cell has an arc shape in manufacturing, the mobility of electrons becomes small. That is, this region is not very effective as a channel current path. In the present invention, since a contact region is provided in this portion, a portion having little effect as a channel can be used effectively, and thereby each source cell can be further miniaturized.
[0027]
A third effect is that surge resistance can be improved by the present invention. In the structure of FIG. 2, there is a parasitic bipolar transistor formed by drain electrode 111 −high concentration n-type semiconductor substrate 110 −low concentration n type epitaxial layer 109 −p type base region 104 −high concentration n type source region 101. The potential of the p-type base region 104 becomes the base potential of this parasitic bipolar transistor. Therefore, when a surge is applied to the drain region, if the base resistance is large, the parasitic bipolar transistor is turned on, a large current flows, and the element may be destroyed.
[0028]
FIG. 7 is a diagram showing a comparison between the present invention and a conventional device when a surge is applied. FIG. 7A is a sectional view of the UMOSFET of the present invention (corresponding to FIG. 6 described later), and FIG. A cross-sectional view (corresponding to FIG. 9) of the UMOSFET is shown.
[0029]
In either case, when a surge is applied to the drain region, an accumulation layer is formed in the vicinity of the U-shaped gate electrode. In the case of the conventional device shown in (b), the surge current flows through this accumulation layer, and flows to the high-concentration p-type base contact region 202 and the source electrode 208 via the p-type base region 209. On the other hand, in the case of the present invention shown in (a), the high-concentration p-type base contact region 122 is in contact with the U-shaped gate electrode 120, and the surge current is increased from the accumulation layer formed in the p-type base region. It flows to the source electrode 128 through the concentration p-type base contact region 122. Therefore, the potential of the base region is lower in the case of (a) than in the case of (b) in which the resistance of the base region is added, that is, the parasitic bipolar transistor is difficult to turn on, and the element is not easily destroyed. .
[0030]
In FIG. 7 (a), for the sake of illustration, a diagram corresponding to FIG. 6 showing a second embodiment of the present invention to be described later is used, but the same applies to FIG. . That is, in FIG. 2, the high-concentration p-type base contact region 102 is shown at a position away from the U-shaped gate electrode 100 for the convenience of the cross-sectional position, but as can be seen from FIG. The high-concentration p-type base contact region 102 is disposed in the vicinity of the U-shaped gate electrode 100, and the function and effect are the same as in the case of FIG.
[0031]
Further, in the first embodiment of the present invention as described above, the vertical UMOSFET in which the source electrode and the drain electrode are formed on the opposite surface side of the semiconductor substrate has been described, but as shown in FIGS. The same effect can be obtained for a lateral UMOSFET in which a source electrode and a drain electrode are formed on the same surface side of a semiconductor substrate.
[0032]
Hereinafter, FIGS. 3 and 4 will be briefly described.
3 is a plan view of a lateral UMOSFET to which the present invention is applied, and FIG. 4 is a cross-sectional view taken along the line BB′-B ″ -B ″ ′ of FIG. 3 is different from FIG. 1 only in that a drain cell is provided, and the others are the same. In FIG. 4, the low-concentration n-type drain region 112, the high-concentration n-type buried region 113, the p-type semiconductor substrate 114, the drain electrode 115, the high-concentration n-type drain extraction region 116, and the high-concentration n-type drain contact region 117. Except for this part, it is almost the same as FIG.
[0033]
Next, FIG. 5 is a plan view showing a pattern arrangement according to the second embodiment of the present invention, and FIG. 6 is a cross-sectional view taken along line CC′-C ″ in FIG. 5. Configuration of the first embodiment The difference is that the high-concentration p-type base contact region 122 is formed only in the square portions of all the source cells, and the U-shaped gate electrode 120 is formed in a completely mesh shape. 5 and 6, each symbol indicates the following: 120 is a U-shaped gate electrode, 121 is a high-concentration n-type source region, 122 is a high-concentration p-type base contact region, 123 is a source cell, 124 Is a p-type base region, 125 is a gate oxide film, 126 is a polycrystalline silicon layer, 127 is an oxide film, 128 is a source electrode, 129 is a low-concentration n-type drain region, 130 is a high-concentration n-type semiconductor substrate, and 131 is a drain Electrode.
[0034]
In FIG. 5, the case where the source cell is a quadrangle and the base contact regions are provided at the four corners is illustrated. However, even when the source cell has a triangular or hexagonal shape, the source cell is provided at each corner. That's fine.
[0035]
Similarly to the first embodiment, the second embodiment of the present invention can have a larger channel width per unit area than the conventional technique, and the source cell is square and U-shaped. When the side surface of the gate electrode is a {100} plane, a region with low electron mobility is used as the base contact region, and the area is effectively used, so that the on-resistance can be reduced. Further, since the high-concentration p-type base contact region is formed so as to be in contact with the U-shaped gate electrode, the base resistance can be reduced and the surge resistance can be improved.
[0036]
Also in the second embodiment of the present invention, the same effect can be obtained when applied to a lateral UMOSFET as in the case of the first embodiment of the present invention.
[Brief description of the drawings]
FIG. 1 is a plan view showing a pattern arrangement according to a first embodiment of the present invention.
2 is a cross-sectional view taken along the line AA′-A ″ in FIG. 1;
FIG. 3 is a plan view showing a pattern arrangement when the first embodiment is applied to a lateral UMOSFET.
4 is a cross-sectional view taken along the line BB′-B ″ -B ″ ′ of FIG. 3;
FIG. 5 is a plan view showing a pattern arrangement according to a second embodiment of the present invention.
6 is a cross-sectional view taken along the line CC′-C ″ of FIG. 5;
FIG. 7 is a cross-sectional view showing a current path in the vicinity of a U-shaped gate electrode when a surge voltage is applied.
FIG. 8 is a plan view showing a pattern arrangement in the prior art.
9 is a cross-sectional view taken along the line DD ′ of FIG.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 100 ... U-shaped gate electrode 101 ... High concentration n type source region 102 ... High concentration p type base contact region 103 ... Source cell 104 ... P type base region 105 ... Gate oxide film 106 ... Polycrystalline silicon layer 107 ... Oxide film 108 ... Source electrode 109 ... Low-concentration n-type drain region 110 ... High-concentration n-type semiconductor substrate 111 ... Drain electrode 112 ... Low-concentration n-type drain region 113 ... High-concentration n-type buried region 114 ... p-type semiconductor substrate 115 ... Drain electrode 116 ... High-concentration n-type drain lead region 117 ... High-concentration n-type drain contact region 120 ... U-shaped gate electrode 121 ... High-concentration n-type source region 122 ... High-concentration p-type base contact region 123 ... Source cell 124 ... p-type base Region 125 ... Gate oxide film 126 ... Polycrystalline silicon layer 127 ... Oxide film 128 ... Low-concentration n-type drain region 130 High-concentration n-type semiconductor substrate 131 Drain electrode 200 U-shaped gate electrode 201 High-concentration n-type source region 202 High-concentration p-type base contact region 203 Source Cell 204 ... p-type base region 205 ... gate oxide film 206 ... polycrystalline silicon layer 207 ... oxide film 208 ... source electrode 209 ... low concentration n-type drain region 210 ... high concentration n-type semiconductor substrate 211 ... drain electrode

Claims (4)

A semiconductor substrate serving as a drain region of the first conductivity type, a second conductivity type base region formed on the surface of the first main surface of the semiconductor substrate, and a source region of the first conductivity type formed on the surface of the base region And an oxide film is formed on the bottom and side surfaces of the second conductive type base contact region, the source region and the U-shaped groove formed through the base region, and a conductive material is applied to the U-shaped groove. A U-shaped gate electrode formed by being embedded; a source electrode connected to the source region and the base contact region; and a drain electrode connected to the semiconductor substrate; a source region of the rectangular are arranged in cell shape at predetermined intervals, the U-shaped U-shaped gate electrode are arranged in a net-like gate MOSF between the source region disposed in the cell shape in the predetermined distance A T,
The base contact region is formed across corners of a plurality of adjacent source regions , and the U-shaped gate electrode is arranged in a mesh pattern except for a portion where the base contact region is formed. wherein a is. A semiconductor substrate serving as a drain region of the first conductivity type, a second conductivity type base region formed on the surface of the first main surface of the semiconductor substrate, and a source region of the first conductivity type formed on the surface of the base region And an oxide film is formed on the bottom and side surfaces of the second conductive type base contact region, the source region and the U-shaped groove formed through the base region, and a conductive material is applied to the U-shaped groove. A U-shaped gate electrode formed by being embedded; a source electrode connected to the source region and the base contact region; and a drain electrode connected to the semiconductor substrate; a source region of the rectangular are arranged in cell shape at predetermined intervals, the U-shaped U-shaped gate electrode are arranged in a net-like gate MOSF between the source region disposed in the cell shape in the predetermined distance A T,
2. A semiconductor device according to claim 1, wherein the base contact region is formed only at each corner of each source region .   3. The semiconductor device according to claim 1, wherein the U-shaped gate MOSFET is a lateral UMOSFET in which a source electrode and a drain electrode are formed on the same surface side of a semiconductor substrate.   4. The semiconductor device according to claim 1, wherein a side surface of the U-shaped gate electrode is formed so that a crystal orientation of a semiconductor material is a {100} plane.

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