JP2006237125A - Method of operating bipolar type semiconductor device, and bipolar type semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress the increase of a created stacking fault area by continuing energizing in a bipolar type semiconductor device which performs electron and hole recombination in the time of energization inside a silicon carbide epitaxial film grown up from the front surface of a silicon carbide single crystal substrate. <P>SOLUTION: A conducting operation is performed while the above SiC bipolar type semiconductor device is maintained in a temperature environment at 350°C or more. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a method of operating a bipolar semiconductor device in which electrons and holes are recombined when energized inside a silicon carbide epitaxial film grown from the surface of a silicon carbide single crystal substrate, and in particular, energizing operation. The present invention relates to an improvement in technology for suppressing an increase in the stacking fault area due to the above.

  Silicon carbide (SiC) has a breakdown electric field strength of about 10 times that of silicon (Si), and also has excellent physical properties in terms of thermal conductivity, electron mobility, band gap, etc. Therefore, it is expected as a semiconductor material that realizes a dramatic performance improvement as compared with conventional Si-based power semiconductor elements.

  Recently, 4H-SiC and 6H-SiC single crystal substrates up to 3 inches in diameter have become commercially available, and various switching elements that greatly exceed the performance limit of Si have been reported one after another. Device development is ongoing.

  Semiconductor elements are roughly classified into unipolar elements in which only electrons or holes act on conduction when energized, and bipolar elements in which both electrons and holes act on conduction. The unipolar element includes a Schottky barrier diode (SBD), a junction field effect transistor (J-FET), a metal / oxide film / semiconductor field effect transistor (MOS-FET), and the like. The bipolar element includes a pn diode, a bipolar junction transistor (BJT), a thyristor, a GTO thyristor, an insulated gate bipolar transistor (IGBT), and the like.

When manufacturing a power semiconductor element using a SiC single crystal, it is difficult to diffuse impurities deeply because the diffusion coefficient of the SiC single crystal is extremely small. Therefore, the same crystal as the substrate is formed on the SiC single crystal substrate. In many cases, a single crystal film having a predetermined film thickness and doping concentration is epitaxially grown in a mold (Patent Document 1). Specifically, an SiC single crystal substrate obtained by growing an epitaxial single crystal film by a CVD method on the surface of a substrate obtained by slicing a bulk single crystal obtained by a sublimation method or chemical vapor deposition (CVD). Is used.

There are various polytypes (crystal polymorphs) in SiC single crystals, but in the development of power semiconductors, 4H-SiC, which has high dielectric breakdown strength and mobility and relatively low anisotropy, is mainly used. . Crystal planes for epitaxial growth include (0001) Si plane, (000-1) C plane, (11-20) plane, (1-100) plane, (03-38) plane, etc. In the case of epitaxial growth from the Si plane and the (000-1) C plane, these planes are [11-2] for homoepitaxial growth by the step flow growth technique.
A crystal plane tilted several degrees in the [0] direction or [01-10] direction is often used.
International Publication WO03 / 038876 Pamphlet Journal of Applied Physics Volume 95 No. 3 2004, pages 1485 to 1488 Journal of Applied Physics Volume 92 No. 8 2004 4699-4704

As described above, the power semiconductor element using SiC has various excellent points.
There is a problem that the forward voltage increases as the energization time (integrated use time) increases after energization of a new SiC bipolar element. An increase in the forward voltage decreases the reliability of the SiC bipolar element, and causes an increase in power loss of a power control apparatus incorporating the SiC bipolar element.

This increase in forward voltage due to energization is considered to be caused by the following reason, and many reports have been made (Non-Patent Documents 1 and 2 above). FIG. 1 is a cross-sectional view showing the vicinity of an interface between a SiC single crystal substrate and an epitaxial film formed from the surface by a step flow growth technique. In the figure, 5 is a crystal plane ((0001) Si plane), and θ is an off angle. As shown in the figure, the SiC single crystal substrate 1 has a large number of basal plane dislocations 3 which are a kind of crystal defects. For example, in a SiC single crystal substrate tilted so that the off-angle is 8 ° from the (0001) Si plane, the basal plane dislocation density on the substrate surface is typically 10 ² to 10 ^4, although it depends on the crystal quality. / Cm ² .

  The basal plane dislocations 3 extending in parallel with the (0001) Si plane appear on the surface of the SiC single crystal substrate 1, and about several percent of the basal plane dislocations 3 are n-type epitaxial film 2a and p-type epitaxial film (or at the time of epitaxial growth). p-type implantation layer) 2b propagates as basal plane dislocation 3 as it is, and the rest is converted to threading edge dislocation 4 to n-type epitaxial film 2a and p-type epitaxial film (or p-type implantation layer) 2b. Propagate.

  In a bipolar device such as a pn diode, electrons and holes are regenerated when the n-type epitaxial film and the interface between the n-type epitaxial film and the p-type epitaxial film or the interface between the n-type epitaxial film and the p-type injection layer are energized. The basal plane dislocation 3 is converted into a stacking fault by the recombination energy of electrons and holes generated during energization. As shown in FIG. 5A, the stacking fault occurs as a planar defect 31 having a triangular shape or the like.

  The basal plane dislocation has a Burgers vector of 1/3 [11-20], but two Shockley-type partial dislocations (Shockley 1/3 [10-10] and 1/3 [01-10]). partial dislocations (also called Shockley-type incomplete partial dislocations) are present in a decomposed state, and the microregions sandwiched between these partial dislocations form stacking faults. This stacking fault is called a Shockley-type stacking fault. It is considered that one of these partial dislocations moves due to the recombination energy between electrons and holes, thereby increasing the stacking fault area (see Non-Patent Document 1 above).

  The area of the planar stacking fault increases as the energization time increases. Since the stacking fault region acts as a high-resistance region when energized, the forward voltage of the bipolar element increases as the stacking fault area increases. An increase in the forward voltage decreases the reliability of the SiC bipolar element and causes an increase in power loss of the power control device incorporating the SiC bipolar element, and thus there is a problem of suppressing an increase in the forward voltage due to energization.

  The present invention has been made to solve the above-described problems in the prior art, and an object of the present invention is to suppress an increase in stacking fault area caused by continuing energization in a SiC bipolar semiconductor device.

Conventionally, a SiC bipolar element such as a pn diode is usually energized in a temperature environment from room temperature to less than 350 ° C., for example. In other words, for SiC bipolar elements incorporated in devices for power control, etc., the environmental temperature of the bipolar elements is intentionally controlled and operated at high temperatures to reduce the stacking fault area that causes current deterioration. There was no suppression of expansion. However, when the energization operation was performed while maintaining the bipolar element in a temperature environment of 350 ° C. or higher, particularly 400 ° C. or higher, it was found that even if energization was continued for a long time, the area of stacking faults was hardly enlarged, and the present invention was completed. It came to.

An operation method of a bipolar semiconductor device of the present invention is an operation method of a bipolar semiconductor device in which electrons and holes recombine when energized inside a silicon carbide epitaxial film grown from the surface of a silicon carbide single crystal substrate. ,
In order to prevent an increase in the stacking fault area that causes energization degradation, the bipolar semiconductor device is energized while being maintained at a temperature of 350 ° C. or higher.

  The operation method of the bipolar semiconductor device according to the present invention is characterized in that the bipolar semiconductor device is energized while being maintained at a temperature of 350 ° C. or higher by using a temperature control device for heating the bipolar semiconductor device. And

  The operation method of the bipolar semiconductor device of the present invention is characterized in that energization is started after the bipolar semiconductor device reaches a temperature of 350 ° C. or higher by the temperature control device.

  The operation method of the bipolar semiconductor device according to the present invention is characterized in that energization is stopped by the temperature control device while maintaining the bipolar semiconductor device at a temperature of 350 ° C. or higher.

  The operation method of the bipolar semiconductor device of the present invention is characterized in that energization is stopped when the temperature of the bipolar semiconductor device is lowered to a temperature lower than 350 ° C. by the temperature control device.

  The operation method of the bipolar semiconductor device of the present invention is characterized by using a bipolar semiconductor device manufactured by a substrate in which a hexagonal silicon carbide epitaxial film is grown from the surface of a hexagonal silicon carbide single crystal substrate. As such a bipolar semiconductor device, specifically, a hexagonal quadruple periodic silicon carbide epitaxial film grown from the surface of a hexagonal quadruple periodic silicon carbide single crystal substrate, a hexagonal crystal six times A substrate obtained by growing a hexagonal hexa-periodic silicon carbide epitaxial film from the surface of a periodic silicon carbide single crystal substrate, or a hexagonal bi-periodic type from the surface of a hexagonal double-period silicon carbide single crystal substrate A bipolar semiconductor device manufactured using a substrate on which a silicon carbide epitaxial film is grown can be given.

  The operation method of the bipolar semiconductor device of the present invention is a bipolar type manufactured by a substrate in which a rhombohedral fifteen-period silicon carbide epitaxial film is grown from the surface of a rhombohedral fifteen-period silicon carbide single crystal substrate. A semiconductor device is used.

The bipolar semiconductor device of the present invention is a bipolar semiconductor device in which electrons and holes are recombined when energized inside a silicon carbide epitaxial film grown from the surface of a silicon carbide single crystal substrate,
A bipolar element and a temperature detection element for detecting the temperature of the bipolar element are formed on the same silicon carbide single crystal substrate.

The bipolar semiconductor device of the present invention is a bipolar semiconductor device in which electrons and holes are recombined when energized inside a silicon carbide epitaxial film grown from the surface of a silicon carbide single crystal substrate,
A bipolar element, a heater for heating the bipolar element, and a temperature detecting element for detecting the temperature of the bipolar element are formed on the same silicon carbide single crystal substrate.

  According to the present invention, the expansion of the stacking fault area caused by energizing the SiC bipolar semiconductor device can be significantly suppressed.

  Hereinafter, the present invention will be described with reference to the drawings. Regarding the lattice orientation and lattice plane, the individual orientation is indicated by [], the individual plane is indicated by (), and the negative exponent is crystallographically "-" (bar) is added on the number. In order to prepare the description, a negative sign is added before the number.

  In the present invention, a conventionally used SiC bipolar element is used. As a semiconductor substrate for forming electrodes and the like, a SiC single crystal substrate obtained by growing a SiC epitaxial single crystal film from the surface is used.

  As the SiC single crystal substrate, a slice obtained by slicing a bulk crystal obtained by a sublimation method or a CVD method is used. In the case of the sublimation method (modified Rayleigh method), for example, SiC powder is put into a crucible and heated at 2200 to 2400 ° C. to vaporize, and deposited on the surface of the seed crystal typically at a rate of 0.8 to 1 mm / h. Let it grow in bulk. The obtained ingot is sliced into a predetermined thickness so that a desired crystal plane appears. In order to suppress the propagation of basal plane dislocations to the epitaxial film, the surface of the cut wafer is processed into a mirror surface by polishing using abrasive grains, hydrogen etching, chemical mechanical polishing (CMP), or the like. To smooth.

  A SiC single crystal epitaxial film is grown from the surface of the SiC single crystal substrate. There are crystal polymorphisms (polytypes) in SiC single crystals. For example, 4H—SiC, 6H—SiC, 2H—SiC, 15R—SiC and the like are used as SiC single crystal substrates. Among these, 4H—SiC has high dielectric breakdown strength and mobility, and relatively low anisotropy. Examples of crystal planes for epitaxial growth include (0001) Si plane, (000-1) C plane, (11-20) plane, (01-10) plane, (03-38) plane, and the like.

When epitaxial growth is performed on the (0001) Si face and the (000-1) C face, [01−
10] direction, [11-20] direction, or a substrate cut out by inclining at an off angle of, for example, 1 to 12 ° in the off direction in the intermediate direction between the [01-10] direction and the [11-20] direction. Then, SiC is epitaxially grown from this crystal plane by a step flow growth technique.

  The epitaxial growth of the SiC single crystal film is performed using a CVD method. Propane or the like is used as the C source gas, and silane or the like is used as the Si source gas. A mixed gas of these source gas, a carrier gas such as hydrogen, and a dopant gas is supplied to the surface of the SiC single crystal substrate. As the dopant gas, nitrogen or the like is used when growing an n-type epitaxial film, and trimethylaluminum or the like is used when growing a p-type epitaxial film.

  Under these gas atmospheres, for example, SiC is epitaxially grown at a growth rate of 2 to 20 μm / h under conditions of 1500 to 1600 ° C. and 40 to 80 Torr. Thereby, step-flow growth of SiC having the same crystal type as the SiC single crystal substrate occurs.

As a specific apparatus for performing epitaxial growth, a vertical hot wall furnace can be used. In the vertical hot wall furnace, a water-cooled double cylindrical tube made of quartz is installed. Inside the water-cooled double cylindrical tube, a cylindrical heat insulating material, a hot wall made of graphite, and a SiC single crystal substrate Is provided with a wedge-shaped susceptor for holding the device vertically. A high-frequency heating coil is installed around the outside of the water-cooled double cylindrical tube, the hot wall is induction-heated by the high-frequency heating coil, and the SiC single crystal substrate held by the wedge-shaped susceptor is heated by radiant heat from the hot wall. . SiC is epitaxially grown on the surface of the SiC single crystal substrate by supplying a reaction gas from below the water-cooled double cylindrical tube while heating the SiC single crystal substrate.

A bipolar element is fabricated using the SiC single crystal substrate on which the epitaxial film is formed in this manner. Hereinafter, an example of a method for manufacturing a pn (pin) diode, which is one of bipolar elements, will be described with reference to FIG. An ingot grown by the modified Rayleigh method is sliced at a predetermined off angle, and the surface is mirror-finished on n-type 4H—SiC (carrier density 8 × 10 ¹⁸ cm ⁻³ , thickness 400 μm) 21, CVD method A nitrogen-doped n-type SiC layer (drift layer 23: donor density 5 × 10 ¹⁴ cm ⁻³ , film thickness 40 μm) and an aluminum-doped p-type SiC layer (p-type junction layer 24: acceptor density 5 × 10 ¹⁷ cm ⁻³⁾ , 1.5 μm thick and p + -type contact layer 25: acceptor density 1 × 10 ¹⁸ cm ⁻³ , 0.5 μm thick) are epitaxially grown sequentially.

  Next, the outer peripheral portion of the epitaxial film is removed by reactive ion etching (RIE) to form a mesa structure. In order to form a mesa structure, a Ni metal film is deposited on the epitaxial film. An electron beam heating vapor deposition apparatus is used for vapor deposition. The electron beam heating vapor deposition apparatus includes an electron beam generator, a crucible for storing a Ni metal piece, and a substrate holder for holding a SiC single crystal substrate with the surface of the epitaxial film as the outside. The Ni metal piece placed in the crucible is irradiated with an electron beam accelerated to about 10 kV to melt the Ni metal piece, and is deposited on the epitaxial film.

  A photoresist for patterning the mesa structure is applied to the surface of the Ni metal film deposited on the epitaxial film so as to have a thickness of 1 μm using a spin coater, and the resist film is heat-treated in an oven. The resist film is exposed to ultraviolet rays through a mask corresponding to a mesa structure pattern and developed using a resist developer. The Ni metal film exposed on the substrate surface by development is removed with an acid, and then the epitaxial film exposed on the substrate surface after the Ni metal film is removed by RIE using a mixed gas of carbon tetrafluoride and oxygen is etched. A mesa having a height width of 4 μm is formed.

Next, in order to alleviate electric field concentration at the bottom of the mesa, aluminum ions are implanted to form a JTE (junction termination extension) 26. JTE26 has a total dose of 1.2 × 10 ¹³ cm ⁻² , a width of 250 μm, and a depth of 0.7 μm. By implanting ions while sequentially changing energy between 30 to 450 keV, the implanted aluminum ions have a concentration distribution such that the concentration in the depth direction is constant. After the ion implantation, aluminum ions are activated by heat treatment in an argon gas atmosphere.

  Next, an oxide film 27 for protecting the element surface is formed. In order to perform thermal oxidation, the substrate is placed in a thermal oxidation furnace, and the substrate is heated while flowing a dry oxygen gas to form a thermal oxide film having a thickness of 40 nm on the entire surface of the substrate. Thereafter, a predetermined portion such as a portion for forming an electrode on the substrate surface is patterned by a photolithography technique, and the thermal oxide film at these portions is removed by hydrofluoric acid to expose the epitaxial film.

Next, the cathode electrode 28 and the anode electrode 29 are vapor-deposited using an electron beam heating vapor deposition apparatus. The cathode electrode 28 is formed by depositing Ni (thickness 350 nm) on the lower surface of the substrate 21.
The anode electrode 29 is formed by sequentially depositing an Al (thickness: 100 nm) film and a Ti (thickness: 350 nm) film on the upper surface of the p + -type contact layer 25. These electrodes are formed into ohmic electrodes by performing a heat treatment after vapor deposition to form an alloy with SiC.

  In the present invention, the SiC bipolar element is energized and operated in a temperature environment of 350 ° C. or higher, preferably 400 ° C. to 800 ° C., more preferably 400 ° C. to 600 ° C. If the temperature exceeds 600 ° C., the metal material constituting the electrode may not be able to perform a normal operation such as melting. If the temperature exceeds 800 ° C., the characteristics of the bipolar element may be affected. By energizing the SiC bipolar element while maintaining it in the above temperature range, it is possible to significantly suppress the stacking fault area from increasing over time. In other words, as shown in the examples described later, the increase in stacking fault area (increase in forward voltage) with time is remarkably reduced at around 350 ° C. as a boundary.

  This phenomenon is considered to occur for the following reason. As described above, in a bipolar element such as a pn diode, an n-type epitaxial film and the vicinity of the interface between the n-type epitaxial film and the p-type epitaxial layer or the vicinity of the interface between the n-type epitaxial film and the p-type injection layer are electrically Holes are recombined and basal plane dislocations propagated from the SiC single crystal substrate to the epitaxial film are converted into stacking faults by this recombination energy. Since the region where the stacking fault is formed acts as a high-resistance region when energized, the forward voltage of the bipolar element increases as the stacking fault increases in area.

  However, it is considered that the SiC single crystal is stabilized under the condition of 350 ° C. or higher, thereby significantly suppressing the conversion of basal plane dislocations into stacking faults and the expansion of stacking faults. The stacking fault can be confirmed by observing the epitaxial film as an X-ray topographic image, a photoluminescence image, an electroluminescence image, or a cathodoluminescence image. Fabricate multiple pn diodes using 4H-SiC as crystal type, and continue to energize these pn diodes in each temperature environment from room temperature to 450 ° C, then observe photoluminescence image of epitaxial film As a result, as shown in the conceptual diagrams of FIGS. 5 (a) to 5 (e), a large number of triangular stacking faults 31 are generated when the energized operation is performed in a temperature environment from room temperature to less than 350 ° C. (FIGS. 5A and 5B). On the other hand, in the case where the energization operation was performed in a temperature environment of 350 ° C., the occurrence of stacking faults was greatly reduced. It was not seen (FIG.5 (c)-FIG.5 (e)).

  Thus, by energizing the SiC bipolar element at 350 ° C. or more, the expansion of the stacking fault area over time can be remarkably reduced, but this phenomenon is considered not to depend on the crystal plane on which the epitaxial growth is performed, For example, the above effect can be obtained even when the (0001) Si plane, the (000-1) C plane, the (11-20) plane, the (01-10) plane, the (03-38) plane, etc. are used as crystal planes for epitaxial growth. Can do. In particular, when the angle between the plane of the stacking fault and the direction of the energization path is large, for example, when the plane of the stacking fault interrupts the energization path perpendicularly, the stacking fault greatly affects the deterioration of the energization. In such a case, it is considered that the energization deterioration is remarkably suppressed.

  On the other hand, there are a plurality of crystal types in SiC single crystal, but the above phenomenon is considered to be caused by stabilization of the SiC single crystal under the condition of 350 ° C. or higher. In addition to SiC (hexagonal four-period type), 6H-SiC (hexagonal six-period type), 2H-SiC (hexagonal double-period type), 15R-SiC (rhombic fifteen-period type) Similarly, the deterioration of energization can be remarkably suppressed when used.

In addition, any other bipolar element other than a pn diode can be used as long as it is a SiC bipolar semiconductor element in which electrons and holes recombine when energized inside a silicon carbide epitaxial film grown from the surface of a silicon carbide single crystal substrate. By conducting the energization operation in the above temperature environment, the silicon carbide epitaxial film is stabilized and expansion of the stacking fault area is suppressed. Examples of such SiC bipolar semiconductor elements include thyristors, gate turn-off thyristors (GTO), insulated gate bipolar transistors (IGBT), and bipolar junction transistors (BJT). 6 (a) to 6 (c), thyristors (FIG. 6 (a), reference numeral 41), GTO thyristors (FIG. 6 (b), reference numeral 42), and IGBTs (FIG. 6 (c), reference numeral 43). A schematic cross-sectional view is shown. In the figure, 51 is an n-type layer, 52 is a p-type layer, 53 is a cathode electrode, 54 is an anode electrode, 55 is a gate electrode, 56 is an emitter electrode, 57 is a collector electrode, and 58 is an oxide film.

  SiC bipolar devices are used in power control devices such as inverters in the fields of home appliances, industry, vehicles such as electric vehicles, and power systems such as power transmission. When the present invention is applied to an actually incorporated SiC bipolar element, a temperature control device for heating the SiC bipolar element and controlling it to a predetermined temperature is provided so that the SiC bipolar element is always heated to a predetermined temperature. It is desirable to operate while maintaining the temperature.

  This temperature control device includes at least heating means for heating the SiC bipolar element. Examples of such heating means include a heater built in a package of the SiC bipolar element, a heater formed on the same SiC single crystal substrate as the SiC single crystal substrate on which the SiC bipolar element is manufactured, and the like.

  Further, the temperature control device may include a temperature detection unit that measures the temperature of the SiC bipolar element. As such temperature detection means, the temperature sensor built in the heater, the temperature sensor built in the package of the SiC bipolar device, and the same SiC single crystal substrate as the SiC single crystal substrate on which the SiC bipolar device was fabricated were formed. A temperature detection element etc. can be mentioned.

Said temperature control apparatus is connected with the operation control apparatus which controls the electricity supply operation | movement of a SiC bipolar element, for example, the following control is performed so that electricity supply may be performed at predetermined temperature.
(1) The SiC bipolar element is heated by a heater, and after the temperature sensor detects that the SiC bipolar element has reached a predetermined temperature (for example, 350 ° C. or higher), the operation control device starts energizing the SiC bipolar element. .
(2) Energization is performed while heating the SiC bipolar element with a heater, and the operation control device stops the energization operation of the SiC bipolar element while maintaining the SiC bipolar element at a predetermined temperature or higher (for example, 350 ° C. or higher).
(3) While the SiC bipolar element is energized while being heated by the heater, and the SiC bipolar element is being operated while maintaining the SiC bipolar element at a predetermined temperature or higher (eg, 350 ° C. or higher), the SiC bipolar element is disconnected due to disconnection of the heater or the like. When the temperature of the temperature drops below a predetermined temperature, the operation control device urgently stops the energization operation of the SiC bipolar element based on a signal from the temperature detection element. FIG. 10 shows an example of such control. In the normal operation sequence, as shown in FIG. 10A, an energization current flows after the SiC bipolar element reaches a predetermined temperature, and the energization is continued while maintaining the SiC bipolar element at the predetermined temperature, and is also maintained at the predetermined temperature. The energization and temperature are controlled so that the energization is stopped in this state. However, as shown in FIG. 10 (b), when the temperature of the SiC bipolar element decreases and falls below a predetermined temperature due to disconnection of the heater during energization, the temperature detection element detects this, and the operation control device Based on the detection result, energization is urgently stopped.

Thus, by installing a temperature control device and appropriately energizing the SiC bipolar element in a temperature environment of 350 ° C. or higher, it is possible to effectively suppress an increase in stacking fault area.
7 to 9 are diagrams showing specific examples provided with the temperature control device as described above. In FIG. 7, a temperature control device 62 including a heater 66 and a temperature sensor 65 in a package is connected to an operation control device 61 that controls energization through the electrode 64 to the SiC bipolar element 63, thereby energizing the SiC bipolar element 63. And is configured to control the temperature.

  In FIG. 8, both the pn diode 73 and the temperature detection element 74 are fabricated on the SiC single crystal substrate 71 on which the epitaxial film 72 is formed, and the temperature of the pn diode 73 is measured by the temperature detection element 74. Has been.

  In FIG. 9, a pn diode 81, a heater 82, and a temperature detection element 83 are manufactured on the same SiC single crystal substrate, the pn diode 81 is heated by the heater 82, and the temperature of the pn diode 81 is increased by the temperature detection element 83. And the temperature control for the pn diode 81 is performed.

Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, and various modifications and changes can be made without departing from the scope of the present invention.
Examples Hereinafter, the present invention will be described by way of examples. However, the present invention is not limited to these examples.
[Example 1]
The pn diode shown in FIG. 2 was fabricated for testing. An n-type 4H—SiC (0001) substrate (carrier density 8 × 10 ¹⁸ cm ⁻³ ) obtained by slicing an ingot grown by the modified Rayleigh method at an off direction [11-20] and an off angle of 8 ° and mirror-treating the surface. And a nitrogen-doped n-type SiC layer (donor density 5 × 10 ¹⁴ cm ⁻³ , film thickness 40 μm) and an aluminum-doped p-type SiC layer (p-type junction layer: acceptor density 5 ×). 10 ¹⁷ cm ⁻³ , film thickness 1.5 μm, and p + type contact layer: acceptor density 1 × 10 ¹⁸ cm ⁻³ , film thickness 0.5 μm) were sequentially epitaxially grown.

Next, the outer peripheral portion of the epitaxial film was removed by reactive ion etching (RIE) to form a mesa structure having a height width of 4 μm. In order to alleviate electric field concentration at the mesa bottom, aluminum ions were implanted into the mesa bottom to form a JTE having a total dose of 1.2 × 10 ¹³ cm ⁻² , a width of 250 μm, and a depth of 0.7 μm. After ion implantation, heat treatment was performed in an argon gas atmosphere to activate aluminum ions. Thereafter, a protective thermal oxide film was formed on the element surface.

  A cathode electrode and an anode electrode were deposited on the front and back surfaces of the obtained substrate using an electron beam heating deposition apparatus. The cathode electrode is formed by depositing Ni (thickness 350 nm) on the lower surface of the substrate, and the anode electrode is formed by sequentially depositing Al (thickness 100 nm) and Ti (thickness 350 nm) films on the upper surface of the p + type contact layer. It was formed by vapor deposition. After vapor-depositing these electrodes, heat treatment was performed at 1050 ° C. and 90 sec for the cathode electrode and 900 ° C. and 180 sec for the anode electrode to form an alloy with SiC to obtain an ohmic electrode.

Using the pn diode thus obtained, the following energization test was performed. A cathode electrode of a pn diode was pasted on a copper plate using a high melting point solder, and an aluminum wire was bonded to the anode electrode using an ultrasonic bonding apparatus. A current source (TAKASAGO GP350-10R) and a voltmeter (YOKOGAWA HR2300) were electrically connected to the copper plate and the aluminum wire, and an energization test was performed. The energization test was performed by flowing a direct current of 100 A / cm ² (rated current density of the silicon-based power diode) in the forward direction for 60 minutes while maintaining the pn diode in a temperature environment of 350 ° C. The result of observing the photoluminescence image after the energization test is shown in FIG.
[Example 2]
An energization test was performed in the same manner as in Example 1 except that the pn diode similar to that manufactured in Example 1 was used and energization was performed while maintaining the pn diode in a temperature environment of 400 ° C. . The result of observing the photoluminescence image after the energization test is shown in FIG.
[Example 3]
An energization test was performed in the same manner as in Example 1 except that the pn diode similar to that manufactured in Example 1 was used and energization was performed while maintaining the pn diode in a temperature environment of 450 ° C. . The result of observing the photoluminescence image after the energization test is shown in FIG.
[Comparative Example 1]
Using a pn diode similar to that manufactured in Example 1 and conducting energization while maintaining the pn diode in a room temperature (25 ° C.) temperature environment, the energization test was performed in the same manner as in Example 1. Went. The result of observing the photoluminescence image after the energization test is shown in FIG.
[Comparative Example 2]
An energization test was performed in the same manner as in Example 1 except that the pn diode similar to that manufactured in Example 1 was used and energization was performed while maintaining the pn diode in a temperature environment of 300 ° C. . The result of observing the photoluminescence image after the energization test is shown in FIG.
[Example 4]
Using a pn diode similar to that manufactured in Example 1, energization was performed while maintaining the pn diode in a temperature environment of 350 ° C., and an energization test similar to that in Example 1 was performed. The forward voltage Vf before and after the energization test was measured, and the difference ΔVf was used as an index of energization deterioration. The results of the energization test are shown in FIG.
[Example 5]
Using a pn diode similar to that manufactured in Example 1, energization was performed while maintaining the pn diode in a temperature environment of 400 ° C., and an energization test similar to that in Example 1 was performed. The forward voltage Vf before and after the energization test was measured, and the difference ΔVf was used as an index of energization deterioration. The results of the energization test are shown in FIG.
[Example 6]
Using a pn diode similar to that manufactured in Example 1, energization was performed while maintaining the pn diode in a temperature environment of 450 ° C., and an energization test similar to that in Example 1 was performed. The forward voltage Vf before and after the energization test was measured, and the difference ΔVf was used as an index of energization deterioration. The results of the energization test are shown in FIG.
[Comparative Example 3]
Using a pn diode similar to that manufactured in Example 1, energization was performed while maintaining the pn diode in a room temperature (25 ° C.) temperature environment, and the same energization test as in Example 1 was performed. . The forward voltage Vf before and after the energization test was measured, and the difference ΔVf was used as an index of energization deterioration. The results of the energization test are shown in FIG.
[Comparative Example 4]
Using a pn diode similar to that manufactured in Example 1, energization was performed while maintaining the pn diode in a temperature environment of 300 ° C., and an energization test similar to that in Example 1 was performed. The forward voltage Vf before and after the energization test was measured, and the difference ΔVf was used as an index of energization deterioration. The results of the energization test are shown in FIG.
[Example 7]
A number of pn diodes similar to those manufactured in Example 1 were manufactured, and energization was performed while maintaining the pn diodes in a temperature environment of 400 ° C., and an energization test similar to that of Example 1 was performed. The forward voltage Vf before and after the energization test was measured, and the distribution of these differences ΔVf was obtained. The results are shown in FIG.
[Comparative Example 5]
A large number of pn diodes similar to those manufactured in Example 1 were manufactured, and energization was performed while maintaining the pn diodes in a room temperature (25 ° C.) temperature environment, and the same energization test as in Example 1 was performed. It was. The forward voltage Vf before and after the energization test was measured, and the distribution of these differences ΔVf was obtained. The results are shown in FIG.

FIG. 1 is a cross-sectional view showing the vicinity of an interface between a SiC single crystal substrate and an epitaxial film formed from the surface by a step flow growth technique. FIG. 2 is a cross-sectional view of a pn diode fabricated using a SiC single crystal substrate having an epitaxial film formed on the surface. FIG. 3 is a graph showing the results of energization tests in Examples and Comparative Examples, and shows the relationship between the temperature of the pn diode and ΔVf during energization operation. FIG. 4 is a graph showing the distribution of ΔVf obtained by conducting an energization test on a number of prototyped pn diodes at room temperature (upper side) and 400 ° C. (lower side). FIG. 5 is a conceptual diagram of a photoluminescence image of the SiC epitaxial film in which the pn diode is continuously energized at each temperature from room temperature to 450 ° C. FIG. 6 is a schematic cross-sectional view of various SiC bipolar elements. FIG. 7 is a diagram for explaining an example in which a temperature control device for controlling the temperature of the SiC bipolar element is provided. FIG. 8 is a diagram for explaining an example in which a temperature control device for controlling the temperature of the SiC bipolar element is provided. FIG. 9 is a diagram for explaining an example in which a temperature control device for controlling the temperature of the SiC bipolar element is provided. FIG. 10 is a diagram illustrating an operation sequence in the case where the energization is urgently stopped when the SiC bipolar element falls below a predetermined temperature. FIG. 10 (a) is a normal operation, and FIG. 10 (b) is an operation in an abnormal state. Indicates the sequence.

Explanation of symbols

1 SiC single crystal substrate 2a n-type epitaxial film 2b p-type epitaxial film (or p-type implantation layer)
3 Basal plane dislocation 4 Threading edge dislocation 5 Crystal plane 21 Substrate 23 Drift layer 24 p-type junction layer 25 p + type contact layer 26 JTE
27 Oxide film 28 Cathode electrode 29 Anode electrode 31 Stacking fault 41 Thyristor 42 GTO thyristor 43 IGBT
51 n-type layer 52 p-type layer 53 cathode electrode 54 anode electrode 55 gate electrode 56 emitter electrode 57 collector electrode 58 oxide film 61 operation control device 62 temperature control device 63 SiC bipolar element 64 electrode 65 temperature sensor 66 heater 71 SiC single crystal substrate 72 Epitaxial film 73 pn diode 74 temperature detection element 81 pn diode 82 heater 83 temperature detection element θ off angle

Claims (10)

A method for operating a bipolar semiconductor device in which electrons and holes recombine when energized inside a silicon carbide epitaxial film grown from the surface of a silicon carbide single crystal substrate,
A method for operating a bipolar semiconductor device, wherein the bipolar semiconductor device is energized while being maintained at a temperature of 350 ° C. or higher in order to prevent an increase in the stacking fault area that causes energization deterioration.   2. The bipolar semiconductor device according to claim 1, wherein the bipolar semiconductor device is energized while maintaining the temperature at 350 ° C. or higher using a temperature control device for heating the bipolar semiconductor device. 3. Driving method.   3. The method of operating a bipolar semiconductor device according to claim 2, wherein the temperature control device starts energization after the bipolar semiconductor device reaches a temperature of 350 [deg.] C. or higher.   4. The method of operating a bipolar semiconductor device according to claim 2, wherein the temperature control device stops energization while maintaining the bipolar semiconductor device at a temperature of 350 [deg.] C. or higher.   5. The operation method of a bipolar semiconductor device according to claim 2, wherein energization is stopped when the temperature of the bipolar semiconductor device is lowered to a temperature lower than 350 ° C. by the temperature control device.   The bipolar semiconductor device according to any one of claims 1 to 5, wherein a bipolar semiconductor device manufactured using a substrate in which a hexagonal silicon carbide epitaxial film is grown from the surface of a hexagonal silicon carbide single crystal substrate is used. A method for operating a semiconductor device.   A substrate in which a hexagonal quadruple periodic silicon carbide epitaxial film is grown from the surface of a hexagonal tetraperiodic silicon carbide single crystal substrate, and a hexagonal hexagonal hexagonal crystal from the surface of a hexagonal hexaperiodic silicon carbide single crystal substrate. Bipolar fabricated with a substrate on which a periodic silicon carbide epitaxial film is grown or a substrate on which a hexagonal double periodic silicon carbide epitaxial film is grown from the surface of a hexagonal double periodic silicon carbide single crystal substrate The bipolar semiconductor device operating method according to claim 6, wherein a bipolar semiconductor device is used.   2. A bipolar semiconductor device manufactured by using a substrate obtained by growing a rhombus 15-cycle periodic silicon carbide epitaxial film from the surface of a rhombus 15-cycle silicon carbide single crystal substrate. A method for operating the bipolar semiconductor device according to any one of? A bipolar semiconductor device in which electrons and holes are recombined when energized inside a silicon carbide epitaxial film grown from the surface of a silicon carbide single crystal substrate,
A bipolar semiconductor device, wherein a bipolar element and a temperature detecting element for detecting the temperature of the bipolar element are formed on the same silicon carbide single crystal substrate. A bipolar semiconductor device in which electrons and holes are recombined when energized inside a silicon carbide epitaxial film grown from the surface of a silicon carbide single crystal substrate,
2. A bipolar semiconductor device comprising: a bipolar element, a heater for heating the bipolar element, and a temperature detecting element for detecting the temperature of the bipolar element formed on the same silicon carbide single crystal substrate.

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