JPH11150273A - Dielectric isolation semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which enables reduction in capacitance, while maintaining level of withstand voltage. SOLUTION: This device has an n-type semiconductor layer 1 formed on an n-type Si-made semiconductor support substrate 10 via an insulation layer 11 with an n<+> -type drain region, n<+> -type source region and p-type well region formed in the semiconductor layer 1 and with a drain electrode 7, a source electrode 8 and a gate electrode 6 formed on the surface of the semiconductor layer 1, and a field plate 12 connected to the gate electrode 6. The field plate 12 is formed on a gate oxide film 5 and extends to an oxide thin film 5', formed on a drift region composed of the wiring layer 1. The thin film 5' has approximately the same thickness as that of the oxide film 5.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dielectric isolation type semiconductor device utilizing an SOI structure.

[0002]

2. Description of the Related Art In recent years, in OA equipment, information communication equipment, lighting equipment, etc., it has been desired to reduce the size of power supply circuits and reduce power consumption. Attempts have been made in various places. 2. Description of the Related Art A dielectric isolation type semiconductor device has attracted attention as a main device of a power supply circuit in this field. As this type of dielectric isolation type semiconductor device, a single crystal silicon substrate is provided with an insulating film made of a silicon oxide film interposed therebetween. Lateral MOSFET (LDMOSFET: Lateral Double D) using a so-called SOI (Silicon on Insulator) substrate provided with a single crystal silicon layer
iffused MOSFET).

FIG. 5 shows a conventional LDM using an SOI substrate.
OSFET (hereinafter referred to as SOI-LDMOSFET)
FIG. SOI-LDMOSFET shown in FIG.
An insulating layer 11 made of a buried oxide film is formed on a semiconductor supporting substrate 10 made of an n-type silicon substrate or a p-type silicon substrate, and an n-type semiconductor layer made of an n-type silicon layer formed on the insulating layer 11 1, a p-type well region 4 and an n ⁺ -type drain region 2 are formed apart from each other,
⁺ -Type source region 3 is formed in p-type well region 4. Here, the p-type well region 4 is formed to a depth reaching the insulating layer 11. The drain electrode 7 is provided in the n ⁺ -type drain region 2, the source electrode 8 is provided in a part of the p-type well region 4 and a part of the n ^{+ -type} source region 3, and the p-type well region 4 is provided.
A field plate 12 made of polycrystalline silicon or the like having conductivity via a gate oxide film 5 (gate insulating film) and a gate electrode 6 connected to the field plate 12 are formed in a part of the substrate. Note that the n-type semiconductor layer 1 forms a drift region. By the way, the field plate 12 extends over the field oxide film 9. Here, the field oxide film 9 has a much larger thickness than the gate oxide film 5. FIG.
Reference numeral 13 denotes an insulating film.

The n-channel SOI-LDM shown in FIG.
The OSFET operates similarly to a normal double diffused metal oxide semiconductor device. By the way, the n-channel SO shown in FIG.
When a reverse bias is applied between the drain and the source in the I-LDMOSFET, depletion occurs in the direction of the n ⁺ -type drain region 2 from the junction interface between the p-type well region 4 and the n-type silicon layer 1 in accordance with the reverse bias voltage. Although the layer is expanded, the field plate 12 short-circuited to the gate electrode 6 is provided, so that the expansion of the depletion layer near the junction and the electric field distribution can be optimized (the surface electric field concentrated near the junction can be reduced), and the high drain -A source-to-source voltage can be obtained. Generally, the drain of SOI-LDMOSFET
Source breakdown voltage (hereinafter, abbreviated as tolerance) is a high breakdown voltage structure such as field plate 12, and the p-type well region 4 n ⁺
Is determined by the drift region distance Ld from the drain region 2, the thickness Tsoi of the n-type semiconductor layer 1 (that is, the drift region), the thickness Tbox of the insulating layer 11, and the like, and is used for OA equipment and information wiring equipment. A body separation type semiconductor device requires a withstand voltage of 30 V to 200 V, and a dielectric separation type semiconductor device used for lighting equipment has a breakdown voltage of 200 V to 1000 V.
Is required.

In these devices, there is a strong demand for low power consumption and high performance, and high-speed operation and miniaturization of a dielectric isolation type semiconductor device constituting a part of a power supply circuit of the device are required. Therefore, low power consumption is required, and it is important to reduce the parasitic capacitance of the dielectric isolation type semiconductor device. As shown in FIG. 6, the parasitic capacitance of the SOI-LDMOSFET includes a gate-drain capacitance Cgd, a gate-source capacitance Cgs, a drain-source capacitance Cds, a drain-substrate capacitance Cdsub, and the like.

When the voltage applied to the drain electrode 7 is zero,
Each of the above capacities is determined as follows. Gate Dray
The capacitance Cgd between the capacitors is the capacitance Cg shown in FIG.₁(Parasitic capacitance) and
Capacity C _Two(Parasitic capacitance). Where the capacity
C₁Is an oxide thin film 5 ′ having substantially the same thickness as the gate oxide film 5.
And extension of the field plate 12 sandwiching the oxide thin film 5 '
Intermediate part 12b of part 12b₁And n-type semiconductor layer 1
Is the capacitance of the capacitor. Also, the capacity C_TwoIs
Field oxide film 9 and a field oxide film 9
Tip portion 12b of extension 12b of metal plate 12_Twoas well as
The capacitance of the capacitor composed of the n-type semiconductor layer 1
You. Note that Lover in FIG.
Intermediate portion of the extension 12b extended on the oxide thin film 5 '
12b₁Lfp is the field plate 12
Extending on the field oxide film 9 out of the extending portion 12b
Tip 12b_TwoIndicates the distance of

The gate-source capacitance Cgs is a capacitance of a capacitor composed of the gate oxide film 5, the base end 12a of the field plate 12 sandwiching the gate oxide film 5, and the p-type well region 4. In addition, the drain-source capacitance Cds corresponds to the built-in potential (diffusion potential) and corresponds to the pn junction (the p-type well region 4 and the n-type semiconductor layer 1).
The capacitance is determined by the distance of the depletion layer extending from the junction between the p-type well region 4 and the n-type semiconductor layer 1.

The drain-substrate capacitance Cdsub is the capacitance of a capacitor composed of the insulating layer 11, the n-type semiconductor layer 1 sandwiching the insulating layer 11, and the semiconductor supporting substrate 10. Based on the capacitance described above, the SOI-LDMOS
The input capacitance Ciss and output capacitance Coss of the FET are defined as follows. Ciss = Cgd + Cgs Coss = Cgd + Cds + Cdsub Here, the cut-off frequency Ft of the SOI-LDMOSFET
(1 / maximum gate operation speed) and power consumption P are Ron for on-resistance, Irms for the root mean square value of drain current, N for circuit constant, Vd for input voltage, Vgs for gate voltage, f for operating frequency, If the conductance is gm, it is expressed as follows (I. Kim et al, 1995 International Sympo
sium on Power Semiconductor Devices and ICs, pp309
314). Ft = gm / (2π × Ciss) P = Ron × Irms ² + N × Coss × Vd ² × f + Ciss × V
gs ² × f From these equations, the high-speed operation of the SOI-LDMOSFET (Y. Suzuki et al, 1995 International Symposium on P
It can be seen that the parasitic capacitance can be reduced in order to achieve low power consumption and lower semiconductor devices and ICs, pp. 303-308).

[0009]

However, in the conventional SOI-LDMOSFET shown in FIG. 5, the field plate 12 is extended to the field oxide film 9 on the n-type semiconductor layer 1 in order to maintain the breakdown voltage. because it is, minute by the above-mentioned capacitance C ₂ gate-drain capacitance C
There is a problem that gd becomes large and hinders high-speed operation and low power consumption of the SOI-LDMOSFET. On the other hand, if the field plate 12 extended on the field oxide film 9 is removed, there is a problem that the withstand voltage is reduced, and it has been difficult to simultaneously achieve the reduction in capacity and the maintenance of the withstand voltage.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a dielectric isolation type semiconductor device capable of reducing a capacitance while maintaining a withstand voltage.

[0011]

According to a first aspect of the present invention, there is provided a first conductive type semiconductor layer formed on a semiconductor support substrate via an insulating layer. A source region of the second conductivity type and a drain region of the second conductivity type are formed apart from each other, a well region of the second conductivity type is formed surrounding the source region, and a well interposed between the source region and the drain region A field plate made of a conductive layer formed on the region with a gate insulating film interposed therebetween, and a gate electrode connected to the field plate, wherein the field plate is formed via an oxide film having substantially the same thickness as the gate insulating film. And extending above the semiconductor layer interposed between the well region and the drain region. The withstand voltage between the drain and the source is provided by providing the field plate. Of course, the field plate is extended through an oxide film of approximately the same thickness as the gate insulating film, so that the field oxide film is thicker than the conventional gate insulating film. The gate-drain capacitance can be reduced as compared with the case where it is extended up, and as a result, the capacitance can be reduced while maintaining the drain-source breakdown voltage.

According to a second aspect of the present invention, in the first aspect, the extension distance of the field plate extending above the semiconductor layer and the drift region distance between the well region and the drain region are zero. <Extension distance <Drift area distance-
0.5 μm and 0.5 μm <drift region distance <1
0 μm, and the product of the impurity concentration of the semiconductor layer and the thickness of the semiconductor layer is 6 × 10 ¹¹ cm ^{−2 to} 4 × 10
^{Since it is 12} cm ^-2 , it is possible to secure a drain-source breakdown voltage of 30 V or more.

According to a third aspect of the present invention, in the first aspect, the gate oxide film has a thickness of 0.03 μm to 0.1 μm.
Therefore, there is no need to significantly change the thickness of the gate oxide film from the past, and it is possible to reduce the gate-drain capacitance and the gate-source capacitance without greatly changing the process for adjusting the threshold value. it can. Claim 4
The invention according to claim 1, wherein the thickness of the insulating layer is 1
Since the thickness is from 4 μm to 4 μm, warpage caused by providing an insulating layer of a so-called SOI wafer including a semiconductor support substrate, an insulating layer, and a semiconductor layer in a manufacturing process can be reduced, and there is no process restriction due to warpage of the SOI wafer. In addition, the capacitance between the drain and the semiconductor supporting substrate can be reduced.

According to a fifth aspect of the present invention, in the first aspect of the present invention, since the thickness of the semiconductor layer is 0.2 μm to 5 μm, the well region and the semiconductor layer can be connected without significantly increasing the process time required for forming the well region. Can be reduced by the pn junction. According to a sixth aspect of the present invention, in the first aspect of the invention, since the insulating layer is formed of a material having a lower dielectric constant and a higher thermal conductivity than SiO ₂ , the capacitance between the drain and the semiconductor supporting substrate can be reduced. Can be. Further, heat generated in the semiconductor layer due to on-resistance and drain current can be efficiently released to the semiconductor support substrate side, and heat generation can be suppressed, so that thermal destruction can be prevented.

According to a seventh aspect of the present invention, in the first aspect of the invention, since the semiconductor layer is formed of a semiconductor material having a band gap wider than Si, the on-resistance is low and the withstand voltage between the drain and source is high. At the same time, heat generated in the semiconductor layer can be efficiently released to the semiconductor support substrate side, and heat generation can be suppressed, so that thermal destruction can be prevented.

[0016]

FIG. 1 is a sectional view of a dielectric isolation type semiconductor device according to this embodiment. The dielectric isolation type semiconductor device shown in FIG. 1 is an n-channel SOI-LDMOSFET and has a basic structure substantially the same as that of the conventional structure.

In this embodiment, the field plate 12
And the structure of the gate electrode 6 is different from the conventional structure. That is, in this embodiment, the field plate 12 short-circuited with the gate electrode 6 is replaced with the gate oxide film 5 (gate insulating film).
And an oxide thin film 5 ′ having substantially the same thickness as the gate oxide film 5, and the distance between the extension 12 b of the field plate 12 and the n-type semiconductor layer 1 is substantially equal to the thickness of the gate oxide film 5. Equal points are different. Here, the gate oxide film 5 and the oxide thin film 5 ′ can be formed simultaneously.

FIG. 2 shows the relationship between the impurity concentration of n-type semiconductor layer 1 and n.
The product Dose with the thickness of the semiconductor layer 1 is 1 × 10 ¹² cm ⁻²
The relationship between the withstand voltage between the drain and the source, which is assumed to be constant, and the output capacitance Coss described in the conventional example is shown. The horizontal axis indicates the withstand voltage, and the vertical axis indicates the output capacitance Coss. Further, A shown by a solid line in FIG. 2 indicates the n-channel SOI-
The output capacitance of the LDMOSFET and the b
The output capacitance of the channel SOI-LDMOSFET,
The output capacitance is indicated by a relative value between the present embodiment and the conventional example. In the present embodiment, since the field plate 12 extends only on the oxide thin film 5 ', the gate-drain capacitance Cgd is reduced as compared with the related art, and the output capacitance Coss is smaller than that of the related art when compared at the same withstand voltage. Is reduced.

FIG. 3 shows that the product Dose of the impurity concentration of the n-type semiconductor layer 1 as the drift region and the thickness of the n-type semiconductor layer 1 is constant at 1 × 10 ¹² cm ⁻² based on the structure shown in FIG. By varying the extending distance Lover of the field plate 12 above the n-type semiconductor layer 1, the drift region distance Ld
The result of examining the relationship between (drift distance Ld) and withstand voltage is shown. Here, A in FIG. 3 is Lover = 0 μm, and B is Lover
= Ld, C is Lover = Ld-0.5 μm, D is Lover =
Ld-1 μm, E = Lover = Ld−2 μm, F = Lover
= Ld -4 μm, G is Lover = Ld-6 μm, H is Lov
The case where er = Ld-8 μm is shown.

FIG. 4 shows the result of examining the relationship between the product Dose and the breakdown voltage by changing the extension distance Lover and the drift region distance Ld. A, B, and C in FIG.
Assuming that over = Ld, Ld is 0.5 μm, 1 μm, 2 μm
It is a case where it changed. In FIG. 4, D, E and F are Lover = Ld−0.5 μm and Ld is 0.5 μm.
m, 1 μm, and 2 μm.

3 and 4, the extension Lover of the field plate 12 above the n-type semiconductor layer 1 (drift region), the p-type well region 4 and the n ⁺ -type drain region 2
If the relationship between the drift region distance Ld and the product Dose of the impurity concentration of the n-type semiconductor layer 1 and the thickness of the n-type semiconductor layer 1 satisfies the following relationship, a dielectric material for OA equipment or the like can be used. 30 required when applying a separated type semiconductor device
A withstand voltage of about V to 200 V can be secured. 0 <Lover <Ld−0.5 μm 0.5 μm <Ld <10 μm 6 × 10 ¹¹ cm ⁻² <Dose <4 × 10 ¹² cm ⁻² The thickness Tgate of the gate oxide film 5 is set to 0.03 μm to 1
μm, a normal gate applied voltage of 10 V
To the extent, the quality of the gate oxide film 5 is prevented from deteriorating, and the gate-drain capacitance C described in the conventional example can be prevented without changing the process such as threshold value adjustment.
gd and the gate-source capacitance Cgs can also be reduced.

Further, by setting the thickness Tbox of the insulating layer 11 made of a buried oxide film (SiO ₂ ) to 1 μm to 4 μm, an SOI wafer can be easily manufactured.
Further, since the warpage of the SOI wafer can be reduced, the drain-substrate capacitance Cdsub described in the conventional example can also be reduced without the difficulty of the process due to the warpage of the SOI wafer.

By setting the thickness Tsoi of the n-type semiconductor layer 1 (drift region) to 0.2 μm to 5 μm,
The drain-source capacitance Cds can also be reduced without significantly increasing the processing time required for forming the p-type well region 4 from the prior art. Also, as the insulating layer 11, instead of SiO ₂ , AlN (aluminum nitride)
Alternatively, when formed of a material having a lower dielectric constant and higher thermal conductivity than SiO ₂ other than AlN, the drain-substrate capacitance Cdsub can be reduced, and the n-type semiconductor layer 1 (drift region ) Can be efficiently released to the semiconductor support substrate 10 side to suppress heat generation and prevent thermal destruction.

The n-type semiconductor layer 1 (drift region)
Is formed of SiC having higher mobility, higher thermal conductivity and higher electric field strength than Si, or a material having similar characteristics and a wider band gap than Si,
The on-resistance decreases, the breakdown voltage increases, and heat generated in the n-type semiconductor layer 1 (drift region) can be efficiently released to the semiconductor support substrate 10 side to suppress heat generation, thereby preventing thermal destruction. be able to.

[0025]

According to the first aspect of the present invention, a semiconductor layer of a first conductivity type formed on a semiconductor supporting substrate via an insulating layer includes:
A source region of the first conductivity type and a drain region of the second conductivity type are formed apart from each other, a well region of the second conductivity type is formed surrounding the source region, and is formed between the source region and the drain region. A field plate formed of a conductive layer formed on the intervening well region with a gate insulating film interposed therebetween; and a gate electrode connected to the field plate. The field plate has an oxide film having substantially the same thickness as the gate insulating film. Since it extends above the semiconductor layer interposed between the well region and the drain region via the film, it is of course possible to increase the withstand voltage between the drain and the source by providing the field plate. Since the field plate extends through an oxide film having substantially the same thickness as the gate insulating film, the field plate is thicker than the conventional gate insulating film. Gate-drain capacitance can be reduced as compared with the case where the gate oxide film extends over the oxide film, and as a result, it is possible to reduce the capacitance while maintaining the drain-source breakdown voltage. effective.

According to a second aspect of the present invention, in the first aspect, the extension distance of the field plate extending above the semiconductor layer and the drift region distance between the well region and the drain region are zero. <Extension distance <Drift area distance-
0.5 μm and 0.5 μm <drift region distance <1
0 μm, and the product of the impurity concentration of the semiconductor layer and the thickness of the semiconductor layer is 6 × 10 ¹¹ cm ^{−2 to} 4 × 10
^{Since it is 12} cm ^-2 , there is an effect that a drain-source breakdown voltage of 30 V or more can be secured.

According to a third aspect of the present invention, in the first aspect, the thickness of the gate oxide film is 0.03 μm to 0.1 μm.
Therefore, there is no need to significantly change the thickness of the gate oxide film from the past, and it is possible to reduce the gate-drain capacitance and the gate-source capacitance without greatly changing the process for adjusting the threshold value. There is an effect that can be.

According to a fourth aspect of the present invention, in the first aspect of the present invention, since the thickness of the insulating layer is 1 μm to 4 μm, the insulating layer of a so-called SOI wafer which is composed of a semiconductor supporting substrate, an insulating layer and a semiconductor layer in a manufacturing process. Can be reduced, and there is an effect that the capacity between the drain and the semiconductor supporting substrate can be reduced without restricting the process due to the warpage of the SOI wafer.

According to a fifth aspect of the present invention, in the first aspect of the present invention, since the thickness of the semiconductor layer is 0.2 μm to 5 μm, the well region and the semiconductor layer can be connected without significantly increasing the processing time required for forming the well region. Has the effect that the capacitance due to the pn junction can be reduced. According to a sixth aspect of the present invention, in the first aspect, the insulating layer is made of Si.
Since it is formed of a material having a lower dielectric constant and a higher thermal conductivity than O _2, the capacitance between the drain and the semiconductor supporting substrate can be reduced. Further, the heat generated in the semiconductor layer due to the on-resistance and the drain current can be efficiently released to the semiconductor supporting substrate side, and the heat generation can be suppressed, so that there is an effect that the thermal destruction can be prevented.

According to a seventh aspect of the present invention, in the first aspect, the semiconductor layer is formed of a semiconductor material having a band gap wider than that of Si, so that the on-resistance is low and the drain-source withstand voltage is high. At the same time, heat generated in the semiconductor layer can be efficiently released to the semiconductor support substrate side, and heat generation can be suppressed, so that there is an effect that thermal destruction can be prevented.

[Brief description of the drawings]

FIG. 1 is a sectional view showing an embodiment.

FIG. 2 is a graph showing a relationship between a withstand voltage and an output capacitance according to the first embodiment.

FIG. 3 is a graph showing a relationship between a drift region distance and a withstand voltage according to the first embodiment.

FIG. 4 is a graph showing a relationship between a product Dose and a withstand voltage according to the first embodiment.

FIG. 5 is a sectional view showing a conventional example.

FIG. 6 is an explanatory diagram of a parasitic capacitance according to the embodiment.

FIG. 7 is an explanatory diagram of a parasitic capacitance according to the embodiment.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 n-type semiconductor layer 2 n ⁺ -type drain region 3 n ^{+ -type} source region 4 p-type well region 5 gate oxide film 5 ′ oxide thin film 7 drain electrode 8 source electrode 10 semiconductor support substrate 11 insulating layer 12 field plate 12 b extension 13 Insulating film

Continued on the front page (72) Inventor Yoshifumi Shirai 1048, Kazuma Kadoma, Kadoma, Osaka Prefecture Inside Matsushita Electric Works Co., Ltd. ▲ Taka ▼ Hinoji No.1048 Kadoma, Kadoma, Osaka Prefecture Inside Matsushita Electric Works, Ltd. (72) Inventor Takeshi Yoshida 1048 Kadoma, Kazuma, Kadoma, Osaka Prefecture Inside Matsushita Electric Works, Ltd.

Claims (7)

[Claims] A first conductive type source region and a second conductive type drain region formed in a first conductive type semiconductor layer formed on a semiconductor support substrate via an insulating layer; And a field plate formed of a conductive layer formed via a gate insulating film on a well region interposed between the source region and the drain region, wherein a well region of the second conductivity type is formed surrounding the source region. And a gate electrode connected to the field plate, wherein the field plate extends above a semiconductor layer interposed between the well region and the drain region via an oxide film having substantially the same thickness as the gate oxide film. A dielectric isolation type semiconductor device characterized by being formed. 2. An extension distance of a field plate extending above a semiconductor layer and a drift region distance between a well region and a drain region are 0 <extension distance <drift region distance−0.5 μm. In addition, the relationship of 0.5 μm <drift region distance <10 μm is satisfied, and the product of the impurity concentration of the semiconductor layer and the thickness of the semiconductor layer is 6 × 10 ¹¹ cm ^{−2 to} 4 × 10 ¹² cm ^−2. 2. The dielectrically isolated semiconductor device according to claim 1, wherein: 3. The dielectric isolation type semiconductor device according to claim 1, wherein the thickness of the gate oxide film is 0.03 μm to 0.1 μm. 4. The dielectrically isolated semiconductor device according to claim 1, wherein the thickness of the insulating layer is 1 μm to 4 μm. 5. The semiconductor layer has a thickness of 0.2 μm to 5 μm.
2. The dielectric isolation type semiconductor device according to claim 1, wherein 6. The dielectric isolation type semiconductor device according to claim 1, wherein the insulating layer is formed of a material having a lower dielectric constant and a higher thermal conductivity than SiO ₂ . 7. The dielectric isolation type semiconductor device according to claim 1, wherein the semiconductor layer is formed of a semiconductor material having a band gap wider than that of Si.