KR19980084367A - Modeling Method for Reduced Surface Field Transverse Double-Diffusion Morse Transistor Using Silicon-on-Insulator Substrate - Google Patents

Abstract

A modeling method for a reduced surface electric field (RESURF) type lateral double-diffusion MOS (LDMOS) transistor using a silicon-on-insulator (SOI) substrate is disclosed. By representing the breakdown voltage BVVF of the transistor as a function of the concentration Nepi of the drift region and the thickness Tbox of the buried oxide layer, the optimum length Ldr and the thickness of the drift region are applied by applying the condition that the breakdown in the horizontal direction and the vertical breakdown occur simultaneously. Find the depi. In addition, the on-resistance RON of the transistor is represented by the term of the channel resistance Rch and the resistance Rdr of the drift region, so that the optimum on-resistance RON using the length Ldr and the concentration Nepi of the optimum drift region obtained from the breakdown voltage BVVF is obtained. Obtain

Description

Modeling Method for Reduced Surface Field Transverse Double-Diffusion Morse Transistor Using Silicon-on-Insulator Substrate

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a modeling method of a semiconductor device, and more particularly to a reduced surface field type lateral double-diffusion MOS transistor using a silicon-on-insulator (SOI) substrate. The present invention relates to a modeling method of a RESURF type SOI LDMOS transistor capable of presenting an analytical model for breakdown voltage and ON resistance characteristics in a lateral double diffused metal oxide semiconductor transistor.

Recently, the trend of semiconductor technology is to integrate power devices such as DMOS transistors and insulated gate field effect transistors (IGFETs) with high density. The above-mentioned power devices, which are being widely used as individual devices and power integrated circuits (ICs), are formed with a channel of double diffusion inside the device.

In particular, the DMOS transistor is a transistor made by using double diffusion, and impurity regions having different conductivity types are formed by sequentially diffusing impurities of different conductivity types through holes drilled in the insulating layer. Since the DMOS transistor has a double diffusion structure, a short channel can be made with high precision and high speed operation is possible.

On the other hand, in recent years, so-called silicon-on-insulator (SOI) technology that uses an insulating substrate to effectively separate the active elements formed on the silicon substrate is attracting attention. According to the above SOI technology, mutual separation between devices is achieved by forming active devices in individual silicon islands supported on the insulating substrate. Thus, as compared to bulk silicon structures, SOI technology can not only provide good integration density, but can also reduce the number of processes. As described above, the active element formed on the SOI substrate is called an SOI element. Since the parasitic capacitance of the SOI element is significantly reduced compared to the bulk silicon element, it is possible to obtain high circuit operation speed and low power consumption.

Accordingly, a so-called reduced surface field type (RESURF type) LDMOS transistor in which a lateral double diffusion MOS (LDMOS) transistor is formed on the top of the SOI substrate is obtained. K. Proposed by S.K. Chung et al.

The RESURF type SOI LDMOS transistor includes an SOI substrate having n-epitaxial layers stacked on top of an n-type semiconductor substrate with a buried insulating layer, a gate electrode formed on the SOI substrate with a gate oxide film on the SOI substrate, and the SOI substrate. A p- body region formed on the surface of the substrate, an n + source region formed on the surface of the SOI substrate and self-aligned to the gate electrode, and surrounded by the p- body region, a gate outside the gate electrode An n + drain region formed on the surface of the SOI substrate non-self-aligned to an electrode, a channel region formed on the surface of the p− body region overlapping the gate electrode, and p− in the n + drain region N- drift regions that isolate body regions.

However, analytical models for electrical characteristics, such as breakdown voltage and on-resistance characteristics, in the RESURF type SOI LDMOS transistor having the above-described structure have not been proposed.

Accordingly, it is an object of the present invention to provide a modeling method for a RESURF type SOI LDMOS transistor that can present an analytical model for breakdown voltage and on-resistance characteristics.

1 is a cross-sectional view of a reduced surface field type silicon-on-insulator double-diffusion MOS transistor according to the present invention.

* Explanation of symbols for main parts of drawings *

100 ... n-type substrate 102 ... investment insulation layer

104 ... n- epitaxial layer 106 ... n- drift region

108 ... gate electrode 110 ... p-body region

112 ... n + source region 114 ... n + drain region

In order to achieve the above object, the present invention provides an SOI substrate comprising a first conductive silicon layer stacked on top of a semiconductor substrate with a buried oxide layer, a gate electrode formed on the SOI substrate, and self-aligning to the gate electrode. A high concentration first conductivity type source region, a high concentration first conductivity type drain region formed outside the gate electrode, a second conductivity type body region surrounding the source region, and the first conductivity type drain region In the modeling method for the RESURF type LDMOS including a first conductivity type drift region defined between the second conductive type and the body region,

By expressing the breakdown voltage BVVF of the transistor as a function of only the concentration Nepi of the drift region and the thickness Tbox of the buried oxide layer, the optimum length of the drift region Ldr and Obtaining a thickness depi; And

By expressing the on-resistance RON of the transistor in terms of the channel resistance Rch and the resistance Rdr of the drift region, an optimal on-resistance RON is obtained using the length Ldr and the concentration Nepi of the optimum drift region obtained from the breakdown voltage BVVF. It provides a modeling method for a reduced surface field-type lateral double diffusion MOS transistor comprising a step.

According to the present invention, the breakdown voltage of a RESURF type SOI LDMOS transistor is expressed as a function of only the concentration of the n- drift region and the thickness of the buried oxide layer. Therefore, the optimum length and thickness of the drift region can be obtained by applying the condition that the yield in the horizontal direction and the yield in the vertical direction occur simultaneously.

In addition, the on-resistance of the RESURF type SOI LDMOS transistor is expressed in terms of the channel resistance and the resistance of the drift region. Therefore, the optimum on-resistance can be obtained using the length and concentration of the optimum drift region obtained from the model of the breakdown voltage.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a cross-sectional view of a RESURF type SOI LDMOS transistor according to the present invention.

Referring to FIG. 1, a RESURF type SOI LDMOS transistor according to the present invention includes a buried oxide layer 102 made of an oxide (SiO 2) formed on an n-type semiconductor substrate 100, and the buried oxide layer 102. It includes an SOI substrate consisting of an n- epitaxial layer 104 formed on the top of).

A gate electrode 108 is formed on the SOI substrate through a gate oxide film. The p- body region 110 is formed on the surface of the SOI substrate, the n + source region 112 is formed to be self-aligned to the gate electrode 108 and is surrounded by the p- body region 110, and the gate electrode 108. An n + drain region 114 formed by being non-self-aligned to the gate electrode 108 from the outside thereof. In addition, a channel region (not shown) is formed on a surface of the p− body region 110 overlapping the gate electrode 108, and between the n + drain region 114 and the p− body region 110. An n-drift region 106 is formed in the. Since the n− drift region 106 serves to isolate the p− region 110 from the n + drain region 114, the drain junction is formed of a reverse biased pn junction, and the depletion layer is almost the above. is in the n-drift region 106.

In the RESURF type SOI LDMOS transistor of the present invention described above, a structure having an n + / p− / n− / n + region is formed between the source region 112 and the drain region 114, and the n + drain region 114 is formed. An offset gate structure is formed in the gate electrode 108 which is formed non-magnetically.

Hereinafter, in the RESURF type SOI LDMOS transistor of the present invention having the structure described above with reference to FIG. 1, modeling of breakdown voltage and on-resistance characteristics will be described.

I. Breakdown Voltage Modeling

As shown in FIG. 1, the vertical electric field of the RESURF type SOI LDMOS transistor is formed in the structure of the n + drain region 114 / n- drift region 106 / the buried oxide layer 102, whereby the breakdown voltage is It is as shown in Formula 1.

[Equation 1]

0202020202020202 (1)

Where q is the charge, Nepi is the concentration of n-drift region 106, ksi and kox are the dielectric constants of silicon and oxide, ε0 is the dielectric constant of vacuum, Tbox is the thickness of the buried oxide layer 102, and d1 is buried The distance between the oxide layer 102 and the n + drain region 114. Moreover, yBn = 2.602 S 1010 Nepi-0.875.

On the other hand, the breakdown voltage by the horizontal electric field shown in the structure of the p-body region 110 / n- drift region 106 / n + drain region 114 is as shown in Equation 2 below.

[Equation 2]

020202020202020202020202020202020202 (2)

Where Ldr is the length of n− drift region 104 to p− body region 110 and n + drain region 114.

When breakdown occurs in a RESURF type LDMOS transistor using an SOI substrate, the optimum condition is when the breakdown voltage in the vertical direction is the same as the breakdown voltage in the horizontal direction, and at the same time, breakdown occurs simultaneously in the vertical direction and the horizontal direction.

In order to maintain the breakdown voltage and satisfy the reduced surface electric field (RESURF) condition, the thickness depi of the n-drift region 106 must satisfy the following equation (3).

[Equation 3]

0202020202020202020202020202 (3)

Here, the critical electric field Ecr = 4.010 S 103 Nepi 0.125.

Substituting Equation 3 into Equation 1, the breakdown voltage can be expressed as a function of only the concentration Nepi of the n-drift region 106 and the thickness Tbox of the buried oxide layer 102. At this time, the distance d1 between the n + drain region 114 and the buried oxide layer 102 is d1 = depi−xj. In Equation 1, the concentration Nepi of the n-drift region 106 according to the change of the breakdown voltage can be obtained. Once Nepi is obtained, d1 can be easily obtained since it is a function of Nepi.

The length Ldr of the optimal n-drift region 106 may be expressed by Equation 4 by applying the condition that Equation 1 and Equation 2 are the same, that is, the condition that the yielding in the horizontal direction and the vertical direction occurs simultaneously.

[Equation 4]

02020202020202020202020202020202020202 (4)

The optimum depi and Ldr can be calculated | required using Formula 3 and Formula 4 obtained above.

II. ON-resistance

s. Seed. RON, which is an on-resistance per width of the n-drift region 106 of the LDMOS transistor proposed by S. C. Sun et al. That is, RON is as shown in following formula (5).

[Equation 5]

02020202020202020202020202020202020202020202020202020202020202 (5)

Here, Rch and the resistance Rdr are as shown in following formulas 6 and 7, respectively.

[Equation 6]

02020202020202020202020202020202020202020202020202 (6)

[Equation 7]

0202020202020202020202 (7)

Where Lch is the channel length, μn is the mobility of electrons, Co is the capacitance of the gate oxide, VG is the gate voltage, VT is the threshold voltage, and r1 and r2 are p + body region 110 and n + drain region 114, respectively. Represents the junction depth of.

Substituting the length Ldr and the concentration Nepi of the optimal n-drift region 106 obtained from Equation 4 into Equation 7, minimum on-resistance can be obtained.

As described above, according to the present invention, the breakdown voltage BVVF of the RESURF type SOI LDMOS transistor is represented as a function of only the concentration Nepi of the n-drift region and the thickness Tbox of the buried oxide layer. Therefore, the optimum length Ldr and thickness depi of the drift region can be obtained by applying the condition that the yielding in the horizontal direction and the yielding in the vertical direction occur simultaneously.

In addition, the on-resistance RON of the RESURF type SOI LDMOS transistor is represented by the term of the channel resistance Rch and the resistance Rdr of the drift region. Therefore, the optimum on-resistance RON can be obtained using the length Ldr and the concentration Nepi of the optimum drift region obtained from the model formula of the breakdown voltage.

Although the above has been described with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the present invention without departing from the spirit and scope of the invention described in the claims below. I can understand that you can.

Claims (3)

A silicon-on-insulator substrate formed by stacking a silicon layer of a first conductivity type through a buried oxide layer on a semiconductor substrate, a gate electrode formed on the silicon-on-insulator substrate, and a high concentration self-aligned to the gate electrode. A first conductivity type source region of the transistor, a high concentration first conductivity type drain region formed outside the gate electrode, a body region of a second conductivity type surrounding the first conductivity type source region, and the first conductivity type A modeling method for a reduced surface field type lateral double diffusion MOS transistor comprising a drift region of a first conductivity type defined between a drain region of a and a body region of a second conductivity type, By expressing the breakdown voltage BVVF of the transistor as a function of only the concentration Nepi of the drift region and the thickness Tbox of the buried oxide layer, the optimum length of the drift region Ldr and Obtaining a thickness depi; And By expressing the on-resistance RON of the transistor in terms of the channel resistance Rch and the resistance Rdr of the drift region, an optimal on-resistance RON is obtained using the length Ldr and the concentration Nepi of the optimum drift region obtained from the breakdown voltage BVVF. A method for modeling a reduced surface field type lateral double diffusion MOS transistor comprising the steps of: 2. The reduced surface electric field lateral double diffusion MOS according to claim 1, wherein the vertical electric field of the transistor is formed in the structure of the drain region, the drift region, and the buried oxide layer, and thus the breakdown voltage is set. Modeling method for transistors. 2. The modeling of claim 1, wherein the vertical breakdown and the horizontal breakdown occur when the vertical breakdown voltage and the horizontal breakdown voltage are equal to each other. 3. Way.