KR100790247B1 - Lateral double diffused metal oxide semiconductor transistor and method of manufacturing the same - Google Patents

Lateral double diffused metal oxide semiconductor transistor and method of manufacturing the same Download PDF

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KR100790247B1
KR100790247B1 KR1020060135641A KR20060135641A KR100790247B1 KR 100790247 B1 KR100790247 B1 KR 100790247B1 KR 1020060135641 A KR1020060135641 A KR 1020060135641A KR 20060135641 A KR20060135641 A KR 20060135641A KR 100790247 B1 KR100790247 B1 KR 100790247B1
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region
breakdown voltage
drift region
layer
conductivity type
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고철주
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동부일렉트로닉스 주식회사
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    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
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    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66537—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a self aligned punch through stopper or threshold implant under the gate region
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors

Abstract

An LDMOS(Laterally-Diffused Metal Oxide Semiconductor) transistor and a manufacturing method thereof are provided to prevent damage of a high voltage device by improving a break down voltage of the LDMOS transistor. A second conductive-type first body region(120) is arranged on an upper portion of a drift region(100) and has a channel region(121). A second conductive-type second body region(135) is arranged adjacent to the drift region. A first conductive-type extended drain region(130) is arranged on top portion of the drift region to be separated from the first body region. A first conductive-type drain region is arranged on an upper portion of the extended drain region. A gate dielectric(160) and a gate conductive layer(170) are sequentially arranged on the channel region. A breakdown voltage increasing layer(200) is arranged on a lower portion of the first conductive-type drift region to increase a breakdown voltage by double RESURF(Reduced SURface Field). An NBL(N-Buried Layer) is arranged on a lower portion of the breakdown voltage increasing layer. A plug is electrically connected to the NBL.

Description

ＬＤＭＯＳ 트랜지스터 및 이의 제조 방법{LATERAL DOUBLE DIFFUSED METAL OXIDE SEMICONDUCTOR TRANSISTOR AND METHOD OF MANUFACTURING THE SAME}LMDMOS transistor and its manufacturing method {LATERAL DOUBLE DIFFUSED METAL OXIDE SEMICONDUCTOR TRANSISTOR AND METHOD OF MANUFACTURING THE SAME}

도 1은 본 발명의 일실시예에 의하여 작동전압을 향상시킨 LDMOS 트랜지스터를 도시한 단면도이다.1 is a cross-sectional view illustrating an LDMOS transistor having an improved operating voltage according to an embodiment of the present invention.

도 2 내지 도 6은 본 발명의 일실시예에 의한 LDMOS 트랜지스터의 제조 방법을 도시한 단면도들이다.2 to 6 are cross-sectional views illustrating a method of manufacturing an LDMOS transistor according to an embodiment of the present invention.

본 발명은 LDMOS 트랜지스터 및 이의 제조 방법에 관한 것이다. 보다 구체적으로 본 발명은 브레이크다운 전압을 크게 향상시킨 LDMOS 트랜지스터 및 이의 제조 방법에 관한 것이다.The present invention relates to an LDMOS transistor and a method of manufacturing the same. More specifically, the present invention relates to an LDMOS transistor having a greatly improved breakdown voltage and a method of manufacturing the same.

일반적으로 사용되는 전력 모스 전계효과 트랜지스터(MOSFET)는 바이폴라 트랜지스터에 비해 높은 입력 임피던스를 가지기 때문에 전력이득이 크고 게이트 구동 회로가 매우 간단하며, 유니폴라 소자이기 때문에 소자가 턴-오프 되는 동안 소수 캐리어에 의한 축적 또는 재결합에 의해 발생되는 시간지연이 없는 등의 장점을 가지고 있다. 따라서, 스위칭 모드 전력 공급장치, 램프 안정화 및 모터 구동회로 등에서의 응용이 점차 확산되고 있는 추세이다. 이와 같은 전력 MOSFET으로는 통산 플래너 확산 기술을 이용한 DMOSFET 구조가 널리 사용되고 있으며, 대표적인 LDMOS 트랜지스터가 개발된 바 있다.The commonly used power MOS field-effect transistors (MOSFETs) have higher input impedance than bipolar transistors, resulting in greater power gain and very simple gate drive circuits, and because they are unipolar devices, There is no time delay caused by accumulation or recombination. Therefore, applications in switching mode power supplies, lamp stabilization, motor drive circuits, and the like are gradually spreading. As such power MOSFETs, a DMOSFET structure using integrated planar diffusion technology is widely used, and a typical LDMOS transistor has been developed.

그러나, 최근 개발된 LDMOS 트랜지스터는 동작 전압이 약 60[V] 정도에 불과하기 때문에 동작전압이 60[V] 이상이 되는 소자에 LDMOS 트랜지스터 구조를 구현할 경우 게이트의 에지 부분에 강한 전계가 인가되어 소자가 손상되는 문제점을 갖는다.However, recently developed LDMOS transistors have an operating voltage of only about 60 [V], so when the LDMOS transistor structure is implemented in a device having an operating voltage of 60 [V] or higher, a strong electric field is applied to the edge portion of the gate. Has the problem of being damaged.

본 발명의 하나의 목적은 동작 전압을 약 100[V] 이상까지 향상시키기에 적합한 LDMOS 트랜지스터를 제공함에 있다.One object of the present invention is to provide an LDMOS transistor suitable for improving the operating voltage to about 100 [V] or more.

본 발명의 다른 목적은 상기 LDMOS 트랜지스터의 제조 방법을 제공함에 있다.Another object of the present invention is to provide a method of manufacturing the LDMOS transistor.

본 발명의 하나의 목적을 구현하기 위한 LDMOS 트랜지스터는 제1 도전형의 드리프트 영역, 상기 드리프트 영역의 상부에 배치되어 상부의 채널 영역을 갖는 제2 도전형의 제1 바디 영역, 상기 드리프트 영역과 인접한 곳에 배치된 제2 도전형의 제2 바디 영역, 상기 드리프트 영역의 상부에서 상기 제1 바디 영역과 일정간격 이격되어 배치된 제1 도전형의 확장된 드레인 영역, 상기 확장된 드레인 영역의 상부에 배치되는 제1 도전형의 드레인 영역, 상기 채널 영역 위에 순차적으로 배치되는 게이트 절연막 및 게이트 도전막, 상기 제1 도전형의 드리프트 영역의 하부에 배치되어 더블 RESURF에 의하여 항복전압을 증가시키는 항복전압 증가층, 상기 항복전압 증가층 하부에 배치된 NBL(N-Buried Layer) 및 상기 NBL과 전기적으로 연결된 플러그를 포함한다.An LDMOS transistor for realizing an object of the present invention includes a first conductive drift region, a first conductive region of a second conductivity type disposed over the drift region and having a channel region thereon, and adjacent to the drift region. A second body region of a second conductivity type disposed therein, an extended drain region of the first conductivity type disposed at a predetermined distance from the first body region above the drift region, and disposed above the extended drain region A first conductive type drain region, a gate insulating film and a gate conductive layer sequentially disposed on the channel region, and a breakdown voltage increasing layer disposed below the drift region of the first conductive type to increase the breakdown voltage by a double RESURF. And an N-Buried Layer (NBL) disposed under the breakdown voltage increasing layer and a plug electrically connected to the NBL.

본 발명의 다른 목적을 구현하기 위한 LDMOS 트랜지스터의 제조 방법은 NBL(N-buried layer) 및 NBL 상에 P형 에피텍셜층을 형성하는 단계, 상기 NBL층의 상부에 항복전압 증가층을 형성하고 항복전압 증가층 상에 N형 드리프트 영역을 형성하는 단계, 상기 드리프트 영역의 상부에 배치되어 채널 영역을 형성하는 제2 도전형의 제1 바디 영역 및 상기 드리프트 영역과 인접하게 배치된 제2 바디 영역을 형성하는 단계, 상기 드리프트 영역의 상부에서 상기 제1 바디 영역과 일정간격 이격되어 배치된 제1 도전형의 확장된 드레인 영역을 형성하는 단계, 상기 확장된 드레인 영역의 상부에 제1 도전형의 드레인 영역을 형성하는 단계, 상기 채널 영역 위에 순차적으로 배치되는 게이트 절연막 및 게이트 도전막을 형성하는 단계를 포함한다.According to another aspect of the present invention, there is provided a method of manufacturing an LDMOS transistor, including forming an N-buried layer (NBL) and a P-type epitaxial layer on the NBL, forming a breakdown voltage increasing layer on the NBL layer, and breaking down. Forming an N-type drift region on the voltage increasing layer, a first body region of a second conductivity type disposed on the drift region to form a channel region, and a second body region disposed adjacent to the drift region; Forming an extended drain region of a first conductivity type disposed at a predetermined distance from the first body region at an upper portion of the drift region; a drain of the first conductive type disposed on the extended drain region Forming a region, and forming a gate insulating layer and a gate conductive layer sequentially disposed on the channel region.

이하, 첨부된 도면들을 참조하여 본 발명의 실시예들에 따른 LDMOS 트랜지스터 및 이의 제조 방법에 대하여 상세하게 설명하지만, 본 발명이 하기의 실시예들에 제한되는 것은 아니며, 해당 분야에서 통상의 지식을 가진 자라면 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 본 발명을 다양한 다른 형태로 구현할 수 있을 것이다.Hereinafter, an LDMOS transistor and a method of manufacturing the same according to embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the following embodiments, and the general knowledge in the art. Those skilled in the art can implement the present invention in various other forms without departing from the technical spirit of the present invention.

도 1은 본 발명의 일실시예에 의하여 작동전압을 향상시킨 LDMOS 트랜지스터를 도시한 단면도이다.1 is a cross-sectional view illustrating an LDMOS transistor having an improved operating voltage according to an embodiment of the present invention.

도 1을 참조하면, 소자 분리막(110)에 의해 활성 영역이 정의되는 반도체 기판(50) 상에는 드리프트 영역(100)이 형성된다. 본 실시예에서, 드리프트 영역(100)은 인(P)을 포함한다. 드리프트 영역(100)상에는 P형 제1 바디 영역(120) 및 n-형 확장된 드레인 영역(130)이 일정 간격 이격되어 배치된다.Referring to FIG. 1, a drift region 100 is formed on a semiconductor substrate 50 in which an active region is defined by the device isolation layer 110. In the present embodiment, the drift region 100 includes phosphorus (P). The P-type first body region 120 and the n-type extended drain region 130 are disposed on the drift region 100 at predetermined intervals.

P형 제1 바디 영역(120)에는 n+형 소스 영역(140)이 배치된다. P형 제1 바디 영역(120)의 상부 영역 중 n+ 형 소스 영역(140)에 인접하고 게이트 절연막(160) 및 게이트 도전막(170)과 중첩되는 부분은 채널 영역(121)이 된다. n-형 확장된 드레인 영역(130)상에는 n+형드레인 영역(150)이 배치된다.The n + type source region 140 is disposed in the P type first body region 120. A portion of the upper region of the P-type first body region 120 adjacent to the n + -type source region 140 and overlapping with the gate insulating layer 160 and the gate conductive layer 170 becomes the channel region 121. An n + type drain region 150 is disposed on the n− type extended drain region 130.

채널 영역(121) 위에는 게이트 절연막(160)과 게이트 도전막(170)이 순차적으로 적층되고, n+ 형 소스 영역(140) 및 n+ 형 드레인 영역(150)은 배선을 통해 소스 전극과 드레인 전극과 전기적으로 연결된다.The gate insulating layer 160 and the gate conductive layer 170 are sequentially stacked on the channel region 121, and the n + type source region 140 and the n + type drain region 150 are electrically connected to the source electrode and the drain electrode through wiring. Is connected.

한편, 드리프트 영역(100)의 하부에는 공핍 영역(deplection region)을 확장시켜 브레이크다운 전압을 증가시키는 항복전압 증가층(200)이 형성된다. 본 실시예에서, 항복전압 증가층(200)은 불순물, 예를 들면, 붕소(B)를 포함한다.Meanwhile, a breakdown voltage increasing layer 200 is formed below the drift region 100 to increase the breakdown voltage by expanding the depletion region. In the present embodiment, the breakdown voltage increasing layer 200 includes an impurity, for example, boron (B).

항복전압 증가층(200)의 하부에는 NBL(N-buried layer)가 형성되고, NBL은 반도체 기판(50)에 고농도/고에너지 이온 주입된 불순물에 의하여 형성된 플러그(350)와 전기적으로 연결된다. 본 실시예에서, NBL은 플러그(350)를 통해 드레인 영역(130)과 전기적으로 연결된다.An N-buried layer (NBL) is formed below the breakdown voltage increasing layer 200, and the NBL is electrically connected to a plug 350 formed by impurities having high concentration / high energy ion implanted into the semiconductor substrate 50. In this embodiment, the NBL is electrically connected to the drain region 130 through the plug 350.

한편, 드리프트 영역(100)과 인접한 반도체 기판(50) 상에는 P형 제2 바디 영역(135)가 형성된다. P형 제2 바디 영역(135)은 접지되어 더블 RESURF(Reduced SURface Field)를 형성하여 브레이크다운 전압을 크게 향상시키는 역할을 한다.The P-type second body region 135 is formed on the semiconductor substrate 50 adjacent to the drift region 100. The P-type second body region 135 is grounded to form a double reduced surface field (RESURF), thereby greatly improving the breakdown voltage.

상술한 LDMOS 트랜지스터는 드레인 영역(130)에 바이아스(bias)가 인가되면, 공핍 영역이 항복전압 증가층(200) 및 드리프트 영역(100)으로부터 각각 확장되고, 이로 인해 공핍 영역은 크게 확장된다. 이로서, 게이트 도전막(170)의 에지 부분에 형성된 강한 전계를 풀어 브레이크다운 전압을 크게 향상시킬 수 있다.In the above-described LDMOS transistor, when a bias is applied to the drain region 130, the depletion region extends from the breakdown voltage increasing layer 200 and the drift region 100, thereby greatly expanding the depletion region. As a result, the breakdown voltage can be greatly improved by releasing a strong electric field formed at the edge portion of the gate conductive film 170.

도 2 내지 도 6은 본 발명의 일실시예에 의한 LDMOS 트랜지스터의 제조 방법을 도시한 단면도들이다.2 to 6 are cross-sectional views illustrating a method of manufacturing an LDMOS transistor according to an embodiment of the present invention.

도 2를 참조하면, LDMOS 트랜지스터를 제조하기 위해서, 먼저, NBL(300)을 먼저 형성한 후, NBL(300) 상에 P형 에피텍셜층(50)을 형성한다.Referring to FIG. 2, in order to manufacture an LDMOS transistor, first, an NBL 300 is first formed, and then a P-type epitaxial layer 50 is formed on the NBL 300.

이하, 본 실시예에서는 일반 LDMOS 트랜지스터 영역(A) 및 항복전압이 증가된 LDMOS 트랜지스터 영역(B)으로 구분하여 설명하기로 한다.In the present embodiment, a description will be made of the general LDMOS transistor region A and the LDMOS transistor region B having a higher breakdown voltage.

도 3을 참조하면, P형 에피텍셜층(50)이 형성된 후, A 영역에 드리프트 영역(20)이 먼저 형성된다. 드리프트 영역(20)을 형성하기 위한 공정 조건으로는 인(P)을 3.6E2/㎠ 개, 900KeV의 이온 주입 에너지로 이온 주입한 후 약 350분 동안 인(P)을 확산시킨다.Referring to FIG. 3, after the P-type epitaxial layer 50 is formed, the drift region 20 is first formed in the A region. As a process condition for forming the drift region 20, phosphorus (P) is implanted with ion implantation energy of 3.6 E 2 / cm 2 and 900 KeV, and then phosphorus (P) is diffused for about 350 minutes.

도 4를 참조하면, 항복 전압이 증가된 LDMOS 트랜지스터 영역인 B 영역에 인(P)과 보론(B)을 각각 이온 주입한다.Referring to FIG. 4, phosphorus (P) and boron (B) are ion implanted into region B, which is an LDMOS transistor region where the breakdown voltage is increased.

구체적으로, NBL(300)과 인접하도록 붕소(B)를 제1 이온 주입 에너지로 이온 주입하고, 이어서, 인(P)을 제1 이온 주입 에너지보다 낮은 제2 이온 주입 에너지로 이온 주입한다. 이로써, B 영역에는 붕소(B)가 주입된 영역 및 인(P)이 주입된 영역이 생성된다.Specifically, boron (B) is ion-implanted with the first ion implantation energy so as to be adjacent to the NBL 300, and then phosphorus (P) is ion-implanted with the second ion implantation energy lower than the first ion implantation energy. As a result, a region in which boron (B) is implanted and a region in which phosphorus (P) is implanted are generated in region B. FIG.

도 5를 참조하면, 붕소(B) 및 인(P)을 1150℃의 온도에서 70분 동안 확산시켜 드리프트 영역(100) 및 항복전압 증가층(200)을 형성한다.Referring to FIG. 5, boron (B) and phosphorus (P) are diffused at a temperature of 1150 ° C. for 70 minutes to form a drift region 100 and a breakdown voltage increasing layer 200.

도 6에 도시된 바와 같이 드리프트 영역(100)의 상부에 채널 영역을 형성하기 위해 제1 바디 영역(120)을 형성 및 드리프트 영역(100)과 인접하게 배치된 반도체 기판(50) 상에 제2 바디 영역(135)를 형성한다.As shown in FIG. 6, a second body is formed on the semiconductor substrate 50 formed with the first body region 120 and disposed adjacent to the drift region 100 to form a channel region on the drift region 100. Body region 135 is formed.

도 1을 다시 참조하면, 드리프트 영역(100)의 상부에서 상기 제1 바디 영역(120)과 일정간격 이격되어 배치된 제1 도전형의 확장된 드레인 영역(130)을 형성고, 확장된 드레인 영역(130)의 상부에 제1 도전형의 드레인 영역(150)을 형성한다.Referring to FIG. 1 again, an extended drain region 130 having a first conductivity type is formed on the drift region 100 and spaced apart from the first body region 120 at a predetermined interval. A drain region 150 of the first conductivity type is formed on the upper portion 130.

이어서, 채널 영역(121) 위에 순차적으로 게이트 절연막(160) 및 게이트 도전막(170)을 형성하여 LDMOS 트랜지스터를 제조한다.Subsequently, the gate insulating layer 160 and the gate conductive layer 170 are sequentially formed on the channel region 121 to manufacture an LDMOS transistor.

앞서 상술한 바에 의하면, LDMOS 트랜지스터의 브레이크다운 전압을 크게 향상시켜 LDMOS 트랜지스터를 적용한 고전압 소자의 파손 및 손상을 방지하는 효과를 갖는다.As described above, the breakdown voltage of the LDMOS transistor is greatly improved to prevent breakage and damage of the high voltage device to which the LDMOS transistor is applied.

앞서 설명한 본 발명의 상세한 설명에서는 본 발명의 실시예들을 참조하여 설명하였지만, 해당 기술분야의 숙련된 당업자 또는 해당 기술분야에 통상의 지식을 갖는 자라면 후술될 특허청구범위에 기재된 본 발명의 사상 및 기술 영역으로부터 벗어나지 않는 범위 내에서 본 발명을 다양하게 수정 및 변경시킬 수 있음을 이 해할 수 있을 것이다.Although the detailed description of the present invention has been described with reference to the embodiments of the present invention, those skilled in the art or those skilled in the art will have the spirit and scope of the present invention as set forth in the claims below. It will be understood that various modifications and variations can be made in the present invention without departing from the scope of the art.

Claims (6)

제1 도전형의 드리프트 영역;A drift region of a first conductivity type; 상기 드리프트 영역의 상부에 배치되어 상부의 채널 영역을 갖는 제2 도전형의 제1 바디 영역:A first conductive first body region disposed above the drift region and having an upper channel region: 상기 드리프트 영역과 인접한 곳에 배치된 제2 도전형의 제2 바디 영역;A second body region of a second conductivity type disposed adjacent to the drift region; 상기 드리프트 영역의 상부에서 상기 제1 바디 영역과 일정간격 이격되어 배치된 제1 도전형의 확장된 드레인 영역;An extended drain region of a first conductivity type disposed above the drift region and spaced apart from the first body region by a predetermined distance; 상기 확장된 드레인 영역의 상부에 배치되는 제1 도전형의 드레인 영역;A drain region of a first conductivity type disposed over the extended drain region; 상기 채널 영역 위에 순차적으로 배치되는 게이트 절연막 및 게이트 도전막;A gate insulating film and a gate conductive film sequentially disposed on the channel region; 상기 제1 도전형의 드리프트 영역의 하부에 배치되어 더블 RESURF에 의하여 항복전압을 증가시키는 항복전압 증가층;A breakdown voltage increasing layer disposed below the drift region of the first conductivity type to increase the breakdown voltage by a double RESURF; 상기 항복전압 증가층 하부에 배치된 NBL(N-Buried Layer); 및An N-Buried Layer (NBL) disposed under the breakdown voltage increasing layer; And 상기 NBL과 전기적으로 연결된 플러그를 포함하는 LDMOS 트랜지스터.And a plug electrically connected to the NBL. 제1항에 있어서, 상기 제1 도전형의 드리프트 영역은 인(P)을 포함하고, 상기 항복전압 증가층은 붕소(B)를 포함하는 것을 특징으로 하는 LDMOS 트랜지스터.The LDMOS transistor of claim 1, wherein the drift region of the first conductivity type includes phosphorus (P), and the breakdown voltage increasing layer includes boron (B). 제1항에 있어서, 상기 드레인 영역 및 상기 플러그는 배선에 의하여 상호 연결된 것을 특징으로 하는 LDMOS 트랜지스터.The LDMOS transistor of claim 1, wherein the drain region and the plug are interconnected by a wire. 제1항에 있어서, 상기 제2 바디 영역은 접지되는 것을 특징으로 하는 LDMOS 트랜지스터.The LDMOS transistor of claim 1, wherein the second body region is grounded. NBL(N-buried layer) 및 NBL 상에 P형 에피텍셜층을 형성하는 단계;Forming an N-buried layer (NBL) and a P-type epitaxial layer on the NBL; 상기 NBL층의 상부에 항복전압 증가층을 형성하고 항복전압 증가층 상에 N형 드리프트 영역을 형성하는 단계;Forming a breakdown voltage increasing layer on the NBL layer and forming an N-type drift region on the breakdown voltage increasing layer; 상기 드리프트 영역의 상부에 배치되어 채널 영역을 형성하는 제2 도전형의 제1 바디 영역 및 상기 드리프트 영역과 인접하게 배치된 제2 바디 영역을 형성하는 단계;Forming a first body region of a second conductivity type disposed on the drift region to form a channel region and a second body region disposed adjacent to the drift region; 상기 드리프트 영역의 상부에서 상기 제1 바디 영역과 일정간격 이격되어 배치된 제1 도전형의 확장된 드레인 영역을 형성하는 단계;Forming an extended drain region of a first conductivity type disposed on the drift region and spaced apart from the first body region by a predetermined distance; 상기 확장된 드레인 영역의 상부에 제1 도전형의 드레인 영역을 형성하는 단계;Forming a drain region of a first conductivity type on top of the extended drain region; 상기 채널 영역 위에 순차적으로 배치되는 게이트 절연막 및 게이트 도전막을 형성하는 단계를 포함하는 LDMOS 트랜지스터의 제조 방법.And forming a gate insulating film and a gate conductive film sequentially disposed over the channel region. 제5항에 있어서, 항복전압층을 형성하는 단계는The method of claim 5, wherein the forming of the breakdown voltage layer is performed. 상기 NBL과 인접하도록 붕소(B)를 제1 이온 주입 에너지로 이온 주입하는 단계;Implanting boron (B) with a first ion implantation energy to adjoin the NBL; 인(P)을 상기 제1 이온 주입 에너지보다 낮은 제2 이온 주입 에너지로 이온 주입하는 단계; 및Ion implanting phosphorus (P) with a second ion implantation energy lower than the first ion implantation energy; And 상기 붕소 및 인을 1150℃의 온도에서 70분 동안 확산시키는 단계를 포함하는 LDMOS 트랜지스터의 제조 방법.And diffusing the boron and phosphorus at a temperature of 1150 ° C. for 70 minutes.
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