JP3427704B2 - Dielectric separated type semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to derivative collector isolation type semiconductor device.

[0002]

2. Description of the Related Art In recent years, in OA equipment, information communication equipment, lighting equipment, etc., there is a demand for downsizing of power supply circuits and reduction of power consumption. Therefore, the frequency of power supply circuits is increased and passive components of the circuits are downsized. Attempts are being made everywhere. Dielectric isolation type semiconductor devices have been attracting attention as main devices of power supply circuits in this field.As dielectric isolation type semiconductor devices of this type, a single crystal silicon substrate with an insulating film made of a silicon oxide film interposed therebetween is used. A lateral MOSFET (LDMOSFET: Lateral Double D) using a so-called SOI (Silicon on Insulator) substrate provided with a single crystal silicon layer.
iffused MOSFETs) are attracting attention.

FIG. 5 shows a conventional LDM using an SOI substrate.
OSFET (hereinafter referred to as SOI-LDMOSFET)
FIG. SOI-LDMOSFET shown in FIG.
Is an n-type semiconductor layer made of an n-type silicon layer formed on an insulating layer 11 made of a buried oxide film on a semiconductor supporting substrate 10 made of an n-type silicon substrate or a p-type silicon substrate. 1, a p-type well region 4 and an n ⁺ -type drain region 2 are formed separately from each other.
^{A + type} source region 3 is formed in the p type well region 4. Here, the p-type well region 4 is formed to a depth reaching the insulating layer 11. The drain electrode 7 is provided in the n ⁺ -type drain region 2, the source electrode 8 is provided in a part of the p-type well region 4 and the n ^{+ -type} source region 3, and the p-type well region 4 is provided.
A field plate 12 made of polycrystalline silicon or the like having conductivity and a gate electrode 6 connected to the field plate 12 are formed on a part of each of them via a gate oxide film 5 (gate insulating film). The n-type semiconductor layer 1 constitutes a drift region. By the way, the field plate 12 extends to above the field oxide film 9. Here, the field oxide film 9 is much thicker than the gate oxide film 5. Also, FIG.
Reference numeral 13 indicates an insulating film.

The n-channel SOI-LDM shown in FIG.
The OSFET operates similarly to a normal double-diffused metal oxide semiconductor device. By the way, the n-channel SO shown in FIG.
Also in the I-LDMOSFET, when a reverse bias is applied between the drain and the source, the depletion in the direction of the n ⁺ -type drain region 2 from the junction interface between the p-type well region 4 and the n-type silicon layer 1 depending on the reverse bias voltage. Although the layer expands, since the field plate 12 short-circuited to the gate electrode 6 is provided, the expansion of the depletion layer near the junction and the electric field distribution can be optimized (the surface electric field concentrated near the junction can be relaxed), and the high drain can be obtained. -The voltage between sources can be obtained. Generally, the drain of SOI-LDMOSFET
The breakdown voltage between the sources (hereinafter, simply referred to as breakdown voltage) is the high breakdown voltage structure of the field plate 12, the p-type well region 4 and the n ⁺
Is determined by the drift region distance Ld from the drain region 2, the thickness Tsoi of the n-type semiconductor layer 1 (that is, the drift region), the thickness Tbox of the insulating layer 11, and the like, and is used for OA equipment and information wiring equipment. The body-separated semiconductor device requires a withstand voltage of 30V to 200V, and the dielectric-separated semiconductor device used in a lighting fixture has a voltage of 200V to 1000V.
Withstand voltage is required.

Further, in these devices, there is a strong demand for lower power consumption and higher performance, and the dielectric isolation type semiconductor device forming a part of the power supply circuit of the device is operated at high speed and is miniaturized. However, low power consumption is required, and it is becoming important to reduce the parasitic capacitance of the dielectric isolation type semiconductor device. As shown in FIG. 6, the parasitic capacitance of the SOI-LDMOSFET includes a gate-drain capacitance Cgd, a gate-source capacitance Cgs, a drain-source capacitance Cds, and a drain-substrate capacitance Cdsub.

When the voltage applied to the drain electrode 7 is zero,
The above capacities are determined as follows. Gate dray
The inter-capacitance Cgd is the capacitance C shown in FIG.₁(Parasitic capacitance) and
Capacity C ₂It is expressed as the sum of (parasitic capacitance). Where the capacity
C₁Is an oxide thin film 5'having substantially the same thickness as the gate oxide film 5.
And extension of the field plate 12 sandwiching the oxide thin film 5 '.
Middle part 12b of part 12b₁And n-type semiconductor layer 1
Is the capacity of the capacitor to be used. Also, the capacity C₂Is
Field oxide film 9 and field oxide film 9 are sandwiched between them.
Tip 12b of extension 12b of the rudder plate 12₂as well as
It is the capacitance of the capacitor composed of the n-type semiconductor layer 1.
It In addition, Lover in FIG.
An intermediate portion of the extended portion 12b extended on the oxide thin film 5 '.
12b₁Indicates the distance of the field plate, and Lfp is the field plate 12
The extended portion 12b of the magnetic field is extended on the field oxide film 9.
Tip 12b₂Indicates the distance.

The gate-source capacitance Cgs is the capacitance of a capacitor composed of the gate oxide film 5, the base end portion 12a of the field plate 12 and the p-type well region 4 which sandwich the gate oxide film 5. Further, the drain-source capacitance Cds corresponds to the built-in potential (diffusion potential), and corresponds to a pn junction (p-type well region 4 and n-type semiconductor layer 1).
It is the capacitance determined by the distance of the depletion layer extending from the junction with the p-type well region 4 and the n-type semiconductor layer 1.

The drain-substrate capacitance Cdsub is the capacitance of a capacitor composed of the insulating layer 11 and the n-type semiconductor layer 1 and the semiconductor supporting substrate 10 which sandwich the insulating layer 11. Based on the capacitance described above, SOI-LDMOS
The input capacitance Ciss and output capacitance Coss of the FET are defined as follows. Ciss = Cgd + Cgs Coss = Cgd + Cds + Cdsub where the cutoff frequency Ft of the SOI-LDMOSFET is
(1 / maximum gate operation speed) and power consumption P are as follows: on-resistance Ron, drain current root mean square value Irms, circuit constant N, input voltage Vd, gate voltage Vgs, operating frequency f, mutual If the conductance is gm, it is expressed as follows (I. Kim et al, 1995 International Sympo
sium on Power Semiconductor Devices and ICs, pp309
~ 314). Ft = gm / (2π × Ciss) P = Ron × Irms ² + N × Coss × Vd ² × f + Ciss × V
gs ² × f From these equations, high-speed operation of SOI-LD MOSFET (Y. Suzuki et al, 1995 International Symposium on P
ower Semiconductor Devices and ICs, pp303 to 308) and low power consumption can be achieved by reducing the parasitic capacitance.

[0009]

However, in the conventional SOI-LDMOSFET shown in FIG. 5, the field plate 12 is extended to above the field oxide film 9 on the n-type semiconductor layer 1 in order to maintain the breakdown voltage. Therefore, the capacitance C between the gate and the drain is equal to the capacitance C ₂ described above.
There is a problem that gd becomes large, which hinders high-speed operation and low power consumption of the SOI-LDMOSFET. On the other hand, if the field plate 12 extended on the field oxide film 9 is removed, there is a problem that the breakdown voltage is lowered, and it is difficult to satisfy both the low capacitance and the breakdown voltage maintenance at the same time.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a dielectric isolation type semiconductor device capable of reducing the capacitance while maintaining the breakdown voltage.

[0011]

In order to achieve the above object, a first conductivity type semiconductor layer is formed in a semiconductor layer of a first conductivity type formed on a semiconductor supporting substrate via an insulating layer. -Shaped source region and second-conductivity-type drain region are formed apart from each other, and a second-conductivity-type well region is formed so as to surround the source region, and the well is interposed between the source region and the drain region. A field plate formed of a conductive layer formed on the region via a gate insulating film and a gate electrode connected to the field plate are provided, and the field plate includes an oxide film having a film thickness substantially the same as that of the gate insulating film. since consisting extends to above the semiconductor layer interposed between the well region and the drain region Te, can be increased breakdown voltage between the drain and the source by providing a full I over field plate Of course, since the field plate is extended through the oxide film having almost the same thickness as the gate insulating film, it is extended to a field oxide film which is thicker than the gate insulating film as in the conventional case. The gate-drain capacitance can be reduced as compared with the case where it is present, and as a result, it is possible to reduce the capacitance while maintaining the drain-source breakdown voltage.

Moreover , a withstand voltage of 30V to 200V is ensured.
So that the extension distance of the field plate extended above the semiconductor layer and the drift region distance between the well region and the drain region are 0 <extension distance <drift region distance−0. 0.5 μm and 0.5 μm <drift region distance <10 μm,
The product of the impurity concentration of the semiconductor layer and the thickness of the semiconductor layer is 6 ×
Since it is 10 ¹¹ cm ^{−2 to} 4 × 10 ¹² cm ⁻² , it is possible to secure a drain-source breakdown voltage of 30 V to 200 V.

[0013] In addition, 0.03μm the Thickness of the gate oxide film
To 0.1 μm between the gate and drain
Since the capacitance between the gate and the source is reduced, it is not necessary to change the thickness of the gate oxide film from before, and the capacitance between the gate and drain can be changed without changing the process for adjusting the threshold value. The gate-source capacitance can be reduced. According to the invention of claim 2, in the invention of claim 1, since the thickness of the insulating layer is 1 μm to 4 μm, the insulating layer of a so-called SOI wafer including the semiconductor supporting substrate, the insulating layer and the semiconductor layer is provided in the manufacturing process. It is possible to reduce the warp caused by such a phenomenon, and it is possible to reduce the capacitance between the drain and the semiconductor supporting substrate without the process restriction caused by the warp of the SOI wafer.

According to a third aspect of the present invention, in the first aspect of the present invention, since the thickness of the semiconductor layer is 0.2 μm to 5 μm, the well region and the semiconductor layer can be formed without increasing the process time required for forming the well region. The capacitance due to the pn junction can be reduced. According to a fourth aspect of the invention, in the first aspect of the invention, the insulating layer is made of a material having a lower dielectric constant and a higher thermal conductivity than SiO ₂ , so that the capacitance between the drain and the semiconductor supporting substrate is reduced. You can Further, the heat generated in the semiconductor layer due to the on-resistance and the drain current can be efficiently dissipated to the semiconductor supporting substrate side, and the heat generation can be suppressed, so that the thermal destruction can be prevented.

According to a fifth aspect of the invention, in the first aspect of the invention, the semiconductor layer is formed of a semiconductor material having a bandgap wider than Si, so that the on-resistance is low and the drain-source breakdown voltage is large. In addition, the heat generated in the semiconductor layer can be efficiently released to the semiconductor supporting substrate side, and the heat generation can be suppressed, so that the thermal destruction can be prevented.

[0016]

1 is a sectional view of a dielectric isolation type semiconductor device of this embodiment. The dielectric isolation type semiconductor device shown in FIG. 1 is an n-channel SOI-LDMOSFET, and since its basic structure is substantially the same as the conventional structure, the same components are designated by the same reference numerals and description thereof will be omitted.

In this embodiment, the field plate 12
Then, the structure of the gate electrode 6 is different from the conventional structure. That is, in this embodiment, the field plate 12 short-circuited with the gate electrode 6 is formed into the gate oxide film 5 (gate insulating film).
And is provided only on the oxide thin film 5 ′ having substantially the same thickness as the gate oxide film 5, and the distance between the extension 12 b of the field plate 12 and the n-type semiconductor layer 1 is substantially equal to the thickness of the gate oxide film 5. Equal points differ. Here, the gate oxide film 5 and the oxide thin film 5 ′ can be simultaneously formed.

FIG. 2 shows the impurity concentration of the n-type semiconductor layer 1 and n.
The product Dose with the thickness of the semiconductor layer 1 is 1 × 10 ¹² cm ^-2
The relationship between the drain-source breakdown voltage and the output capacitance Coss described in the conventional example is shown, where the horizontal axis represents the breakdown voltage and the vertical axis represents the output capacitance Coss. Further, the solid line a in FIG. 2 indicates the n-channel SOI- of the present embodiment shown in FIG.
The output capacitance of the LDMOSFET is the conventional n
The output capacitance of the channel SOI-LDMOSFET,
The output capacitance is shown as a relative value between this embodiment and the conventional example. In this embodiment, since the field plate 12 is extended only on the oxide thin film 5 ′, the gate-drain capacitance Cgd is reduced as compared with the conventional case, and when compared with the same breakdown voltage, the output capacitance Coss compared with the conventional case. Is reduced.

FIG. 3 is based on the structure shown in FIG. 1 and the product Dose of the impurity concentration of the n-type semiconductor layer 1 which is the drift region and the thickness of the n-type semiconductor layer 1 is constant at 1 × 10 ¹² cm ⁻² , The extension distance Lover of the field plate 12 onto the n-type semiconductor layer 1 is variously changed to change the drift region distance Ld.
The result of examining the relationship between (drift distance Ld) and breakdown voltage is shown. Here, a in FIG. 3 is Lover = 0 μm, and b is Lover.
= Ld, C is Lover = Ld −0.5 μm, D is Lover =
Ld −1 μm, E for Lover = Ld −2 μm, F for Lover
= Ld -4 μm, G is Lover = Ld -6 μm, J is Lov
The case where er = Ld-8 μm is shown.

FIG. 4 shows the results of examining the relationship between the product Dose and the breakdown voltage by changing the extension distance Lover and the drift region distance Ld. A, R, and C in FIG. 4 are L
When over = Ld, Ld is 0.5 μm, 1 μm, 2 μm
It is when changing to. In addition, for D, E, and F in FIG. 4, Ld is 0.5 μm with Lover = Ld −0.5 μm.
m, 1 μm, 2 μm.

From the results of FIGS. 3 and 4, the extension distance Lover of the field plate 12 onto the n-type semiconductor layer 1 (drift region), the p-type well region 4 and the n ⁺ -type drain region 2 are shown.
If the relation between the drift region distance Ld between the and D, and the product Dose of the impurity concentration of the n-type semiconductor layer 1 and the thickness of the n-type semiconductor layer 1 satisfies the following relation, the 30 required when applying a separated semiconductor device
It is possible to secure a withstand voltage of about V to 200V. 0 <Lover <Ld −0.5 μm 0.5 μm <Ld <10 μm 6 × 10 ¹¹ cm ⁻² <Dose <4 × 10 ¹² cm ^{−2 Further} , the thickness Tgate of the gate oxide film 5 is 0.03 μm to 1
The gate applied voltage of 10 V
Depending on the degree, the gate-drain capacitance C described in the conventional example can be prevented without deteriorating the quality of the gate oxide film 5 and changing the process such as threshold adjustment.
The gd and the gate-source capacitance Cgs can also be reduced.

By setting the thickness Tbox of the insulating layer 11 made of a buried oxide film (SiO ₂ ) to 1 μm to 4 μm, an SOI wafer can be easily manufactured,
Further, since the warp of the SOI wafer can be reduced, the drain-substrate capacitance Cdsub described in the conventional example can be reduced without the difficulty of the process due to the warp of the SOI wafer.

By setting the thickness Tsoi of the n-type semiconductor layer 1 (drift region) to 0.2 μm to 5 μm,
The drain-source capacitance Cds can also be reduced without significantly increasing the process time required for forming the p-type well region 4 from the conventional case. Further, as the insulating layer 11, AlN (aluminum nitride) is used instead of SiO _2.
Alternatively, if it is formed of a material having a lower dielectric constant and higher thermal conductivity than SiO ₂ other than AlN, the drain-substrate capacitance Cdsub can be reduced, and the n-type semiconductor layer 1 (drift region can be formed by the on-resistance and drain current). The heat generated in () can be efficiently released to the semiconductor supporting substrate 10 side to suppress heat generation, and thermal destruction can be prevented.

The n-type semiconductor layer 1 (drift region)
Is formed of SiC having higher mobility, higher thermal conductivity, and higher electric field strength than Si, or a material having similar characteristics and a wider band gap than Si,
The on-resistance becomes low, the breakdown voltage becomes high, and the heat generated in the n-type semiconductor layer 1 (drift region) can be efficiently released to the semiconductor supporting substrate 10 side to suppress the heat generation and prevent thermal destruction. be able to.

[0025]

According to the invention of claim 1, in the semiconductor layer of the first conductivity type formed on the semiconductor supporting substrate via the insulating layer,
A source region of the first conductivity type and a drain region of the second conductivity type are formed apart from each other, and a well region of the second conductivity type is formed so as to surround the source region, and between the source region and the drain region. A field plate including a conductive layer formed on the intervening well region via a gate insulating film and a gate electrode connected to the field plate are provided, and the field plate is an oxide film having substantially the same thickness as the gate insulating film. Since it extends above the semiconductor layer that is interposed between the well region and the drain region through the film, it is of course possible to increase the breakdown voltage between the drain and source by providing the field plate. Since the field plate is extended through the oxide film having almost the same film thickness as the gate insulating film, the film thickness of the film is larger than that of the gate insulating film as in the past. It is possible to reduce the gate-drain capacitance compared to the case where it is extended over the field oxide film, and as a result, it is possible to reduce the capacitance while maintaining the drain-source breakdown voltage. effective.

Moreover , a withstand voltage of 30V to 200V is ensured.
So that the capacitance between the gate and the drain can be reduced, the extension distance of the field plate extending above the semiconductor layer and the drift region distance between the well region and the drain region are , 0 <extension distance <drift region distance-0.5 μm and 0.5 μm <drift region distance <10 μm, and the product of the impurity concentration of the semiconductor layer and the thickness of the semiconductor layer is 6 ×. 10 ¹¹ c
Since m ^{−2 to} 4 × 10 ¹² cm ⁻² , 30 V to
There is an effect that it becomes possible to secure a drain-source breakdown voltage of 200V .

[0027] In addition, 0.03μm the Thickness of the gate oxide film
To 0.1 μm between the gate and drain
Since the capacitance between the gate and the source is reduced, it is not necessary to change the thickness of the gate oxide film from before, and the capacitance between the gate and drain can be changed without changing the process for adjusting the threshold value. There is an effect that the capacitance between the gate and the source can be reduced.

According to a second aspect of the present invention, in the first aspect of the present invention, since the thickness of the insulating layer is 1 μm to 4 μm, the insulating layer of a so-called SOI wafer constituted by the semiconductor supporting substrate, the insulating layer and the semiconductor layer in the manufacturing process. It is possible to reduce the warp due to the provision of the structure, and it is possible to reduce the capacitance between the drain and the semiconductor supporting substrate without the process restriction due to the warp of the SOI wafer.

According to a third aspect of the present invention, in the first aspect of the present invention, the thickness of the semiconductor layer is 0.2 μm to 5 μm. Therefore, the well region and the semiconductor layer can be formed without increasing the process time required for forming the well region. There is an effect that the capacitance due to the pn junction can be reduced. Claim
According to a fourth aspect of the invention, in the first aspect of the invention, the insulating layer is Si.
Since it is made of a material having a lower dielectric constant and a higher thermal conductivity than O _2, the capacitance between the drain and the semiconductor supporting substrate can be reduced. Further, the heat generated in the semiconductor layer due to the on-resistance and the drain current can be efficiently dissipated to the semiconductor supporting substrate side, and the heat generation can be suppressed, so that the thermal destruction can be prevented.

According to a fifth aspect of the invention, in the first aspect of the invention, the semiconductor layer is formed of a semiconductor material having a bandgap wider than Si, so that the on-resistance is low and the drain-source breakdown voltage is large. In addition, the heat generated in the semiconductor layer can be efficiently dissipated to the semiconductor supporting substrate side, and the heat generation can be suppressed, so that the thermal destruction can be prevented.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing an embodiment.

FIG. 2 is a graph showing a relationship between breakdown voltage and output capacitance in the same.

FIG. 3 is a graph showing the relationship between the drift region distance and the breakdown voltage of the above.

FIG. 4 is a graph showing the relationship between the product Dose and the breakdown voltage of the above.

FIG. 5 is a cross-sectional view showing a conventional example.

FIG. 6 is an explanatory diagram of a parasitic capacitance of the above.

FIG. 7 is an explanatory diagram of a parasitic capacitance of the above.

[Explanation of symbols]

1 n-type semiconductor layer 2 n ^{+ type} drain region 3 n ^{+ type} source region 4 p type well region 5 gate oxide film 5 ′ oxide thin film 7 drain electrode 8 source electrode 10 semiconductor supporting substrate 11 insulating layer 12 field plate 12b extension part 13 Insulating film

─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yoshifumi Shirai, 1048, Kadoma, Kadoma, Osaka Prefecture Matsushita Electric Works, Ltd. (72) Takashi Kishida, 1048, Kadoma, Kadoma, Osaka Prefecture, Matsushita Electric Works, Ltd. (72) Inventor ▲ Takano Jinji 1048, Kadoma, Kadoma, Osaka Prefecture, Matsushita Electric Works, Ltd. (72) Inventor, Takeshi Yoshida, 1048, Kadoma, Kadoma, Osaka Prefecture, Matsushita Electric Works, Ltd. (56) Reference: Japanese Patent Laid-Open No. 9 -64371 (JP, A) JP 7-183522 (JP, A) JP 9-121057 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 29/78 H01L 29/786 H01L 21/336

Claims (5)

(57) [Claims] 1. A source region of the first conductivity type and a drain region of the second conductivity type are formed separately in a semiconductor layer of the first conductivity type formed on a semiconductor supporting substrate via an insulating layer. In addition, a well region of the second conductivity type is formed surrounding the source region, and a field plate made of a conductive layer formed on the well region interposed between the source region and the drain region via a gate insulating film. And a gate electrode connected to the field plate, in the dielectric isolation type semiconductor device, the field plate is interposed between the well region and the drain region via an oxide film having substantially the same thickness as the gate oxide film. to be extended to above the semiconductor layer, 30
The extension distance of the field plate extended above the semiconductor layer and the drift region distance between the well region and the drain region are 0 <extension so that a breakdown voltage of V to 200 V can be ensured. Distance <Drift region distance-0.5μ
m and 0.5 μm <drift region distance <10 μm, and the product of the impurity concentration of the semiconductor layer and the thickness of the semiconductor layer is 6 × 10 ¹¹ cm ^{−2 to} 4 ×.
10 ¹² cm ^−2, and the thickness of the gate oxide film is 0.03.
Gate / drain by setting to μm to 0.1 μm
A dielectric isolation type semiconductor device characterized in that the capacitance between the gate and the source is reduced . 2. The dielectric isolation type semiconductor device according to claim 1, wherein the insulating layer has a thickness of 1 μm to 4 μm . 3. The semiconductor layer has a thickness of 0.2 μm to 5 μm.
2. The dielectric isolation type semiconductor device according to claim 1, wherein 4. The insulating layer has a dielectric constant lower than that of SiO ₂ and
2. The dielectric isolation type semiconductor device according to claim 1, which is formed of a material having a high thermal conductivity . 5. The semiconductor layer has a band gap wider than that of Si.
2. The dielectric isolation type semiconductor device according to claim 1, wherein the dielectric isolation type semiconductor device is formed of a semiconductor material having a cap .