JP2000164876A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device, together with its manufacturing method, which contributes to a reduced output capacitance Coss through a reduced Cdsub(drain-substrate capacitance). SOLUTION: A p-type well region 4 and an n+-type drain region 5 are formed with a space inbetween, in an n-type semiconductor layer 3 of an SOI(silicon-on- insulator) substrate, with an n+-type source region 6 formed in the p-type well region 4, A drain electrode 8 is so formed as to be electrically connected to the n+-type drain region 5, a source electrode 9 is so formed as to be electrically connected to the p-type well region 4 and n+-type source region 6, and a gate electrode 11 of polysilicon comprising conductivity is formed through a gate oxide film 10 on a p-type well region 4 of the n-type semiconductor layer 3, which is between the n+-type drain region 5 and n+-type source region 6. The n-type semiconductor layer 3 constitutes a drift region. Here, a p-type impurity region 12 is formed in the drift region in the n-type semiconductor layer 3 near the interface between the n-type semiconductor layer 3 and an insulating layer 2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method for manufacturing the same.

[0002]

2. Description of the Related Art In recent years, a lateral double-diffused MOS field effect using a so-called SOI (Silicon On Insulator) substrate in which a single-crystal silicon layer is provided on a single-crystal silicon substrate via an insulating layer made of a silicon oxide film. Transistor, so-called LDM
OSFETs (Lateral Double Diffused MOSFETs) are attracting attention because of their excellent characteristics of low output-to-output capacitance.

FIG. 6 shows an example of a conventional L-type SOI substrate using an SOI substrate.
FIG. 3 is a schematic sectional view showing a DMOSFET. This LDMOSFET has n
An n-type semiconductor layer 3, which is a first conductivity type semiconductor layer such as an n-type silicon layer, is formed on a semiconductor substrate 1 such as a silicon substrate of a p-type or a p-type via an insulating layer 2 such as a silicon oxide film.
Constructs an I-board.

A p-type well region 4 as a second conductivity type well region and an n + type drain region 5 as a high-concentration first conductivity type drain region are formed in the n-type semiconductor layer 3 so as to be separated from each other. An n + type source region 6 which is a high concentration first conductivity type source region is formed in the p type well region 4. At this time, the p-type well region 4 is formed to a depth reaching the insulating layer 2, and a p + -type body contact region 7, which is a high-concentration second conductivity type body contact region, is formed in the p-type well region 4. Have been.

A drain electrode 8 is formed so as to be electrically connected to n + type drain region 5, and a source electrode 9 is formed so as to be electrically connected to p type well region 4 and n + type source region 6. Formed on the surface of the n-type semiconductor layer 3,
On the p-type well region 4 interposed between the n + -type drain region 5 and the n + -type source region 6, a gate electrode 1 made of conductive polysilicon is interposed via a gate oxide film 10.
1 is formed. Here, the n-type semiconductor layer 3 forms a drift region.

FIG. 7 is a schematic sectional view showing a vertical MOSFET according to a conventional example. In this vertical MOSFET, an n + -type drain region 5 is formed on two main surfaces of a semiconductor substrate 1, a p-type well region 4 is formed on one main surface, and an n + -type source region is included in the p-type well region 4. Region 6 is formed.

A drain electrode 8 is formed so as to be electrically connected to n + type drain region 5, and a source electrode 9 is formed so as to be electrically connected to p type well region 4 and n + type source region 6. Formed on one main surface of the semiconductor substrate 1 and on the p-type well region 4 interposed between the n + -type source region 6 and the semiconductor substrate 1, conductive polysilicon is interposed via a gate oxide film 10. Is formed. Here, the SOI structure type LDMOS shown in FIG.
The FET operates similarly to the vertical MOSFET shown in FIG.

The parasitic capacitance of the SOI structure type LDMOSFET is shown in FIG.
As shown in the figure, the gate-drain capacitance Cgd,
There are a source-to-source capacitance Cgs, a drain-to-source capacitance Cds, and a drain-to-substrate capacitance Cdsub. The parasitic capacitance of the vertical MOSFET is, as shown in FIG.
Gate-source capacitance Cgs, drain-source capacitance Cds
There is.

The output dose Coss of the vertical MOSFET is expressed by Coss
= Cds + Cgd, and the output dose Cos of the SOI structure type LDMOSFET
s is Coss = Cds + Cgd + Cdsub.

Here, Cgd is the gate oxide film capacitance,
The normal vertical MOSFET and the SOI structure type LDMOSFET are at the same level. Cds is the junction capacitance of the p-type region, and the SOI structure in which the size of the side area of the p-type well region 4 on the n + -type drain region 5 side is limited by the presence of the insulating layer 2 is as follows:
Cds is significantly lower than that of a normal vertical MOSFET.

[0011] Therefore, the SOI structure type LDMOSFET has attracted attention because its output capacitance Coss is reduced and the device is excellent in high-speed operation and low power consumption.

[0012]

[0006] However, FIG.
The SOI structure type LDMOSFET has a Cdsub component that does not exist in the vertical type MOSFET. However, vertical MOSFET
When compared with Cds, the new addition of Cdsub is extremely small compared to the reduction of Cds. Therefore, when comparing the output capacities Coss of both, the new addition of Cdsub is a value that is so small that it does not matter.

However, in the SOI structure type LDMOSFET, Cdsu
b may account for about half of Coss, and C
The size of dsub cannot be ignored.

The present invention has been made in view of the above points, and an object of the present invention is to provide a semiconductor device which contributes to a reduction in output capacitance Coss through a reduction in Cdsub, and a method of manufacturing the same. Is to do.

[0015]

According to the first aspect of the present invention,
An SOI substrate having a semiconductor substrate and a first conductivity type semiconductor layer formed on the semiconductor substrate via an insulating layer; and the first conductivity type semiconductor layer exposed on the surface of the first conductivity type semiconductor layer. A high-concentration first-conductivity-type drain region formed therein, and the first-conductivity-type drain region so as to be spaced from the high-concentration first-conductivity-type drain region and exposed on the surface of the first-conductivity-type semiconductor layer. A second conductivity type well region formed in the semiconductor layer, and formed in the first conductivity type semiconductor layer so as to be included in the second conductivity type well region and exposed on a surface of the first conductivity type semiconductor layer. High concentration first conductivity type source region, and the second conductivity interposed between the high concentration first conductivity type drain region and the high concentration first conductivity type source region on the surface of the first conductivity type semiconductor layer. Via a gate oxide film on the mold well region In a semiconductor device having a made a gate electrode, the insulating layer adjacent the first conductive type semiconductor layer, forming a low-concentration second conductivity-type impurity regions,
The low-concentration second-conductivity-type impurity region and the second-conductivity-type impurity region are arranged so that a depletion layer generated by the low-concentration second-conductivity-type impurity region does not contact a depletion layer generated by the second-conductivity-type well region. It is characterized by being formed apart from the well region.

According to a second aspect of the present invention, in the semiconductor device according to the first aspect, the low-concentration second conductivity type impurity region has an impurity concentration of 7.5 × 10 ¹⁵ cm ⁻³ or less. It is.

According to a third aspect of the present invention, in the semiconductor device according to the first or second aspect, the insulating layer includes:
It is characterized by using a material having a lower dielectric constant and a higher thermal conductivity than a silicon oxide film.

According to a fourth aspect of the present invention, in the semiconductor device according to any one of the first to third aspects, silicon is used as the first conductivity type semiconductor layer, and the thickness of the silicon is 2 μm or less. It is characterized by the following.

According to a fifth aspect of the present invention, in the semiconductor device according to any one of the first to third aspects, a semiconductor material having a band gap larger than that of silicon is used as the first conductivity type semiconductor layer. It is characterized by the following.

According to a sixth aspect of the present invention, in the method of manufacturing a semiconductor device according to any one of the first to fifth aspects, the low-concentration second conductivity type impurity region is formed by the high-concentration first conductivity type impurity region. It is characterized in that it is formed by high-energy ion implantation using the same mask as the mask for forming the mold drain region.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. In the embodiments described below, the first conductivity type is described as n-type, and the second conductivity type is described as p-type. However, even when the first conductivity type is p-type and the second conductivity type is n-type, Applicable.

FIG. 1 shows an SOI according to an embodiment of the present invention.
FIG. 3 is a schematic cross-sectional view showing a structure type LDMOSFET. The LDMOSFET according to the present embodiment is an LDMOSFET shown in FIG.
In the vicinity of the interface between the n-type semiconductor layer 3 and the insulating layer 2,
This is a configuration in which a p − -type impurity region 12 which is a low-concentration second conductivity type impurity region is formed in a drift region in the n-type semiconductor layer 3.

FIG. 2 shows an SOI structure type LDMOSFET according to the above figure.
FIG. 4 is an explanatory diagram showing a depletion layer generated in the embodiment. The depletion layer 13
occurs between the p-type impurity region 12 and the drift region,
The depletion layer 14 is generated between the p-type well region 4 and the drift region.

Here, as shown in FIG.
3 is arranged in series with the parasitic capacitance Cbox of the insulating layer 2, and the drain-substrate capacitance Cd according to the present embodiment.
sub (invention) is Cdsub (invention) = 1 / {(1 / Cp-) + (1 / Cbo
x)}. Drain-substrate capacitance Cds with conventional structure
Since ub (conventional) is Cdsub (conventional) = 1 / (1 / Cbox), Cdsub (invention) <Cdsub (conventional) holds.

Therefore, by newly providing the p-type impurity region 12, the capacitance between the drain and the substrate can be reduced.

Here, in order for the above relation to be satisfied,
Care must be taken so that the depletion layer 13 and the depletion layer 14 do not come into contact. If the depletion layer 13 and the depletion layer 14 are in contact with each other and unite, the component Cds constituting the output capacitance Coss is affected.

That is, the drain-source capacitance Cds (conventional) in the conventional structure is smaller than the depletion layer 13 with respect to Cds = Cpwell.
And the depletion layer 14 are integrated, the drain-source capacitance Cds (contact) becomes Cds (contact) = Cpwell + Cp−, and Cds
The ds parasitic capacitance increases. Therefore, it is necessary that the depletion layer 13 and the depletion layer 14 do not come into contact with each other in consideration of the entire output capacitance Coss.

Hereinafter, a manufacturing process of the SOI structure type LDMOSFET according to the present embodiment will be described. FIG.
FIG. 7 is a schematic cross-sectional view showing a part of the manufacturing process of the SOI structure type LDMOSFET according to the present embodiment. SOI according to the present embodiment
The manufacturing process of the structure type LDMOSFET is substantially the same as the manufacturing process of the conventional SOI structure type LDMOSFET. After the p-type impurity region 12 is formed, the n + -type drain region 5 and the n + -type source region are formed. A p-type impurity such as boron (B) is introduced by high-energy ion implantation using the same mask 15 as the mask for forming
Impurities for forming the type drain region 5 and the n + type source region 6 are introduced.

Therefore, in this manufacturing process, the p− type impurity region 12 is formed in the lower region of the n + type drain region 5 using the same mask 15 as the mask for forming the n + type drain region 5 and the n + type source region 6. I decided to
The condition that the depletion layer 13 and the depletion layer 14 do not contact can be satisfied.

Further, since it is only necessary to add only the ion implantation process to the conventional process, it can be manufactured relatively easily.

Here, as shown in the above embodiment,
When the p-type impurity region 12 is formed by the high energy ion implantation method, the implantation position of the p-type impurity is determined by the magnitude of the implantation energy. The upper limit of the implantation energy of the current ion implantation is 1 MeV, and the corresponding implantation position is 2 μm.

Therefore, if the SOI film thickness (the film thickness of the n-type semiconductor layer 3) is larger than 2 μm, the p− type impurity region 12
Is formed at a position that does not reach the insulating layer 2 as shown in FIG.

Comparing the case where the p− type impurity region 12 reaches the insulating layer (FIG. 2) and the case where the p− type impurity region 12 does not reach the insulating layer (FIG. 4), FIG. The impurity region 12 forms a kind of MOS structure, and a depletion layer 13 is generated in the p − -type impurity region 12 from the insulating layer 2. The size of the depletion layer 13 is such that the insulating layer 2 is n +
It corresponds to a one-sided step junction when replaced with a type impurity layer.

On the other hand, in FIG. 4, the region of the depletion layer 13 is a step junction of the p − -type impurity region 12 surrounded by the drift region. n + type impurity layer / p− type impurity region 12
Has a larger internal potential than the drift region / p − -type impurity region 12, so that the region of the depletion layer 13 is p
It is larger that the − type impurity region 12 reaches the insulating layer 2.

Therefore, since the depletion layer parasitic capacitance is inversely proportional to the size of the depletion layer region, the parasitic capacitance becomes smaller when the p − -type impurity region 12 reaches the insulating layer 2. That is,
Capacitance Cp when p-type impurity region 12 reaches insulating layer 2
-, And the capacitance Cp- 'when not reached is Cp- <Cp-'.

Therefore, in order to remarkably reduce the capacitance, the SOI film thickness (the film thickness of the n-type semiconductor layer 3) is set to 2 μm or less, and the p − -type impurity region 12 is located at a position reaching the insulating layer 2. It is effective to form.

Further, in order to apply an SOI structure type LDMOSFET to an inverter or the like, it is necessary to set the withstand voltage to a practical level of 30 V or more. According to the electric field relaxation theory known as the RESURF condition, in order to obtain such a withstand voltage, the ion implantation dose for adjusting the concentration of the drift region needs to be 1.5 × 10 ¹² cm ⁻² or more. SOI film thickness 2μm
In the following, the concentration of the drift region becomes (dose amount) /
From (SOI film thickness), (1.5 × 10 ¹² cm ⁻² ) / (2 μm) = 7.5
× 10 ¹⁵ cm ^-3 is required.

When the impurity concentration of p-type impurity region 12 is set higher than the impurity concentration of the drift region (7.5 × 10 ¹⁵ cm ^-3 ), depletion layer 13 is generated outside p-type impurity region 12, If it is set low, it will occur internally.

Depletion layer 13 is provided outside p-type impurity region 12.
When depletion occurs, a depletion layer 13
Does not occur. On the other hand, when the depletion layer 13 is generated inside, the depletion layer 13 is also generated at the portion in contact with the insulating layer 2. Therefore, the depletion layer 13 is generated inside as compared with the case where the depletion layer 13 is generated outside. Since the region of the depletion layer 13 is large, the parasitic capacitance is reduced.

Accordingly, the p-
It is effective that the impurity concentration of the type impurity region 12 is set to 7.5 × 10 ¹⁵ cm ⁻³ or less at which the depletion layer 13 can be generated inside.

In this embodiment, the insulating layer 2
A silicon oxide film was used as the material, but the dielectric constant was lower than aluminum nitride (AlN) or silicon oxide film.
In addition, if a material having a high thermal conductivity is used, the capacitance Cdsub between the drain and the substrate can be reduced, and the heat generated in the drift region due to the on-resistance and the drain current is efficiently released to the semiconductor substrate 1 to generate heat. Can be suppressed, and thermal destruction can be prevented.

The drift region may be formed of SiC having higher mobility, higher thermal conductivity, and higher electric field strength than Si, or a material having similar characteristics and a wider band gap than Si. In this case, the on-resistance is reduced, the withstand voltage is increased, and the heat generated in the drift region can be efficiently released to the semiconductor substrate 1 side to suppress heat generation, thereby preventing thermal destruction.

[0043]

According to a first aspect of the present invention, there is provided an SOI substrate having a semiconductor substrate and a first conductivity type semiconductor layer formed on the semiconductor substrate via an insulating layer; A high-concentration first-conductivity-type drain region formed in the first-conductivity-type semiconductor layer so as to be exposed on the surface; A second conductivity type well region formed in the first conductivity type semiconductor layer so as to be exposed on the surface of the layer; and a second conductivity type well region included in the second conductivity type well region and exposed on the surface of the first conductivity type semiconductor layer. A high-concentration first-conductivity-type source region formed in the first-conductivity-type semiconductor layer, a high-concentration first-conductivity-type drain region on the surface of the first-conductivity-type semiconductor layer, and the high-concentration first conductivity type. The second conductive material interposed between the mold source region A semiconductor device having a gate electrode formed on a well region via a gate oxide film, wherein a low-concentration second conductivity type impurity region is formed near the insulating layer in the first conductivity type semiconductor layer; The low-concentration second-conductivity-type impurity region and the second-conductivity-type well are formed so that a depletion layer generated by the low-concentration second-conductivity-type impurity region does not contact a depletion layer generated by the second-conductivity-type well region. Since the region is formed apart from the region, the depletion layer capacitance caused by the low-concentration second conductivity type impurity region is connected in series to the capacitance caused by the insulating layer, and the output capacitance Coss is reduced through the reduction of Cdsub. A semiconductor device which contributes to reduction of the semiconductor device can be provided.

According to a second aspect of the present invention, in the semiconductor device of the first aspect, the impurity concentration of the low concentration second conductivity type impurity region is set to 7.5 × 10 ¹⁵ cm ⁻³ or less. In addition to the effect of the invention, a depletion layer can be formed inside the low-concentration second conductivity type impurity region, and the capacitance can be efficiently reduced.

According to a third aspect of the present invention, in the semiconductor device according to the first or second aspect, as the insulating layer,
Since a material having a lower dielectric constant and a higher thermal conductivity than the silicon oxide film is used, the drain-substrate capacitance Cdsub can be reduced in addition to the effects of the invention described in claim 1 or 2. In addition, heat generated in the first conductivity type semiconductor layer due to the ON resistance and the drain current can be efficiently released to the semiconductor substrate side, and thermal destruction can be prevented.

According to a fourth aspect of the present invention, in the semiconductor device according to any one of the first to third aspects, silicon is used as the first conductivity type semiconductor layer, and the thickness of the silicon is set to 2 μm or less. In addition to the effects of the invention according to any one of claims 1 to 3, a depletion layer can be efficiently formed.

According to a fifth aspect of the present invention, in the semiconductor device according to any one of the first to third aspects, a semiconductor material having a band gap larger than that of silicon is used for the first conductive semiconductor layer. In addition to the effects of the invention according to any one of claims 1 to 3, the on-resistance is low, the withstand voltage between the drain and the source is high, and the on-resistance and the drain current cause the first conductive type semiconductor layer to be formed. The generated heat can be efficiently released to the semiconductor substrate side, and thermal destruction can be prevented.

According to a sixth aspect of the present invention, in the method for manufacturing a semiconductor device according to any one of the first to fifth aspects, the low-concentration second conductivity type impurity region is formed by the high-concentration first conductivity type impurity region. Since it is formed by high energy ion implantation using the same mask as the mask for forming the drain region, in addition to the effect of the invention according to any one of claims 1 to 5, the conventional process It is sufficient to add only the ion implantation step, and it is possible to provide a method of manufacturing a semiconductor device that contributes to reduction of the output capacitance Coss through reduction of Cdsub.

[Brief description of the drawings]

FIG. 1 shows an SOI structure type LDMOS according to an embodiment of the present invention.
FIG. 3 is a schematic cross-sectional view showing a FET.

FIG. 2 is an explanatory diagram showing a depletion layer generated in the SOI structure type LDMOSFET according to the upper diagram.

FIG. 3 is a schematic cross-sectional view showing a part of the manufacturing process of the SOI structure type LDMOSFET according to the present embodiment.

FIG. 4 is an SOI structure type LDM according to another embodiment of the present invention.
FIG. 3 is a schematic sectional view showing an OSFET.

FIG. 5 is an explanatory diagram showing a depletion layer generated in the SOI structure type LDMOSFET according to the upper diagram.

FIG. 6 is a schematic sectional view showing an LDMOSFET using a SOI substrate according to a conventional example.

FIG. 7 is a schematic sectional view showing a vertical MOSFET according to a conventional example.

FIG. 8 is an explanatory diagram showing a parasitic capacitance of an LDMOSFET using a SOI substrate according to a conventional example.

[Explanation of symbols]

 Reference Signs List 1 semiconductor substrate 2 insulating layer 3 n-type semiconductor layer 4 p-type well region 5 n + -type drain region 6 n + -type source region 7 P + -type body contact region 8 drain electrode 9 source electrode 10 gate oxide film 11 gate electrode 12 p-type impurity Regions 13, 14 Depletion layer 15 Mask

────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] January 29, 1999 (1999.1.2
9)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0009

[Correction method] Change

[Correction contents]

[0009] In addition, the output capacitance Coss of the vertical MOSFET, Coss
= A Cds + Cgd, the output capacity of the LDMOSFET of SOI structure type Cos
s is Coss = Cds + Cgd + Cdsub.

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0039

[Correction method] Change

[Correction contents]

Depletion layer 13 is provided outside p-type impurity region 12.
When depletion occurs, a depletion layer 13
Does not occur. On the other hand, when the depletion layer 13 is generated inside, the depletion layer 13 is also generated at the portion in contact with the insulating layer 2. Therefore, the depletion layer 13 is generated inside as compared with the case where the depletion layer 13 is generated outside. because the region of the depletion layer 13 is large, the parasitic capacitance is reduced.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification code FI Theme coat ゛ (Reference) H01L 29/78 623Z (72) Inventor Yuji Suzuki 1048 Ojidoma, Kazuma-shi, Osaka Matsushita Electric Works Co., Ltd. ( 72) Inventor Yoshiki Hayasaki 1048 Kadoma Kadoma, Kadoma City, Osaka Prefecture Inside the Matsushita Electric Works, Ltd. (72) Inventor Takashi Kishida 1048 Kadoma Kadoma, Kadoma City, Osaka Prefecture Inside the Matsushita Electric Works Co., Ltd. (72) Inventor Hitoshi Takano Matsushita Electric Works Co., Ltd., 1048, Kazuma, Kadoma, Osaka (72) Inventor Takeshi Yoshida F-term (reference) 510, DA12 DA22 DA22 DC01 DC02 EB01 EB12 5F110 AA02 BB12 CC02 DD05 DD13 EE09 FF02 GG02 GG12 GG52 HJ13 HM12 HM14

Claims (6)

[Claims] An SOI substrate having a semiconductor substrate and a first conductivity type semiconductor layer formed on the semiconductor substrate with an insulating layer interposed therebetween; and an SOI substrate having a first conductivity type semiconductor layer exposed on a surface of the first conductivity type semiconductor layer. A high-concentration first-conductivity-type drain region formed in the one-conductivity-type semiconductor layer, and surrounds the high-concentration first-conductivity-type drain region so as to be exposed on the surface of the first-conductivity-type semiconductor layer. A second conductivity type well region formed in the first conductivity type semiconductor layer, and the first conductivity type included in the second conductivity type well region and exposed on a surface of the first conductivity type semiconductor layer. A high-concentration first-conductivity-type source region formed in a semiconductor layer, and interposed between the high-concentration first-conductivity-type drain region and the high-concentration first-conductivity-type source region on the surface of the first-conductivity-type semiconductor layer; A gate acid on the second conductivity type well region A low concentration second conductivity type impurity region in the first conductivity type semiconductor layer near the insulating layer, wherein the low concentration second conductivity type impurity region is formed in the first conductivity type semiconductor layer in the vicinity of the insulating layer. The low-concentration second-conductivity-type impurity region and the second-conductivity-type well region are separated from each other so that the depletion layer generated by the-type impurity region does not contact the depletion layer generated by the second-conductivity-type well region. A semiconductor device characterized by being formed by: Wherein said low concentration impurity concentration of the second conductivity type impurity region, the semiconductor device according to claim 1, characterized in that a 7.5 × 10 ^{1 5} cm ^-3 or less. 3. The semiconductor device according to claim 1, wherein a material having a lower dielectric constant and a higher thermal conductivity than a silicon oxide film is used as said insulating layer. 4. The semiconductor device according to claim 1, wherein silicon is used as the first conductivity type semiconductor layer, and the thickness of the silicon is 2 μm or less. 5. The semiconductor device according to claim 1, wherein a semiconductor material having a larger band gap than silicon is used for the first conductivity type semiconductor layer. 6. The method for manufacturing a semiconductor device according to claim 1, wherein said low-concentration second conductivity type impurity region is formed as a mask for forming said high-concentration first conductivity type drain region. A method for manufacturing a semiconductor device, characterized in that it is formed by high-energy ion implantation using the same mask as in (1).