JP3420168B2 - Field effect transistor and integrated logic circuit using the same - Google Patents

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a field effect transistor and an integrated circuit using the same.

[0002]

2. Description of the Related Art Si, which is the core of current semiconductor devices
-MOSFETs (Metal-Oxide-Semiconductor field effect transistors) have achieved high density integration and increased driving power at the same time by miniaturization of device dimensions, especially reduction of gate length.
However, in the near future, it has been pointed out that miniaturization of devices according to the conventional trend will hit physical and economic barriers. Therefore, in the future, speeding up by methods other than miniaturization,
It is necessary to establish technology for low power consumption. One of the most promising such technologies is a MOSFET with tensile strained Si as a channel. FIG. 9A is a sectional view of such tensile strained Si-MOSFET. This tensile strain Si-MO
The SFET includes a Si substrate 1, a buffer layer 2 made of SiGe formed on the Si substrate, and lattice-relaxed SiGe formed on the buffer layer 2.
The layer 3, the tensile strained Si layer 15 formed thereon, and the gate electrode 6 formed thereon via the gate insulating film 5.
And a source 7 and a drain 8. SiGe
Since the layer 3 is formed sufficiently thick so as to relax the lattice, if the thickness of the Si layer 15 epitaxially grown on the layer 3 is made as thin as about 20 nm, the crystal lattice of the Si layer 15 does not relax and the in-plane surface of the substrate is not relaxed. It has tensile strain in the direction. Therefore, the Si layer 15 is in a state where the lattice constant in the in-plane direction of the Si substrate 1 is larger than the lattice constant in the vertical direction of the Si substrate 1. Due to the asymmetry of this crystal lattice, the conduction band valley that was degenerate to sixfold in the unstrained state and the Γ point of the valence band that was degenerate to doubly (state where electron wavenumber is 0) Degeneracy in the neighborhood can be solved.

As a result, the conduction band is double degenerate and 4
In the degenerate state, the valence band is separated into a heavy hole band and a light hole band. Therefore, in tensile strained Si, the scattering probability of phonons in both electrons and holes decreases, and the mobility increases near room temperature. Taking advantage of the property of increasing the mobility of tensile strain Si,
We are aiming to speed up the MOSFET by using it for the channel layer of (J. Welser et al., IEDM Tech. Di.
g., p. 1000, (1992), p. 373 (1994), p. 517
(1995), K. Chinmay et al., Solid-State Elect
ron. p1863 41 (1997)). In the tensile strained Si-MOSFET having the tensile strained Si in the channel, the mobility increase of about 1.7 times that of the Si-MOSFET is observed in the n-channel, which is equivalent to the theoretical prediction. On the other hand, in the p-channel, theoretically an increase of about 2.5 times is expected, whereas in reality, an increase of about 1.4 times at most is observed.

Also, n-channel and p-channel MOSFETs
It is the p-channel device that has a low mobility or driving force per unit gate width that mainly limits the operating speed of the CMOS circuit. In Si-MOSFET, the mobility of p-channel is only about 1/3 of that of n-channel. In order to compensate for the resulting difference in driving force, the gate width of the p-MOSFET is set to n-MOSF.
It needed to be wider than ET. However, in this case, the gate area of the p-channel becomes larger than that of the n-channel, and the time constant of charge / discharge of the gate is increased. Therefore, the difference in mobility between p-channel and n-channel complicates the design of CMOS circuits. Further, when the tensile strained Si-MOSFET is used in the CMOS logic circuit, the driving force is increased in both the n-channel and the p-channel than in the Si-MOSFET, so that the operating speed can be expected to be improved. However, in tensile strained Si-MOSFET, p-type and n-type
Since the difference in mobility between the molds has become wider than in the case of ordinary Si-MOSFET, not only the optimum design of CMOS logic circuit becomes more complicated, but also the effect of improving the mobility of tensile strained Si-MOSFET is obtained. I can't make the most of it.

Even if the hole mobility according to the theoretical value is obtained, the electron mobility is also increased at the same time, so that there is a problem that the mobility difference of about double remains. Further, as another technique for speeding up and lowering power consumption by a method other than miniaturization, there is a technique of using SiGe having compressive strain as a channel. FIG. 9B is a sectional view of a MOSFET having the compressive strain SiGe in the p channel. This compressive strain SiGe-MOSFET
Is a p-channel compressive strained SiGe layer 1 formed on the Si substrate 1.
7, a Si cap layer 18 formed on the Si cap layer 18, a gate electrode 6 formed on the Si cap layer 18 via a gate insulating film 5,
It is formed of a source 7 and a drain 8. This p-channel compressively strained SiGe-MOSFET is based on VP Kesan et al.,
IEDM Tech. Dig., P25 (1991), RJP Land
er et al., Semicond. Sci. Technol. p. 1064
12 (1997). Among these, compressive strain SiG
It has been reported that the mobility of e is larger than that of a strain-free p-channel Si-MOSFET due to the effect of decomposing the valence band and the effect of reducing the effective mass. However,
In the case of n-channel, the effective mass of SiGe in the in-plane direction of the ground state becomes heavier in the case of an n-channel than in the case of an unstrained n-channel Si-MOSFET. Also, since the quadruple degenerate state becomes the ground state, the phonon scattering probability does not decrease so much. Further, the effect of alloy scattering is added, so that the mobility decreases conversely (T. Manku and A. Nathan, IEEE.
Trans. Electron Devices, p. 2082 39 (199
2)).

Therefore, even if the CMOS logic circuit is constructed by using the compressively strained SiGe for the n-channel and the p-channel, there is not much merit to the conventional structure for constructing the CMOS logic circuit by using the Si-MOSFET without distortion.

[0007]

As described above, the tensile strained Si-MOSFET has a smaller hole mobility increase rate than an electron mobility increase rate. Therefore, when these are applied to a CMOS circuit using the n-channel and p-channel, not only the optimum design becomes complicated due to the imbalance of the driving force and the gate capacitance, but also the effect of improving the mobility of tensile strained Si is fully utilized. There is a problem that cannot be done. In addition, compressive strain SiGe-MOSFE
The electron mobility of T is lower than that of unstrained Si-MOSFET. Therefore, when these are applied to a CMOS circuit using the n-channel and p-channel, Si-MOS without distortion
There is a problem that there is no merit to the structure of forming a CMOS circuit using FET. The present invention has been made in order to solve the above problems, and makes the mobility of n-channel and p-channel larger than that of conventional unstrained Si, and makes the mobility well balanced. The purpose is to simplify the optimum design and further improve the operation speed of the CMOS circuit.

[0008]

In order to achieve the above object, the present invention provides a semiconductor substrate, a lattice-relaxed first Si1-yGey layer formed on the semiconductor substrate, and the first Si.
Second Si1-xGex layer (x <y) formed on 1-yGey layer
And a gate insulating film formed on the second Si1-xGex layer, and a gate electrode formed on the gate insulating film. The second Si1-xGex layer has no electrons or holes. Provided is a field-effect transistor having a channel layer which mainly runs and a crystal lattice having tensile strain in the in-plane direction of the semiconductor substrate. The present invention also provides a field effect transistor, characterized in that an insulating film is embedded in the semiconductor substrate or the first Si1-yGey layer. Further, the present invention provides an insulating layer between the semiconductor substrate and the first Si1-yGey layer,
The xGex layer provides a field effect transistor having a Ge composition lower in a region closer to the gate insulating film than in a region distant from the gate insulating film.

The present invention also provides a lattice-relaxed first SiGe.
Layer, a second SiGe layer having a tensile strain formed on the first SiGe layer, a gate insulating film formed on the second SiGe layer, and a gate formed on the gate insulating film A field effect transistor comprising: an electrode. The present invention also provides the field effect transistor, wherein the second SiGe layer has a Ge composition lower in a region near the gate insulating film than in a region far from the gate insulating film. The present invention also provides a field effect transistor, wherein the Ge composition in the interface region between the gate insulating film and the second SiGe is 1% or less. In addition, the present invention provides a structure in which the interface between the gate insulating film interface of the second SiGe layer is 10
Provided is a field effect transistor characterized in that a region having a Ge composition of 10% or more exists in a region within nm.
Further, according to the present invention, in an integrated logic circuit configured by combining p-channel and n-channel field effect transistors, the p-channel and n-channel or p-channel field effect transistors are the field effect transistors. An integrated logic circuit is provided.

The present invention is characterized in that a tensile strained SiGe layer is used in a region (channel region) where electrons or holes mainly travel. This tensile strained SiGe channel layer is more
It can be obtained by epitaxial growth on the SiGe buffer layer having a large Ge composition to a thickness not more than the critical film thickness. Alternatively, it can be obtained also by a structure epitaxially grown so that the Ge composition continuously or stepwise decreases from the buffer layer to the channel region.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings. SiGe with tensile strain
Degenerates the degeneracy at the Γ point of the valence band and separates into a light hole band and a heavy hole band. As a result, the probability of phonon interband scattering decreases. This effect increases as the tensile strain introduced increases, but it tends to saturate above a certain level. This is because if the energy for separating the light hole band and the heavy hole band becomes sufficiently larger than the energy of the optical phonon (LO-phonon), the scattering probability between the bands becomes negligible. On the other hand, if Ge is mixed in the channel region, the rate of change in energy of holes in each valence band with respect to the wave number increases. This is equivalent to a decrease in the effective mass of holes. Since the mobility is inversely proportional to the effective mass, the mobility is further improved by reducing the effective mass. Figure 7 shows a p-MOSFET using a tensile strained Si channel.
(Solid line) and the calculated value of the mobility increase rate of the p-MOSFET (dashed line) using the tensile strained Si _0.9 Ge _0.1 channel of the present invention are shown with respect to the Ge composition of the buffer layer.

As can be seen from FIG. 7, sufficient buffer layer
In a region having a large Ge composition (for example, Ge is 0.3 or more), that is, in a region where the channel has a sufficient tensile strain, the tensile strain Si _0.9 Ge _{0.1 according} to the present invention is used as a channel layer.
Mobility of SFET p-MOSFET with tensile strained Si as channel layer
Exceeds the mobility of. In the p-MOSFET having tensile strained SiGe as a channel according to the present invention, SiGe has tensile strain in the substrate surface, and the MOS inversion layer is a two-dimensional hole gas. Next, FIG. 1 shows a sectional view of the field effect transistor of the present invention. This field effect transistor is composed of an n-type Si substrate 1, a graded composition n-type SiGe layer 2 formed on the n-type Si substrate and having Ge gradually increasing toward the surface, and a graded composition n-type SiGe layer 2 on the graded composition n-type SiGe layer 2. Formed on the n-type Si _0.6 Ge _0.4 buffer layer 3 and the second SiGe layer formed on the n-type Si _0.6 Ge _0.4 buffer layer 3 n-type Si _0.9 Ge _0.1 A channel layer 4 and a gate oxide film 5 formed on the channel layer 4 (p
⁺ ) Poly-Si gate electrode 6, and a source 7 and a drain 8 formed on both sides of the channel layer 4. An electrode 10 is formed on the source 7 and the drain 8 and an insulating film 9 is formed on the gate electrode. Since SiGe having a Ge composition lower than that of the underlying buffer layer 3 is used for the channel layer 4 of this semiconductor, tensile strain is introduced and the mobility is improved.

Next, a method of forming this semiconductor element will be described. First, a gradient composition n-type SiGe layer 2 having a thickness of 3 μm is formed on the n-type Si substrate 1 by CVD so that the Ge composition gradually increases toward the surface. Then, n-type Si _0.6 Ge is formed on this by CVD.
_{The 0.4} buffer layer 3 is formed to a thickness of 1 μm. Next, an n-type Si _0.9 Ge _0.1 channel layer 4 having a thickness of 15 nm is formed on the buffer layer 3 by CVD. Since the channel layer 4 is formed sufficiently thinner than the buffer layer 3, tensile strain is introduced. Next, the gate oxide film 5 is formed to a thickness of 5 nm by thermal oxidation. Next, a p-type heavy-doped (p ⁺ ) poly-Si gate electrode 6 is formed by CVD. Next, the poly Si gate electrode 6 and the gate oxide film 5 are shaped into a desired shape by etching, B or BF ₂ is ion-implanted on both sides of the gate, and heat treatment is performed to form a source 7 and a drain 8. . Next, a CVD oxide film 9 is deposited by CVD so as to surround the gate electrode 6, and then contact holes are formed on the source 7 and the drain 8. An Al electrode 10 is formed on this contact hole.

In this semiconductor device, the buffer layer 3 is completely
While the lattice relaxation occurs in the channel layer 4,
Subjected to tensile strain in the direction. Negative bias on the gate
Is added, an inversion layer channel of holes is formed just below the gate.
It is formed. The thickness of this inversion layer is at most about 10 nm.
Therefore, the region where the inversion layer exists, that is, the tensile strained SiGe
The distance from the interface of the channel layer with the insulating film 5 is within 10 nm
A region having a Ge composition of 10% or more as a sufficient Ge composition
Is preferably present. Evaluate the mobility of this MOSFET
Then, as shown at point A in Fig. 7, when conventional strained Si is used,
It was about 30% larger than the total. 2 of the present invention
FIG. 6 shows a cross-sectional view of a field effect transistor according to another embodiment.
You Source and drain regions are omitted in FIG. Si group
Gradient of increasing Ge composition on the surface of plate 1
An oblique composition SiGe layer 12 and a buried oxide film 11 (thickness
100 nm) is formed. On top of this the first Si
Undoped Si that is a Ge layer_0.6Ge_0.4Buffer layer 3 (thickness 8
nm) is formed. Tensile strain is introduced on this
Undoped Si which is the second SiGe layer _0.9Ge_0.1Channel layer
4 (thickness 7 nm), gate oxide film 5 (thickness 3 nm),
(P⁺) Poly-Si gate electrode 6 is sequentially laminated.

The buried oxide film is formed in the SiGe buffer layer 3,
Alternatively, implant oxygen ions into a Si substrate,
It is obtained by annealing at a high temperature of ℃ for several hours. Alternatively, the Si substrate on which the thermal oxide film is formed is inverted and attached to another Si substrate or a substrate on which the SiGe buffer layer is formed, and after heat treatment, it is thinned by polishing or etching. In this way SOI (Semiconductor on
Insulator) structure. In this structure, the Si sandwiched between the gate insulating film 5 and the buried oxide film 11 is used.
Since the regions of the Ge buffer layer 3 and the SiGe channel layer 4 are extremely thin, the channel depletion layer extends to the interface of the buried oxide film 11 even in the off state, which is suitable for miniaturization. By doing so, in the structure, the gate length can be reduced to about 50 nm. FIG. 3 shows a sectional view of a field effect transistor according to another embodiment of the present invention. Buried oxide film 11 (thickness 100n on Si substrate 1)
m) is formed. An undoped Si _0.6 Ge layer, which is the first SiGe layer, is formed on top of this layer through a thin undoped Si layer 13.
_{A 0.4} buffer layer 3 (thickness 8 nm) is formed, and an undoped Si _0.9 Ge _0.1 channel layer 4 (thickness 5 nm), which is a second SiGe layer into which tensile strain has been introduced, and a gate oxide film 5 (thickness 5 3 nm), and a (p ⁺ ) poly-Si gate electrode 6 is sequentially laminated.

The buried oxide film is formed in the SiGe buffer layer 3,
Alternatively, implant oxygen ions into a Si substrate,
It is obtained by annealing at a high temperature of ℃ for several hours. Alternatively, the Si substrate on which the thermal oxide film is formed is inverted and attached to another Si substrate or another substrate on which the SiGe buffer layer is formed, and after heat treatment, it is thinned by polishing or etching. In this way SOI (Semiconductor on
Insulator) structure. Also in this structure, since the regions of the Si layer 13, the SiGe buffer layer 3 and the SiGe channel layer 4 sandwiched between the gate insulating film 5 and the buried oxide film 11 are extremely thin, the channel depletion layer is buried and oxidized even in the off state. The structure is suitable for miniaturization because it extends to the interface of the film 11. Even with this structure, the gate length can be reduced to about 50 nm. In this embodiment, since the buried oxide film 11 is formed in the silicon substrate 1,
A thin Si layer 13 remained on the surface. FIG. 4 shows a sectional view of a field effect transistor according to another embodiment of the present invention. Figure 4
In the figure, the left side has no buried oxide film, and the right side has the buried oxide film 11.

Gradient composition buffer layers 2 and 12 whose Ge composition increases toward the surface are formed on a Si substrate 1, and a SiGe buffer layer 3 which is a first SiGe layer is formed thereon. On the right side, a buried oxide film 11 is formed in the SiGe buffer layer 3. Further, on the n-type Si _0.6 Ge _0.4 buffer layer 3, a second SiGe layer SiGe is formed so that the Ge composition decreases continuously or stepwise toward the gate oxide film 5.
The channel layer 14 (thickness 15 nm) is formed. Si
A gate insulating film 5 and a gate electrode 6 are formed on the Ge channel layer 14. In this embodiment, the Si composition of the SiGe channel layer 14 which is the second SiGe layer is lower in the region closer to the gate insulating film 5 than in the region far from the gate insulating film 5. The gradient of the Ge composition of the SiGe channel layer 14 reduces the effective electric field in the inversion layer region and reduces the interface roughness scattering, as shown in FIG. As a result, the effect of further increasing the mobility can be obtained. FIG. 5 shows a sectional view of a field effect transistor according to another embodiment of the present invention. This embodiment has an SOI structure.

On the Si substrate 1, a SiGe buffer layer, which is a first SiGe layer having a graded composition in which the Ge composition increases toward the surface, is formed and oxidized to form a buried insulating film 11. On top of this, an undoped SiGe channel layer 14 which is a second SiGe layer
Are directly formed. The region of the SiGe channel layer 14 on the buried oxide film 11 side is subjected to compressive strain, and the gate oxide film 5 side is subjected to tensile strain. In the above two examples, the Ge composition near the interface with the gate oxide film is substantially zero. This is to avoid an increase in the interface state density due to the presence of Ge at this interface. In order to obtain this effect, the Ge composition in the interface region between the gate insulating film 5 and the SiGe channel layer 14 which is the second SiGe is preferably 1% or less. Although the embodiments for the p-channel MOSFET have been described above, these structures can be directly used for the n-channel MOSFET. In that case, the conductivity type of each layer may be reversed. By thus forming the p-channel and the n-channel on the substrate, a CMOS logic circuit can be constructed.

FIG. 6 shows a CMOS interface according to another embodiment of the present invention.
A sectional view of the inverter is shown. However, the wiring is drawn schematically
I was there. The basic structure of p, -MOSFET and n-MOSFET is shown in the figure.
Although the SOI structure shown in FIG. 5 is used, the structures shown in other examples are
You may use. In addition, mesa etching between each element
The elements are separated by. p-channel gate electrode 6
Is p⁺Poly-Si, n-channel gate electrode 6'is n⁺Poly S
formed by i. Also, p-channel source and drain
In regions 7 and 8 are p ⁺Type, n-channel source, dray
Area 7 ', 8'is n⁺Each type is doped
It The input signal is output to the gate electrodes 6 and 6'of both MOSFETs.
Signal is applied to each of the ohmic electrodes 8, 8 '
It is connected. Ohmic charge on the other side of the p-MOSFET
The positive power supply voltage Vdd (1 to 3 V) is applied to the pole 7, and the remaining n-MOSFET
Each one of the ohmic electrodes 7'is connected to the ground.
Has been done. Adjust the threshold of both MOSFETs on the substrate.
A back gate electrode for forming the back gate electrode is formed. Like this
The CMOS inverter formed by p-channel and n-channel
Well balanced mobility, which facilitates design,
It is possible to increase the speed of the device.

[0020]

According to the present invention, the n-channel and p-channel mobilities are increased and the mobilities of these mobilities are well balanced to simplify the optimum design and further improve the operating speed of the CMOS circuit. Can be further improved. As a result, the driving force balance of both p and n channels is improved, which simplifies the optimum design and further improves the CM.
The operating speed of the OS circuit is improved.

[Brief description of drawings]

FIG. 1 is a sectional view of a MOSFET according to an embodiment of the present invention.

FIG. 2 is a sectional view of a MOSFET according to another embodiment of the present invention.

FIG. 3 is a sectional view of a MOSFET according to another embodiment of the present invention.

FIG. 4 is a sectional view of a MOSFET according to another embodiment of the present invention.

FIG. 5 is a sectional view of a MOSFET according to another embodiment of the present invention.

FIG. 6 is a sectional view of a CMOS inverter circuit according to an embodiment of the present invention.

FIG. 7: Calculation diagram of increase rate of hole mobility of tensile strained SiGe and tensile strained Si

FIG. 8 is a diagram showing a potential of a valence band of a MOSFET according to an example of the present invention.

FIG. 9 is a sectional view of a conventional MOSFET.

[Explanation of symbols]

1 ... Si substrate 2 ... gradient composition SiGe buffer layer 3 ... relaxation SiGe buffer layer 4 ... tensile strain SiGe channel layer 5 ... gate oxide film 6 ... p ⁺ poly Si gate electrode 6 '... n ⁺ poly-Si gate electrode 7 ... p-type diffusion layer 7' ... n-type diffusion layer 8 ... p-type diffusion layer 8 '... n-type diffusion layer 9 ... CVD insulation Film 10 ... Source / drain electrode 11 ... Buried oxide film 12 ... Gradient composition SiGe layer 13 ... Si buffer layer 14 ... Gradient composition SiGe channel layer 15 ... Tensile strain Si channel layer 16 ... Back gate electrode 17 ... Compressed strain SiGe channel layer 18 ... Si cap layer

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁷ Identification code FI H01L 29/786 H01L 29/78 613A 618B 618E (72) Inventor Naoji Sugiyama 1 Komukai Toshiba-cho, Kawasaki-shi, Kanagawa Prefecture Toshiba Research & Development Center (72) Inventor Koji Usuda 1 Komukai Toshiba-cho, Sachi-ku, Kawasaki, Kanagawa Prefecture Toshiba Research & Development Center (72) Inventor Tetsuo Hatakeyama Komukai-Toshiba, Kawasaki-shi, Kanagawa 1 Within Toshiba Research and Development Center (56) Reference JP-A-5-183153 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 29/78

Claims (8)

(57) [Claims] 1. A semiconductor substrate and a lattice-relaxed first Si1− formed on the semiconductor substrate.
yGey layer and a second Si1-xGex layer formed on the first Si1-yGey layer
A layer (x <y), a gate insulating film formed on the second Si1-xGex layer, and a gate electrode formed on the gate insulating film, the second Si1-xGex layer Is a field effect transistor having a channel layer in which electrons or holes mainly travel, and a crystal lattice having tensile strain in the in-plane direction of the semiconductor substrate. 2. The semiconductor substrate or the first Si1-yGe
field effect transistor of claim 1, wherein the insulating film in the y layer is embedded. 3. An insulating layer is provided between the semiconductor substrate and the first Si1-yGey layer, and the second Si1-xGex layer has a Ge composition lower than a region far from a region close to the gate insulating film. The field effect transistor according to claim 1, wherein 4. A lattice-relaxed first SiGe layer, and a second strain having a tensile strain formed on the first SiGe layer.
A SiGe layer, a gate insulating film formed on the second SiGe, and a gate electrode formed on the gate insulating film. 5. The field effect transistor according to claim 4, wherein the second SiGe layer has a Ge composition lower in a region near the gate insulating film than in a region far from the gate insulating film. 6. The Ge composition of the interface region between the gate insulating film and the second SiGe is 1% or less.
The field effect transistor according to 1, 2, 3 or 5 . 7. The method of claim 1, 2, 3, 4, wherein the second of said gate insulating film Ge composition region within 10nm from the interface 10 percent or more regions of the SiGe layer is present
Alternatively, the field effect transistor according to item 6 . 8. An integrated logic circuit configured by combining p-channel and n-channel field effect transistors, wherein p-channel and n-channel or p-channel field effect transistors are provided. Or
7. An integrated logic circuit, which is the field effect transistor according to 7 .