CN115831757B - Method for manufacturing semiconductor structure and semiconductor structure - Google Patents
Method for manufacturing semiconductor structure and semiconductor structure Download PDFInfo
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- CN115831757B CN115831757B CN202310083747.7A CN202310083747A CN115831757B CN 115831757 B CN115831757 B CN 115831757B CN 202310083747 A CN202310083747 A CN 202310083747A CN 115831757 B CN115831757 B CN 115831757B
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Abstract
The application provides a manufacturing method of a semiconductor structure and the semiconductor structure. The method comprises the following steps: providing a substrate, wherein the substrate comprises a substrate, an epitaxial layer and a plurality of field plates which are arranged at intervals; forming a P-type body region in a part of the epitaxial layer at one side of the N-type drift region, and forming a plurality of P-type doped regions in the N-type drift region between any two adjacent field plates; forming a first grid oxide layer on the exposed surfaces of part of the P-type body region, the epitaxial layer between the P-type body region and the N-type drift region and part of the N-type drift region, and forming a plurality of second grid oxide layers on the inner walls of grooves formed by any two adjacent field plates; and forming a gate layer on the surface of the first gate oxide layer far away from the epitaxial layer, the exposed surface of the second gate oxide layer, the surface of the field plates on two sides of the second gate oxide layer far away from the epitaxial layer and the side wall of part of the field plates. The method solves the problem that the power consumption of the device is high due to the fact that high breakdown voltage resistance is achieved in the prior art.
Description
Technical Field
The present disclosure relates to the field of semiconductor technologies, and in particular, to a method for manufacturing a semiconductor structure and a semiconductor structure.
Background
The goal pursued in LDMOS devices is to obtain a high breakdown voltage and a low on-resistance, however, both the breakdown voltage and the on-resistance are strongly limited by the drift region length and the doping concentration, so that there is an inherent contradictory relationship, achieving a high breakdown voltage requires that the drift region for withstanding the breakdown voltage has a long size and a low doping concentration, but in order to satisfy the low on-resistance of the device, the drift region as a current channel is required to have a high doping concentration, the relationship between the breakdown voltage BV (Breakdown Voltage) and the specific on-resistance Ron, sp is Ron, sp oc BV 2.5 Therefore, the saturation current of the device cannot be improved while the breakdown voltage is effectively improved, and the power consumption level of the device is reduced.
Therefore, a method for manufacturing a semiconductor structure with high breakdown voltage and low power consumption is needed.
The above information disclosed in the background section is only for enhancement of understanding of the background art from the technology described herein and, therefore, may contain some information that does not form the prior art that is already known in the country to a person of ordinary skill in the art.
Disclosure of Invention
The main objective of the present application is to provide a method for manufacturing a semiconductor structure and a semiconductor structure, so as to solve the problem that the power consumption of a device is high due to the fact that higher breakdown voltage resistance is achieved in the prior art.
To achieve the above object, according to one aspect of the present application, there is provided a method for manufacturing a semiconductor structure, including: providing a substrate, wherein the substrate comprises a substrate, an epitaxial layer and a plurality of field plates, the epitaxial layer is positioned on the surface of the substrate, the epitaxial layer comprises an N-type drift region, the exposed surface of the N-type drift region is flush with the exposed surface of the epitaxial layer, and the field plates are arranged on the surface, far away from the substrate, of the N-type drift region at intervals; forming a P-type body region in a part of the epitaxial layer at one side of the N-type drift region, and forming a plurality of P-type doped regions in the N-type drift region between any two adjacent field plates; forming a first gate oxide layer on the exposed surface of part of the P-type body region, the exposed surface of the epitaxial layer between the P-type body region and the N-type drift region and the exposed surface of part of the N-type drift region, and forming a plurality of second gate oxide layers on the inner walls of grooves formed by any two adjacent field plates in a one-to-one correspondence manner, wherein the first gate oxide layer is in contact with the adjacent field plates; and forming a gate layer on the surface of the first gate oxide layer far away from the epitaxial layer, the exposed surface of the second gate oxide layer, the surface of the field plate on two sides of the second gate oxide layer far away from the epitaxial layer and part of the side wall of the field plate.
Further, providing a substrate comprising: providing the substrate; forming the epitaxial layer on the exposed surface of the substrate, and performing ion implantation on part of the epitaxial layer to form the N-type drift region; forming a field oxide layer on the epitaxial layer and the exposed surface of the N-type drift region; and removing part of the field oxide layer to expose the epitaxial layer and part of the N-type drift region, and forming a plurality of field plates arranged at intervals on part of the surface of the N-type drift region by the rest of the field oxide layer.
Further, forming a P-type body region in a part of the epitaxial layer at one side of the N-type drift region, and forming a plurality of P-type doped regions in the N-type drift region between any adjacent two field plates, including: forming a mask layer on the exposed surfaces of the epitaxial layer, the N-type drift region and the field plate; patterning the mask layer to expose a part of the epitaxial layer at one side of the N-type drift region and the N-type drift region between any two adjacent field plates; using the patterned mask layer as a mask, and adopting ion implantation to form the P-type body region and a plurality of P-type doped regions; and removing the residual patterned mask layer.
Further, forming a first gate oxide layer on a part of the exposed surface of the P-type body region, on the exposed surface of the epitaxial layer between the P-type body region and the N-type drift region, and on a part of the exposed surface of the N-type drift region, and forming a plurality of second gate oxide layers on the inner walls of the grooves formed by any two adjacent field plates in a one-to-one correspondence manner, wherein the method comprises the following steps: forming an oxide layer on the epitaxial layer, the P-type body region, the N-type drift region, the P-type doped region and the exposed surfaces of the field plates; and removing part of the oxide layer to expose part of the epitaxial layer, part of the P-type body region and the surface of each field plate far away from the epitaxial layer and part of the side wall of each field plate to form the first gate oxide layer and a plurality of second gate oxide layers.
Further, the method further comprises: forming a source region in the P-type body region on one side of the first gate oxide layer; a drain region is formed in the N-type drift region on a side of the field plate remote from the P-type body region.
Further, the method further comprises: a metal silicide layer is formed on a portion of the surface of the gate layer remote from the epitaxial layer, on a surface of the source region remote from the substrate, and on a surface of the drain region remote from the substrate.
Further, the thickness range of the first gate oxide layer and the second gate oxide layer is 80A-120A.
According to another aspect of the application, there is provided a semiconductor structure comprising a base, a P-type body region, a plurality of P-type doped regions, a first gate oxide layer, a plurality of second gate oxide layers, and a gate layer, wherein the base comprises a substrate, an epitaxial layer and a plurality of field plates, the epitaxial layer is located on a surface of the substrate, the epitaxial layer comprises an N-type drift region, a surface of the N-type drift region away from the substrate is flush with a surface of the epitaxial layer away from the substrate, and a plurality of field plates are arranged on the surface of the N-type drift region away from the substrate at intervals; the P-type body region is positioned in part of the epitaxial layer at one side of the N-type drift region; a plurality of P-type doped regions are positioned in the N-type drift region between any two adjacent field plates; the first gate oxide layer is positioned on a part of the surface of the P-type body region, which is far away from the substrate, on a part of the surface of the epitaxial layer, which is far away from the substrate, between the P-type body region and the N-type drift region, and on a part of the surface of the N-type drift region, which is far away from the substrate, and the first gate oxide layer is in contact with the adjacent field plate; the second grid oxide layers are positioned on the inner walls of grooves formed by any two adjacent field plates; the gate layer is positioned on the surface of the first gate oxide layer far away from the epitaxial layer, the surface of the second gate oxide layer far away from the epitaxial layer, the side wall of the second gate oxide layer, the surface of the field plate on two sides of the second gate oxide layer far away from the epitaxial layer and part of the side wall of the field plate.
Further, the semiconductor structure further comprises a source region and a drain region, wherein the source region is positioned in the P-type body region at one side of the first gate oxide layer; the drain region is located in the N-type drift region on a side of the field plate remote from the P-type body region.
Further, the semiconductor structure further includes a metal silicide layer on a portion of a surface of the gate layer remote from the epitaxial layer, a surface of the source region remote from the substrate, and a surface of the drain region remote from the substrate.
Further, the thickness range of the first gate oxide layer and the second gate oxide layer is 80A-120A.
In the method for manufacturing the semiconductor structure, firstly, a substrate is provided, the substrate comprises a substrate, an epitaxial layer and a plurality of field plates, the epitaxial layer is located on the surface of the substrate, the epitaxial layer comprises an N-type drift region, the exposed surface of the N-type drift region is flush with the exposed surface of the epitaxial layer, and the field plates are arranged on the surface, far away from the substrate, of the N-type drift region at intervals; forming a P-type body region in part of the epitaxial layer at one side of the N-type drift region, and forming a plurality of P-type doped regions in the N-type drift region between any two adjacent field plates; then, forming a first gate oxide layer on the exposed surface of part of the P-type body region, the exposed surface of the epitaxial layer between the P-type body region and the N-type drift region and the exposed surface of part of the N-type drift region, and forming a plurality of second gate oxide layers on the inner walls of grooves formed by any two adjacent field plates in a one-to-one correspondence manner, wherein the first gate oxide layer is in contact with the adjacent field plates; and finally, forming a gate layer on the surface of the first gate oxide layer far away from the epitaxial layer, the exposed surface of the second gate oxide layer, the surface of the field plates on two sides of the second gate oxide layer far away from the epitaxial layer and part of the side walls of the field plates. According to the method, the plurality of P-type doped regions and the second grid oxide layer on the surface of the P-type doped regions are formed in the N-type drift region, the second grid oxide layer and the grid layer on the second grid oxide layer form a plurality of grids, and the distribution intensity of an electric field in the N-type drift region is optimized due to the doping inversion of the P-type doped regions and the N-type drift region, so that the electric field of the N-type drift region can be effectively dispersed, the surface depletion region can be reasonably dispersed at the interface widening position of the substrate and the field plate, breakdown withstand voltage of the device is effectively improved, the size reduction of the device is facilitated, the performance of the device is improved, and the problem that the device has higher power consumption due to higher breakdown withstand voltage in the prior art is solved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiments of the application and together with the description serve to explain the application and do not constitute an undue limitation to the application. In the drawings:
FIG. 1 illustrates a flow chart of a method of fabricating a semiconductor structure according to an exemplary embodiment of the present application;
fig. 2 shows a schematic structural diagram after forming an epitaxial layer according to one embodiment of the present application;
fig. 3 shows a schematic structure after forming an N-type drift region according to an embodiment of the present application;
FIG. 4 shows a schematic structural diagram after forming a field oxide layer according to one embodiment of the present application;
FIG. 5 shows a schematic structural view of a substrate according to one embodiment of the present application;
FIG. 6 illustrates a schematic structure after forming a mask layer according to one embodiment of the present application;
FIG. 7 illustrates a schematic structure after forming a patterned mask layer according to one embodiment of the present application;
fig. 8 shows a schematic structural diagram after forming a P-type body region and a P-type doped region according to an embodiment of the present application;
FIG. 9 illustrates a schematic structural diagram after forming an oxide layer according to one embodiment of the present application;
fig. 10 illustrates a schematic structure after forming a first gate oxide and a second gate oxide according to one embodiment of the present application;
FIG. 11 illustrates a schematic structure after forming a gate layer according to one embodiment of the present application;
FIG. 12 illustrates a schematic structure after forming source and drain regions according to one embodiment of the present application;
fig. 13 shows a schematic structural diagram after forming a metal silicide layer according to one embodiment of the present application.
Wherein the above figures include the following reference numerals:
101. a substrate; 102. an epitaxial layer; 103. an N-type drift region; 104. a field plate; 105. a field oxide layer; 201. a P-type body region; 202. a P-type doped region; 203. a mask layer; 301. a first gate oxide layer; 302. a second gate oxide layer; 303. a gate layer; 401. a source region; 402. a drain region; 501. a metal silicide layer.
Detailed Description
It should be noted that the following detailed description is illustrative and is intended to provide further explanation of the present application. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs.
It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments in accordance with the present application. As used herein, the singular is also intended to include the plural unless the context clearly indicates otherwise, and furthermore, it is to be understood that the terms "comprises" and/or "comprising" when used in this specification are taken to specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof.
It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. Furthermore, in the description and in the claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element or "connected" to the other element through a third element.
As described in the background art, the problem that the power consumption of the device is high due to the high breakdown voltage in the prior art is solved, and in order to solve the problem, the present application provides a method for manufacturing a semiconductor structure and the semiconductor structure.
According to an embodiment of the application, a method for manufacturing a semiconductor structure is provided.
Fig. 1 is a flow chart of a method of fabricating a semiconductor structure according to an embodiment of the present application. As shown in fig. 1, the method comprises the steps of:
step S101, providing a base, as shown in fig. 5, where the base includes a substrate 101, an epitaxial layer 102 and a plurality of field plates 104, the epitaxial layer 102 is located on a surface of the substrate 101, the epitaxial layer 102 includes an N-type drift region 103, an exposed surface of the N-type drift region 103 is flush with an exposed surface of the epitaxial layer 102, and the plurality of field plates 104 are spaced apart from each other and are located on a surface of the N-type drift region 103 away from the substrate 101;
step S102, as shown in fig. 8, of forming a P-type body region 201 in a portion of the epitaxial layer 102 on one side of the N-type drift region 103, and forming a plurality of P-type doped regions 202 in the N-type drift region 103 between any adjacent two of the field plates 104;
step S103, as shown in fig. 10, of forming a first gate oxide layer 301 on a part of the exposed surface of the P-type body region 201, on the exposed surface of the epitaxial layer 102 between the P-type body region 201 and the N-type drift region 103, and on a part of the exposed surface of the N-type drift region 103, and forming a plurality of second gate oxide layers 302 on the inner walls of the grooves formed by any two adjacent field plates 104 in a one-to-one correspondence manner, wherein the first gate oxide layer 301 is in contact with the adjacent field plates 104;
in step S104, as shown in fig. 11, a gate layer 303 is formed on the surface of the first gate oxide layer 301 away from the epitaxial layer 102, on the exposed surface of the second gate oxide layer 302, on the surface of the field plate 104 on both sides of the second gate oxide layer 302 away from the epitaxial layer 102, and on a portion of the sidewall of the field plate 104.
In the method for manufacturing the semiconductor structure, firstly, a base is provided, the base comprises a substrate, an epitaxial layer and a plurality of field plates, the epitaxial layer is positioned on the surface of the substrate, the epitaxial layer comprises an N-type drift region, the exposed surface of the N-type drift region is flush with the exposed surface of the epitaxial layer, and the field plates are arranged on the surface, far from the substrate, of the N-type drift region at intervals; forming a P-type body region in a part of the epitaxial layer at one side of the N-type drift region, and forming a plurality of P-type doped regions in the N-type drift region between any two adjacent field plates; then, forming a first gate oxide layer on the exposed surface of part of the P-type body region, the exposed surface of the epitaxial layer between the P-type body region and the N-type drift region and the exposed surface of part of the N-type drift region, and forming a plurality of second gate oxide layers on the inner walls of the grooves formed by any two adjacent field plates in a one-to-one correspondence manner, wherein the first gate oxide layer is in contact with the adjacent field plates; finally, a gate layer is formed on the surface of the first gate oxide layer far from the epitaxial layer, on the exposed surface of the second gate oxide layer, on the surface of the field plates on both sides of the second gate oxide layer far from the epitaxial layer, and on a part of the side walls of the field plates. According to the method, the plurality of P-type doped regions and the second grid oxide layer on the surface of the P-type doped regions are formed in the N-type drift region, the second grid oxide layer and the grid layer on the second grid oxide layer form a plurality of grids, and the distribution intensity of an electric field in the N-type drift region is optimized due to the doping inversion of the P-type doped regions and the N-type drift region, so that the electric field of the N-type drift region can be effectively dispersed, the surface depletion region can be reasonably dispersed at the interface widening position of the substrate and the field plate, breakdown withstand voltage of the device is effectively improved, the size reduction of the device is facilitated, the performance of the device is improved, and the problem that the device has higher power consumption due to higher breakdown withstand voltage in the prior art is solved.
In practical applications, the material of the gate layer may be polysilicon or other conductive materials, and those skilled in the art may select the gate layer according to practical requirements.
In order to separate a source region from a drain region and a plurality of P-type doped regions to be subsequently fabricated, in another embodiment of the present application, a substrate is provided, including: as shown in fig. 2, the above substrate 101 is provided; forming the epitaxial layer 102 on the exposed surface of the substrate 101, as shown in fig. 3, and performing ion implantation on a portion of the epitaxial layer 102 to form the N-type drift region 103; as shown in fig. 4, a field oxide layer 105 is formed on the exposed surfaces of the epitaxial layer 102 and the N-type drift region 103; as shown in fig. 4 and 5, a portion of the field oxide layer 105 is removed to expose the epitaxial layer 102 and a portion of the N-type drift region 103, and a plurality of field plates 104 are formed on a portion of the surface of the N-type drift region 103 at intervals on the remaining field oxide layer 105.
In practical applications, the substrate may be a P-type silicon substrate, the epitaxial layer may be P-type silicon, silicon carbide, gallium arsenide, indium phosphide or silicon germanium, and the material of the field oxide layer may be silicon oxide, such as silicon dioxide.
In another embodiment of the present application, forming a P-type body region in a portion of the epitaxial layer on one side of the N-type drift region, and forming a plurality of P-type doped regions in the N-type drift region between any two adjacent field plates, includes: as shown in fig. 5 and 6, a mask layer 203 is formed on the exposed surfaces of the epitaxial layer 102, the N-type drift region 103, and the field plate 104; as shown in fig. 7, the mask layer 203 is patterned so that a portion of the epitaxial layer 102 on one side of the N-type drift region 103 and the N-type drift region 103 between any two adjacent field plates 104 are exposed; forming the P-type body region 201 and the P-type doped regions 202 by ion implantation using the patterned mask layer 203 as a mask; as shown in fig. 7 and 8, the remaining patterned mask layer 203 is removed. When the device is conducted, the P-type body region plays a certain role in hole injection and pressure resistance, the P-type doped region can assist in depletion of the N-type drift region in reverse conduction of the device, the electric field distribution intensity in the N-type drift region is optimized, higher breakdown pressure resistance can be achieved under smaller size, the size of the device can be further reduced, and the saturation current of the device is improved.
In practical applications, the width of the P-type doped region is set according to the width of the field plate.
In order to form a gate structure later, in another embodiment of the present application, a first gate oxide layer is formed on a part of exposed surfaces of the P-type body region, on exposed surfaces of the epitaxial layer between the P-type body region and the N-type drift region, and on exposed surfaces of a part of the N-type drift region, and a plurality of second gate oxide layers are formed on inner walls of grooves formed by any two adjacent field plates in a one-to-one correspondence manner, including: as shown in fig. 9, an oxide layer 304 is formed on the exposed surfaces of the epitaxial layer 102, the P-type body region 201, the N-type drift region 103, the P-type doped region 202, and each of the field plates 104; as shown in fig. 9 and 10, a portion of the oxide layer 304 is removed, so that a portion of the epitaxial layer 102, a portion of the P-type body region 201, and a surface of each of the field plates 104 away from the epitaxial layer 102, and a portion of the sidewalls of the field plates 104 are exposed, thereby forming the first gate oxide layer 301 and the plurality of second gate oxide layers 302.
In another embodiment of the present application, the method further includes: as shown in fig. 12, a source region 401 is formed in the P-type body region 201 on one side of the first gate oxide layer 301; a drain region 402 is formed in the N-type drift region 103 on a side of the field plate 104 remote from the P-type body region 201. And forming a source region and a drain region to manufacture a complete transistor device, wherein when the device is conducted in the forward direction, positive voltages are applied to the gate layer and the drain region, and the source region is grounded.
Specifically, the source region and the drain region may be formed by ion implantation of N-type ions.
In order to form a low resistance contact, in another embodiment of the present application, the method further comprises: as shown in fig. 13, a metal silicide layer 501 is formed on a portion of the surface of the gate layer 303 away from the epitaxial layer 102, on a surface of the source region 401 away from the substrate 101, and on a surface of the drain region 402 away from the substrate 101.
Specifically, depositing metals such as nickel, cobalt, titanium and the like on the patterned semiconductor structure, performing heat treatment to enable metal atoms in the metal layer to diffuse into silicon in the source region, the drain region and the gate layer to form a metal silicide layer, and finally removing the metal remained by the reaction by a wet etching method to form the metal silicide layer.
In another embodiment of the present application, the thickness ranges of the first gate oxide layer and the second gate oxide layer are 80 a to 120 a. When the thicknesses of the first gate oxide layer and the second gate oxide layer are 80 a to 120 a, the P-type body region in contact with the first gate oxide layer and the P-type doped region in contact with the second gate oxide layer are inverted when a positive voltage is applied to the gate layer.
According to another aspect of the present application, there is provided a semiconductor structure, as shown in fig. 11, including a substrate, a P-type body region 201, a plurality of P-type doped regions 202, a first gate oxide layer 301, a plurality of second gate oxide layers 302, and a gate layer 303, wherein the substrate includes a substrate 101, an epitaxial layer 102, and a plurality of field plates 104, the epitaxial layer 102 is located on a surface of the substrate 101, the epitaxial layer 102 includes an N-type drift region 103, a surface of the N-type drift region 103 away from the substrate 101 is flush with a surface of the epitaxial layer 102 away from the substrate 101, and a plurality of field plates 104 are spaced apart on a surface of the N-type drift region 103 away from the substrate 101; the P-type body region 201 is located in a portion of the epitaxial layer 102 on the N-type drift region 103 side; a plurality of P-type doped regions 202 are located in the N-type drift region 103 between any adjacent two of the field plates 104; the first gate oxide layer 301 is located on a surface of a portion of the P-type body region 201 away from the substrate 101, on a surface of the epitaxial layer 102 between the P-type body region 201 and the N-type drift region 103 away from the substrate 101, and on a surface of a portion of the N-type drift region 103 away from the substrate 101, the first gate oxide layer 301 being in contact with the adjacent field plate 104; a plurality of second gate oxide layers 302 are located on the inner walls of the grooves formed by any two adjacent field plates 104; the gate layer 303 is located on a surface of the first gate oxide layer 301 away from the epitaxial layer 102, a surface of the second gate oxide layer 302 away from the epitaxial layer 102, a sidewall of the second gate oxide layer 302, a surface of the field plate 104 on both sides of the second gate oxide layer 302 away from the epitaxial layer 102, and a portion of a sidewall of the field plate 104.
The semiconductor structure comprises a substrate, a P-type body region, a plurality of P-type doped regions, a first gate oxide layer, a plurality of second gate oxide layers and a gate layer, wherein the substrate comprises a substrate, an epitaxial layer and a plurality of field plates, the epitaxial layer is positioned on the surface of the substrate, the epitaxial layer comprises an N-type drift region, the surface of the N-type drift region, which is far away from the substrate, is flush with the surface of the epitaxial layer, which is far away from the substrate, and the field plates are arranged on the surface of the N-type drift region, which is spaced apart from the substrate; the P-type body region is positioned in part of the epitaxial layer at one side of the N-type drift region; the P-type doped regions are positioned in the N-type drift region between any two adjacent field plates; the first gate oxide layer is positioned on a part of the surface of the P-type body region, which is far away from the substrate, on a part of the surface of the epitaxial layer, which is far away from the substrate, between the P-type body region and the N-type drift region, and on a part of the surface of the N-type drift region, which is far away from the substrate, and the first gate oxide layer is in contact with the adjacent field plate; the second grid oxide layers are positioned on the inner walls of grooves formed by any two adjacent field plates; the gate layer is located on a surface of the first gate oxide layer away from the epitaxial layer, a surface of the second gate oxide layer away from the epitaxial layer, a sidewall of the second gate oxide layer, a surface of the field plate on both sides of the second gate oxide layer away from the epitaxial layer, and a portion of a sidewall of the field plate. The N-type drift region of the semiconductor structure is provided with a plurality of P-type doped regions, the second grid oxide layer on the surface of the P-type doped regions and the grid layer on the second grid oxide layer form a plurality of grids, and the electric field distribution intensity in the N-type drift region is optimized due to the doping inversion of the P-type doped regions and the N-type drift region, so that the electric field of the N-type drift region can be effectively dispersed, the surface depletion region can be reasonably dispersed at the interface widening position of the substrate and the field plate, the breakdown withstand voltage of the device is effectively improved, the size of the device is reduced, the performance of the device is improved, and the problem that the higher power consumption of the device can be caused due to the higher breakdown withstand voltage in the prior art is solved.
In another embodiment of the present application, as shown in fig. 12, the semiconductor structure further includes a source region 401 and a drain region 402, where the source region 401 is located in the P-type body region 201 on one side of the first gate oxide layer 301; the drain region 402 is located in the N-type drift region 103 on a side of the field plate 104 remote from the P-type body region 201. When the device is turned on in the forward direction, positive voltages are applied to the gate layer and the drain region, and the source region is grounded.
Specifically, the source region and the drain region may be formed by ion implantation of N-type ions.
In order to form a low resistance contact, in another embodiment of the present application, as shown in fig. 13, the semiconductor structure further includes a metal silicide layer 501, where the metal silicide layer 501 is located on a portion of the surface of the gate layer 303 away from the epitaxial layer 102, on a surface of the source region 401 away from the substrate 101, and on a surface of the drain region 402 away from the substrate 101.
Specifically, depositing metals such as nickel, cobalt, titanium and the like on the patterned semiconductor structure, performing heat treatment to enable metal atoms in the metal layer to diffuse into silicon in the source region, the drain region and the gate layer to form a metal silicide layer, and finally removing the metal remained by the reaction by a wet etching method to form the metal silicide layer.
In another embodiment of the present application, the thickness ranges of the first gate oxide layer and the second gate oxide layer are 80 a to 120 a. When the thicknesses of the first gate oxide layer and the second gate oxide layer are 80 a to 120 a, the P-type body region in contact with the first gate oxide layer and the P-type doped region in contact with the second gate oxide layer are inverted when a positive voltage is applied to the gate layer.
In the foregoing embodiments of the present invention, the descriptions of the embodiments are emphasized, and for a portion of this disclosure that is not described in detail in this embodiment, reference is made to the related descriptions of other embodiments.
From the above description, it can be seen that the above embodiments of the present application achieve the following technical effects:
1) In the method for manufacturing the semiconductor structure, firstly, a base is provided, the base comprises a substrate, an epitaxial layer and a plurality of field plates, the epitaxial layer is positioned on the surface of the substrate, the epitaxial layer comprises an N-type drift region, the exposed surface of the N-type drift region is flush with the exposed surface of the epitaxial layer, and the field plates are arranged on the surface, far from the substrate, of the N-type drift region at intervals; forming a P-type body region in a part of the epitaxial layer at one side of the N-type drift region, and forming a plurality of P-type doped regions in the N-type drift region between any two adjacent field plates; then, forming a first gate oxide layer on the exposed surface of part of the P-type body region, the exposed surface of the epitaxial layer between the P-type body region and the N-type drift region and the exposed surface of part of the N-type drift region, and forming a plurality of second gate oxide layers on the inner walls of the grooves formed by any two adjacent field plates in a one-to-one correspondence manner, wherein the first gate oxide layer is in contact with the adjacent field plates; finally, a gate layer is formed on the surface of the first gate oxide layer far from the epitaxial layer, on the exposed surface of the second gate oxide layer, on the surface of the field plates on both sides of the second gate oxide layer far from the epitaxial layer, and on a part of the side walls of the field plates. According to the method, the plurality of P-type doped regions and the second grid oxide layer on the surface of the P-type doped regions are formed in the N-type drift region, the second grid oxide layer and the grid layer on the second grid oxide layer form a plurality of grids, and the distribution intensity of an electric field in the N-type drift region is optimized due to the doping inversion of the P-type doped regions and the N-type drift region, so that the electric field of the N-type drift region can be effectively dispersed, the surface depletion region can be reasonably dispersed at the interface widening position of the substrate and the field plate, breakdown withstand voltage of the device is effectively improved, the size reduction of the device is facilitated, the performance of the device is improved, and the problem that the device has higher power consumption due to higher breakdown withstand voltage in the prior art is solved.
2) The semiconductor structure comprises a substrate, a P-type body region, a plurality of P-type doped regions, a first gate oxide layer, a plurality of second gate oxide layers and a gate layer, wherein the substrate comprises a substrate, an epitaxial layer and a plurality of field plates, the epitaxial layer is positioned on the surface of the substrate, the epitaxial layer comprises an N-type drift region, the surface of the N-type drift region, which is far away from the substrate, is flush with the surface of the epitaxial layer, which is far away from the substrate, and the field plates are arranged on the surface of the N-type drift region, which is spaced apart from the substrate; the P-type body region is positioned in part of the epitaxial layer at one side of the N-type drift region; the P-type doped regions are positioned in the N-type drift region between any two adjacent field plates; the first gate oxide layer is positioned on a part of the surface of the P-type body region, which is far away from the substrate, on a part of the surface of the epitaxial layer, which is far away from the substrate, between the P-type body region and the N-type drift region, and on a part of the surface of the N-type drift region, which is far away from the substrate, and the first gate oxide layer is in contact with the adjacent field plate; the second grid oxide layers are positioned on the inner walls of grooves formed by any two adjacent field plates; the gate layer is located on a surface of the first gate oxide layer away from the epitaxial layer, a surface of the second gate oxide layer away from the epitaxial layer, a sidewall of the second gate oxide layer, a surface of the field plate on both sides of the second gate oxide layer away from the epitaxial layer, and a portion of a sidewall of the field plate. The N-type drift region of the semiconductor structure is provided with a plurality of P-type doped regions, the second grid oxide layer on the surface of the P-type doped regions and the grid layer on the second grid oxide layer form a plurality of grids, and the electric field distribution intensity in the N-type drift region is optimized due to the doping inversion of the P-type doped regions and the N-type drift region, so that the electric field of the N-type drift region can be effectively dispersed, the surface depletion region can be reasonably dispersed at the interface widening position of the substrate and the field plate, the breakdown withstand voltage of the device is effectively improved, the size of the device is reduced, the performance of the device is improved, and the problem that the higher power consumption of the device can be caused due to the higher breakdown withstand voltage in the prior art is solved.
The foregoing description is only of the preferred embodiments of the present application and is not intended to limit the same, but rather, various modifications and variations may be made by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.
Claims (11)
1. A method of fabricating a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises a substrate, an epitaxial layer and a plurality of field plates, the epitaxial layer is positioned on the surface of the substrate, the epitaxial layer comprises an N-type drift region, the exposed surface of the N-type drift region is flush with the exposed surface of the epitaxial layer, and the field plates are arranged on the surface, far away from the substrate, of the N-type drift region at intervals;
forming a P-type body region in a part of the epitaxial layer at one side of the N-type drift region, and forming a plurality of P-type doped regions in the N-type drift region between any two adjacent field plates;
forming a first gate oxide layer on the exposed surface of part of the P-type body region, the exposed surface of the epitaxial layer between the P-type body region and the N-type drift region and the exposed surface of part of the N-type drift region, and forming a plurality of second gate oxide layers on the inner walls of grooves formed by any two adjacent field plates in a one-to-one correspondence manner, wherein the first gate oxide layer is in contact with the adjacent field plates;
and forming a gate layer on the surface of the first gate oxide layer far away from the epitaxial layer, the exposed surface of the second gate oxide layer, the surface of the field plate on two sides of the second gate oxide layer far away from the epitaxial layer and part of the side wall of the field plate.
2. The method of claim 1, wherein providing a substrate comprises:
providing the substrate;
forming the epitaxial layer on the exposed surface of the substrate, and performing ion implantation on part of the epitaxial layer to form the N-type drift region;
forming a field oxide layer on the epitaxial layer and the exposed surface of the N-type drift region;
and removing part of the field oxide layer to expose the epitaxial layer and part of the N-type drift region, and forming a plurality of field plates arranged at intervals on part of the surface of the N-type drift region by the rest of the field oxide layer.
3. The method of claim 1, wherein forming a P-type body region in a portion of the epitaxial layer on one side of the N-type drift region and forming a plurality of P-type doped regions in the N-type drift region between any adjacent two of the field plates comprises:
forming a mask layer on the exposed surfaces of the epitaxial layer, the N-type drift region and the field plate;
patterning the mask layer to expose a part of the epitaxial layer at one side of the N-type drift region and the N-type drift region between any two adjacent field plates;
using the patterned mask layer as a mask, and adopting ion implantation to form the P-type body region and a plurality of P-type doped regions;
and removing the residual patterned mask layer.
4. The method of claim 1, wherein forming a first gate oxide layer on exposed surfaces of portions of the P-type body regions, exposed surfaces of the epitaxial layer between the P-type body regions and the N-type drift regions, and exposed surfaces of portions of the N-type drift regions, and forming a plurality of second gate oxide layers on inner walls of recesses formed by any adjacent two of the field plates in a one-to-one correspondence comprises:
forming an oxide layer on the epitaxial layer, the P-type body region, the N-type drift region, the P-type doped region and the exposed surfaces of the field plates;
and removing part of the oxide layer to expose part of the epitaxial layer, part of the P-type body region and the surface of each field plate far away from the epitaxial layer and part of the side wall of each field plate to form the first gate oxide layer and a plurality of second gate oxide layers.
5. The method according to claim 1, wherein the method further comprises:
forming a source region in the P-type body region on one side of the first gate oxide layer;
a drain region is formed in the N-type drift region on a side of the field plate remote from the P-type body region.
6. The method of claim 5, wherein the method further comprises:
a metal silicide layer is formed on a portion of the surface of the gate layer remote from the epitaxial layer, on a surface of the source region remote from the substrate, and on a surface of the drain region remote from the substrate.
7. The method of any one of claims 1-6, wherein the first gate oxide and the second gate oxide each have a thickness in a range of 80 a to 120 a.
8. A semiconductor structure fabricated by the method of fabricating a semiconductor structure according to any one of claims 1 to 7, comprising:
the epitaxial layer is positioned on the surface of the substrate, the epitaxial layer comprises an N-type drift region, the surface of the N-type drift region, which is far away from the substrate, is flush with the surface of the epitaxial layer, which is far away from the substrate, and a plurality of field plates are arranged on the surface of the N-type drift region, which is far away from the substrate, at intervals;
the P-type body region is positioned in part of the epitaxial layer at one side of the N-type drift region;
a plurality of P-type doped regions located in the N-type drift region between any adjacent two of the field plates;
a first gate oxide layer on a surface of a portion of the P-type body region remote from the substrate, on a surface of the epitaxial layer between the P-type body region and the N-type drift region remote from the substrate, and on a surface of a portion of the N-type drift region remote from the substrate, the first gate oxide layer in contact with an adjacent field plate;
the second grid oxide layers are positioned on the inner walls of grooves formed by any two adjacent field plates;
the gate layer is positioned on the surface, far away from the epitaxial layer, of the first gate oxide layer, the surface, far away from the epitaxial layer, of the second gate oxide layer, the side wall of the second gate oxide layer, the surface, far away from the epitaxial layer, of the field plates on two sides of the second gate oxide layer and part of the side wall of the field plates.
9. The semiconductor structure of claim 8, wherein the semiconductor structure further comprises:
a source region located in the P-type body region on one side of the first gate oxide layer;
and the drain region is positioned in the N-type drift region at one side of the field plate far away from the P-type body region.
10. The semiconductor structure of claim 9, wherein the semiconductor structure further comprises:
and the metal silicide layer is positioned on a part of the surface of the gate electrode layer, which is far away from the epitaxial layer, the surface of the source region, which is far away from the substrate, and the surface of the drain region, which is far away from the substrate.
11. The semiconductor structure of any one of claims 8-10, wherein the first gate oxide and the second gate oxide each have a thickness in the range of 80 a to 120 a.
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