CN114613846B - SGT device and preparation method thereof - Google Patents
SGT device and preparation method thereof Download PDFInfo
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- CN114613846B CN114613846B CN202210496322.4A CN202210496322A CN114613846B CN 114613846 B CN114613846 B CN 114613846B CN 202210496322 A CN202210496322 A CN 202210496322A CN 114613846 B CN114613846 B CN 114613846B
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66484—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with multiple gate, at least one gate being an insulated gate
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure
Abstract
The invention relates to an SGT device and a preparation method thereof, wherein the SGT device comprises: a substrate; the shallow trench isolation structure is positioned on the upper surface of the substrate and is divided into a first area and a second area in the length direction; the groove of the shallow trench isolation structure penetrates through the first region and the second region; the gate oxide layer is positioned on the upper surface of the shallow trench isolation structure of the first area, and a first accommodating space is formed above the trench; the isolation oxide layer is positioned on the upper surface of the shallow trench isolation structure of the second area and forms a second accommodating space above the trench; the polysilicon grid is positioned in the first accommodating space; the shielding grid is positioned in the second accommodating space; first conductivity type drift regions distributed in the first region and the second region; and the second conductive type body regions are distributed in the first region and are positioned on the upper surface of the first conductive type drift region. The invention can improve the voltage resistance of the device.
Description
Technical Field
The invention relates to the technical field of integrated circuit design and manufacture, in particular to an SGT device and a preparation method thereof.
Background
Compared to conventional power semiconductor devices, discrete gate mosfets (sgt mosfets) employ a balanced coupling design, which has a better figure of merit (FOM). The low-reverse-transmission-capacitance low-voltage power supply can simultaneously realize low on-resistance (Rdson) and low reverse transmission capacitance (Crss), thereby reducing the on-loss and the switching loss of a system and improving the service efficiency of an electronic product. The conventional SGT is usually a vertical device, so the vertical dimension of the SGT is limited by the processing conditions such as the depth of a trench, oxide filling, wafer warping and the like, the depth of the SGT cannot exceed 10 micrometers, and the voltage resistance of the SGT is limited to be generally not more than 300V.
Disclosure of Invention
The invention aims to provide an SGT device and a preparation method thereof, which can extend the pressure resistance of the SGT from medium-low pressure to high pressure or ultrahigh pressure field.
The technical scheme adopted by the invention for solving the technical problems is as follows: there is provided an SGT device comprising:
a substrate;
the shallow trench isolation structure is positioned on the upper surface of the substrate and is divided into a first area and a second area in the length direction; the groove of the shallow trench isolation structure penetrates through the first region and the second region;
the gate oxide layer is positioned on the upper surface of the shallow trench isolation structure of the first area, and a first accommodating space is formed above the trench;
the isolation oxide layer is positioned on the upper surface of the shallow trench isolation structure of the second area and forms a second accommodating space above the trench;
the polysilicon gate is positioned in the first accommodating space;
the shielding grid is positioned in the second accommodating space;
first conductivity type drift regions distributed in the first region and the second region; the first conductivity type drift region is located in the lower half part of the convex part of the shallow trench isolation structure in the first region, and the first conductivity type drift region fills the convex part of the shallow trench isolation structure in the second region;
and the second conductive type body regions are distributed in the first region and are positioned on the upper surface of the first conductive type drift region.
The polysilicon gate and the shielding gate are connected into a whole.
The width of the polysilicon gate is greater than the width of the shield gate.
The SGT device further comprises: a source electrode located in the first region and connected to the second conductivity-type body region; and the drain electrode is positioned in the second region and is connected with the first conduction type drift region.
The first conductivity type is N-type and the second conductivity type is P-type, or the first conductivity type is P-type and the second conductivity type is N-type.
The technical scheme adopted by the invention for solving the technical problems is as follows: also provides a preparation method of the SGT device, which comprises the following steps:
providing a substrate;
forming a shallow trench isolation structure on the upper surface of the substrate, wherein the shallow trench isolation structure is divided into a first area and a second area in the length direction; the groove of the shallow trench isolation structure penetrates through the first region and the second region;
forming a gate oxide layer on the upper surface of the shallow trench isolation structure positioned in the first region, wherein the gate oxide layer forms a first accommodating space above the trench;
forming an isolation oxide layer on the upper surface of the shallow trench isolation structure in the second region, wherein the isolation oxide layer forms a second accommodating space above the trench;
forming a polysilicon gate in the first accommodating space;
forming a shielding grid in the second accommodating space;
forming a first conductivity type drift region in the lower half part of the convex part of the shallow trench isolation structure of the first region and in the convex part of the shallow trench isolation structure of the second region;
and forming a second conductive type body region on the upper surface of the first conductive type drift region of the first region.
And when the isolation oxide layer is formed, the second accommodating space is communicated with the first accommodating space.
The width of the formed polysilicon gate is greater than the width of the formed shield gate.
After forming a second conductive type body region on the upper surface of the first conductive type drift region of the first region, the method further includes: forming a source electrode connected to the second conductive type body region in the first region; and forming a drain electrode connected to the first conductive type drift region in the second region.
The first conductivity type is N-type and the second conductivity type is P-type, or the first conductivity type is P-type and the second conductivity type is N-type.
Advantageous effects
Due to the adoption of the technical scheme, compared with the prior art, the invention has the following advantages and positive effects: the invention adopts the horizontally arranged SGT, so that the SGT is not limited by the depth of a channel, the application of the SGT can be extended to the field of high voltage (500V-1200V) or ultrahigh voltage (1700V-6500V) from low voltage to medium voltage, the grid performance can be well controlled, the voltage resistance of a device can be effectively improved by utilizing the balance of a power coupling, the Crss can be reduced, and the invention has popularization value in the fields of new energy inversion, high voltage transmission and new energy automobiles.
Drawings
Fig. 1 is a flowchart of a method of manufacturing an SGT device provided in a first embodiment of the present invention;
fig. 2 is a schematic cross-sectional structure of the structure obtained in step 2 in the method for manufacturing an SGT device according to the first embodiment of the present invention in the first region;
fig. 3 is a schematic cross-sectional structure diagram of the structure obtained in step 2 in the manufacturing method of the SGT device in the first embodiment of the present invention in the second region;
fig. 4 is a schematic cross-sectional structure of the structure obtained in step 3 in the method for manufacturing an SGT device according to the first embodiment of the present invention in the first region;
fig. 5 is a schematic cross-sectional structure of the structure obtained in step 4 in the method for manufacturing an SGT device according to the first embodiment of the present invention in the second region;
fig. 6 is a schematic cross-sectional structure of the structure obtained in step 5 in the method for manufacturing an SGT device according to the first embodiment of the present invention in the first region;
fig. 7 is a schematic cross-sectional structure of the structure obtained in step 5 in the method for manufacturing an SGT device according to the first embodiment of the present invention in the second region;
fig. 8 is a schematic cross-sectional structure of the structure obtained in step 6 in the method for manufacturing an SGT device according to the first embodiment of the present invention in the first region;
fig. 9 is a schematic cross-sectional structure of the structure obtained in step 6 in the method for manufacturing an SGT device according to the first embodiment of the present invention in the second region;
fig. 10 is a schematic cross-sectional structure of the structure obtained in step 7 in the method of manufacturing an SGT device in the first embodiment of the present invention in the first region;
fig. 11 is a schematic top view of the structure obtained in step 9 of the method for manufacturing an SGT device according to the first embodiment of the present invention;
fig. 12 is a schematic top view of another structure obtained in step 9 of the method for manufacturing an SGT device according to the first embodiment of the present invention.
Detailed Description
The invention will be further illustrated with reference to the following specific examples. It should be understood that these examples are for illustrative purposes only and are not intended to limit the scope of the present invention. Further, it should be understood that various changes or modifications of the present invention may be made by those skilled in the art after reading the teaching of the present invention, and such equivalents may fall within the scope of the present invention as defined in the appended claims.
The first embodiment of the present invention relates to a method for manufacturing an SGT device, as shown in fig. 1, including the steps of:
step 2, forming a shallow trench isolation structure 200 on the upper surface of the substrate 100, wherein the shallow trench isolation structure 200 is divided into a first area a and a second area B in the length direction; the trench 201 of the shallow trench isolation structure 200 penetrates through the first region a and the second region B;
step 3, forming a gate oxide layer on the upper surface of the shallow trench isolation structure positioned in the first region, wherein the gate oxide layer forms a first accommodating space above the trench;
step 4, forming an isolation oxide layer on the upper surface of the shallow trench isolation structure positioned in the second region, wherein the isolation oxide layer forms a second accommodating space above the trench;
step 5, forming a polysilicon gate in the first accommodating space, and forming a shielding gate in the second accommodating space;
step 6, forming a first conductive type drift region in the lower half part of the convex part of the shallow trench isolation structure of the first region and in the convex part of the shallow trench isolation structure of the second region;
and 7, forming a second conductive type body region on the upper surface of the first conductive type drift region of the first region.
In step 1, a substrate is provided, and the substrate 100 may be a silicon substrate, a silicon carbide substrate, or a silicon germanium substrate.
In step 2, as shown in fig. 2 and 3, a shallow trench isolation structure 200 is formed on the upper surface of the substrate 100, and the shallow trench isolation structure is divided into a first region a and a second region B. The shallow trench isolation structure 200 includes trenches 201 and protruding portions 202 arranged in a staggered manner, wherein the trenches 201 extend along the length direction of the substrate and penetrate through the first region a and the second region B, and the protruding portions 202 can serve as drift regions.
As an example, the length of the groove may be set according to actual requirements, and preferably, the length of the groove 201 is smaller than the length of the convex portion 202. The groove 201 is in a shallow groove form, and the ratio of the depth to the length of the groove is 1: 7-15. The number of the grooves 201 may be one or more. In this example, the number of the grooves 201 is three, and in practical use, the number of the grooves 201 is not limited thereto. The plurality of grooves 201 are arranged at intervals, and the grooves may be arranged at equal intervals or at unequal intervals.
In step 3, as shown in fig. 4, a gate oxide layer 300 is formed on the upper surface of the shallow trench isolation structure 200 located in the first region a, and the gate oxide layer 300 forms a first accommodating space 301 above the trench 201. In an example, a gate oxide layer 300 may be formed directly on the upper surface of the shallow trench isolation structure in the first region a, and the gate oxide layer 300 leaves a first accommodating space 301 above the trench 201. In another example, the gate oxide layer 300 may be formed first in the trench 201 of the shallow trench isolation structure, and the gate oxide layer 300 is made to exceed the depth of the trench 201 to exceed the raised portion 202; then, an etching process or a grinding process is used to remove the gate oxide layer above the trench to form a first accommodating space 301. Wherein, the gate oxide layer can be a silicon oxide layer.
In step 4, as shown in fig. 5, an isolation oxide layer 400 is formed on the upper surface of the shallow trench isolation structure 200 located in the second region B, and the isolation oxide layer 400 forms a second accommodating space 401 above the trench 201. In an example, an isolation oxide layer 400 may be formed directly on the upper surface of the shallow trench isolation structure in the second region B, and the isolation oxide layer 400 leaves a second accommodating space 401 above the trench 201. In another example, the isolation oxide layer 400 may be formed in the trench 201 of the shallow trench isolation structure first, and the isolation oxide layer 400 is made to exceed the depth of the trench 201 to exceed the raised portion 202; then, an etching process or a grinding process is used to remove the isolation oxide layer above the trench to form a second accommodating space 401. The isolation oxide layer may be a silicon oxide layer.
In step 5, as shown in fig. 6, a polysilicon gate 500 is formed in the first accommodating space 301, and as shown in fig. 7, a shield gate 600 is formed in the second accommodating space 401, wherein the width of the polysilicon gate 500 is greater than the width of the shield gate 600. In an example, the polysilicon gate 500 may be deposited directly in the first accommodating space 301 such that the polysilicon gate 500 in the first accommodating space 301 is flush with the upper surface of the gate oxide layer 300, and the shielding gate 600 may be deposited directly in the second accommodating space 401 such that the shielding gate 600 in the second accommodating space 401 is flush with the upper surface of the isolation oxide layer 400. In another example, first, a polysilicon gate 500 is formed on the first accommodating space 301 and the upper surface of the gate oxide layer 300, a shield gate 600 is formed on the second accommodating space 401 and the upper surface of the isolation oxide layer 400, and then the polysilicon gate on the upper surface of the gate oxide layer 300 and the shield gate on the upper surface of the isolation oxide layer 400 are removed by using an etching process or a grinding process. The deposition mode can adopt a physical vapor deposition process or a chemical vapor deposition process.
In step 6, as shown in fig. 8 and 9, a first conductivity type drift region 700 is formed in the lower half of the protruding portion 202 of the sti 200 in the first region a and in the protruding portion 202 of the sti 200 in the second region B. As an example, ion implantation of the first conductivity type may be performed from the substrate using an ion implantation process to form the first conductivity type drift region. As shown in fig. 8, in the first region a, the first-conductivity-type drift region 700 is within the lower half of the convex portion 202, which occupies 50% of the entire convex portion; as shown in fig. 9, in the second region B, the first-conductivity-type drift region 700 fills the entire convex portion 202.
In step 7, as shown in fig. 10, a second conductive type body region 800 is formed on the upper surface of the first conductive type drift region 700 of the first region a. As an example, the second conductive-type particle implantation may be performed using an ion implantation process to form the second conductive-type body region 800. In the first region a, the second conductive type body region 800 and the first conductive type drift region 700 occupy the same volume.
After the step 7, the following steps are also included:
step 8, forming a source electrode 900 connected to the second conductivity type body region 800 in the first region a;
in step 9, a drain electrode 1000 connected to the first conductive type drift region 700 is formed in the second region B. The structure obtained after the above-described steps 8 and 9 is shown in fig. 11. Both the source electrode 900 and the drain electrode 1000 may be metal electrodes, for example, copper electrodes, aluminum electrodes, gold electrodes, silver electrodes, nickel electrodes, or the like.
In an example, the first conductive type in each of the above steps may be an N type, and in this case, the second conductive type is a P type. In another example, the first conductive type in each step may be a P type, and in this case, the second conductive type is an N type.
Fig. 12 is another structure obtained in step 10 of the method for manufacturing an SGT device according to the first embodiment of the present invention. In the structure, the polysilicon gate 500 and the shield gate 600 are connected into a whole, so that the polysilicon gate 500 and the shield gate 600 can be formed simultaneously, and the preparation efficiency is improved. In this case, after the isolation oxide layer 400 is formed in step 4, the isolation oxide layer 400 may be communicated with the gate oxide layer 300 through an etching process or a grinding process.
A second embodiment of the present invention relates to an SGT device, as shown in fig. 9 to 11, including: a substrate 100; a shallow trench isolation structure 200 located on the upper surface of the substrate 100 and divided into a first region a and a second region B in the length direction; the trench 201 of the shallow trench isolation structure 200 penetrates through the first region a and the second region B; a gate oxide layer 300, which is located on the upper surface of the shallow trench isolation structure 200 of the first region a and forms a first accommodating space 301 above the trench 201; an isolation oxide layer 400 located on the upper surface of the shallow trench isolation structure 200 in the second region B, and forming a second accommodating space 401 above the trench 201; a polysilicon gate 500 located in the first accommodating space 301; the shielding grid 600 is positioned in the second accommodating space 401; first conductive type drift regions 700 distributed in the first region a and the second region B; the first conductivity type drift region 700 is located in the lower half of the raised portion 201 of the shallow trench isolation structure 200 in the first region a, and the first conductivity type drift region 700 fills the raised portion 201 of the shallow trench isolation structure in the second region B; second conductive type body regions 800 are distributed in the first region a and located on the upper surface of the first conductive type drift region 700.
The substrate 100 may be a silicon substrate, a silicon carbide substrate, or a silicon germanium substrate. The length of the groove 201 can be set according to actual needs, and preferably, the length of the groove 201 is smaller than the length of the convex part 202. The groove 201 is in a shallow groove form, and the ratio of the depth to the length of the groove is 1: 7-15. The number of the grooves 201 may be one or more. In this example, the number of the grooves 201 is three, and in practical use, the number of the grooves 201 is not limited thereto, and the plurality of grooves 201 are arranged at equal intervals.
The SGT device further includes: a source electrode 900 located in the first region a and connected to the second conductive type body region 90; and a drain electrode 1000 positioned in the second region B and connected to the first conductive type drift region 700. Both the source electrode 900 and the drain electrode 1000 may be a metal electrode, such as a copper electrode, an aluminum electrode, a gold electrode, a silver electrode, or a nickel electrode.
Wherein the first conductivity type is N-type and the second conductivity type is P-type, or the first conductivity type is P-type and the second conductivity type is N-type.
It should be noted that the present embodiment further includes another structure, which is shown in fig. 12, wherein the polysilicon gate 500 is integrated with the shielding gate 600.
The invention has the advantages that the SGT is transversely arranged, so that the SGT is not limited by the depth of a channel, the application of the SGT can be extended from low voltage to the high voltage (500V-1200V) or ultrahigh voltage (1700V-6500V), the grid performance can be well controlled, the voltage resistance of a device can be effectively improved by utilizing the balance of the coupling, the Crss can be reduced, and the SGT has popularization value in the fields of new energy inversion, high voltage power transmission and new energy automobiles.
Claims (10)
1. An SGT device, comprising:
a substrate;
the shallow trench isolation structure is positioned on the upper surface of the substrate and is divided into a first area and a second area in the length direction; the shallow trench isolation structure comprises grooves and raised parts which are arranged in a staggered mode; the groove of the shallow trench isolation structure penetrates through the first region and the second region;
the gate oxide layer is positioned on the upper surface of the shallow trench isolation structure of the first area, and a first accommodating space is formed above the trench;
the isolation oxide layer is positioned on the upper surface of the shallow trench isolation structure of the second area and forms a second accommodating space above the trench;
the polysilicon grid is positioned in the first accommodating space;
the shielding grid is positioned in the second accommodating space;
first conductivity type drift regions distributed in the first region and the second region; the first conductivity type drift region is located in the lower half part of the convex part of the shallow trench isolation structure in the first region, and the first conductivity type drift region fills the convex part of the shallow trench isolation structure in the second region;
and the second-conductivity-type body regions are distributed in the first region and are positioned on the upper surface of the first-conductivity-type drift region, and the second-conductivity-type body regions are positioned on the upper half part of the convex part of the shallow trench isolation structure in the first region.
2. The SGT device of claim 1 wherein the polysilicon gate is integral with the shield gate.
3. The SGT device of claim 1 wherein the width of the polysilicon gate is greater than the width of the shield gate.
4. The SGT device of claim 1, further comprising: a source electrode located in the first region and connected to the second conductivity-type body region; and the drain electrode is positioned in the second region and is connected with the first conduction type drift region.
5. The SGT device of claim 1, wherein the first conductivity type is N-type and the second conductivity type is P-type or the first conductivity type is P-type and the second conductivity type is N-type.
6. A preparation method of an SGT device is characterized by comprising the following steps:
providing a substrate;
forming a shallow trench isolation structure on the upper surface of the substrate, wherein the shallow trench isolation structure is divided into a first area and a second area in the length direction; the shallow trench isolation structure comprises grooves and raised parts which are arranged in a staggered mode; the groove of the shallow trench isolation structure penetrates through the first region and the second region;
forming a gate oxide layer on the upper surface of the shallow trench isolation structure positioned in the first region, wherein the gate oxide layer forms a first accommodating space above the trench;
forming an isolation oxide layer on the upper surface of the shallow trench isolation structure in the second region, wherein the isolation oxide layer forms a second accommodating space above the trench;
forming a polysilicon gate in the first accommodating space;
forming a shielding grid in the second accommodating space;
forming a first conductivity type drift region in the lower half part of the convex part of the shallow trench isolation structure of the first region and in the convex part of the shallow trench isolation structure of the second region;
and forming a second-conductivity-type body region on the upper surface of the first-conductivity-type drift region of the first region, wherein the second-conductivity-type body region is arranged on the upper half part of the convex part of the shallow trench isolation structure in the first region.
7. The SGT device manufacturing method according to claim 6, wherein the second accommodating space is communicated with the first accommodating space when the isolation oxide layer is formed.
8. The SGT device manufacturing method of claim 6 wherein the width of the polysilicon gate formed is greater than the width of the shield gate formed.
9. The SGT device manufacturing method of claim 6, wherein after forming the second conductivity type body region on the upper surface of the first conductivity type drift region of the first region, further comprising: forming a source electrode connected to the second conductive type body region in the first region; and forming a drain electrode connected to the first conductive type drift region in the second region.
10. A method for making an SGT device as claimed in claim 6, wherein the first conductivity type is N-type and the second conductivity type is P-type or the first conductivity type is P-type and the second conductivity type is N-type.
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| US8004051B2 (en) * | 2009-02-06 | 2011-08-23 | Texas Instruments Incorporated | Lateral trench MOSFET having a field plate |
| CN102412299A (en) * | 2010-09-21 | 2012-04-11 | 株式会社东芝 | Semiconductor device and manufacturing method thereof |
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