CN117637831A - Semiconductor device and method for manufacturing semiconductor device - Google Patents
Semiconductor device and method for manufacturing semiconductor device Download PDFInfo
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- CN117637831A CN117637831A CN202311556350.1A CN202311556350A CN117637831A CN 117637831 A CN117637831 A CN 117637831A CN 202311556350 A CN202311556350 A CN 202311556350A CN 117637831 A CN117637831 A CN 117637831A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 127
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 31
- 238000000034 method Methods 0.000 title claims abstract description 12
- 230000007704 transition Effects 0.000 claims abstract description 57
- 239000002019 doping agent Substances 0.000 claims abstract description 53
- 238000003860 storage Methods 0.000 claims description 50
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 26
- 229920005591 polysilicon Polymers 0.000 claims description 26
- 238000005530 etching Methods 0.000 claims description 17
- 239000000758 substrate Substances 0.000 claims description 10
- 238000005468 ion implantation Methods 0.000 claims description 9
- 238000000151 deposition Methods 0.000 claims description 5
- 230000003647 oxidation Effects 0.000 claims description 4
- 238000007254 oxidation reaction Methods 0.000 claims description 4
- 230000005684 electric field Effects 0.000 abstract description 23
- 238000009826 distribution Methods 0.000 abstract description 9
- 238000009792 diffusion process Methods 0.000 description 7
- -1 phosphorus ion Chemical class 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 229910052698 phosphorus Inorganic materials 0.000 description 4
- 230000000903 blocking effect Effects 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
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Abstract
The invention discloses a semiconductor device and a method for manufacturing the semiconductor device, the semiconductor device includes: a base; a drift layer of the first conductivity type; a well layer of the second conductivity type; a base layer of the second conductivity type, the base layer and the well layer being arranged in a second direction, the well layer having a depth greater than a depth of the base layer; the first groove is arranged in the transition region, the depth of the first groove extends from the first main surface towards the first direction, the first groove is positioned between the well layer and the base layer in the second direction, and two sides of the first groove in the second direction are respectively contacted with the well layer and the base layer. Therefore, the first groove is arranged between the well layer and the base layer, so that the first groove can prevent the second conductive type dopant of the well layer from diffusing towards the base layer, a curved surface is prevented from being formed in the transition region, the electric field distribution of the transition region can be optimized, the electric field concentration is avoided, the reliability of the semiconductor device can be improved, and the safe working region of the semiconductor device can be increased.
Description
Technical Field
The present invention relates to the field of semiconductor devices, and more particularly, to a semiconductor device and a method for manufacturing the semiconductor device.
Background
The insulated gate bipolar transistor (insulated gate bipolar transistor, IGBT) is used as a high-voltage power device, and in practical application, the insulated gate bipolar transistor always works under the severe conditions of high voltage, high current, high frequency and the like, so that the requirements on the reliability and the safe working area of the IGBT device are improved.
In the related art, an insulated gate bipolar transistor includes an active region, a termination region and a transition region, in order to ensure the normal operation and voltage withstanding capability of the transition region, the transition region includes a well layer and a base layer, the depth and concentration of the dopant of the well layer are both greater than those of the dopant of the base layer, so that the dopant of the well layer diffuses toward the base layer, resulting in a curved surface between the well layer and the base layer, and when the device is voltage-withstanding in the reverse direction, electric field concentration is easily generated at the position, the electric field strength is high, which may result in a reduced safe operation region, and the reliability of the device is reduced.
Disclosure of Invention
The present invention aims to solve at least one of the technical problems existing in the prior art. Therefore, an object of the present invention is to provide a semiconductor device having a more uniform electric field distribution and a higher reliability.
The invention further provides a manufacturing method of the semiconductor device.
The semiconductor device according to an embodiment of the present invention includes: a base body having a first main face and a second main face, the first main face and the second main face being spaced apart from each other in a first direction; a drift layer of a first conductivity type, the drift layer being provided to the base body and being located between the first main surface and the second main surface; a well layer of a second conductivity type provided at a portion of a side of the drift layer facing the first main surface corresponding to a transition region of the semiconductor device, a side of the well layer adjacent to the first main surface constituting a part of the first main surface, a length of the well layer extending in a second direction and a depth extending in a first direction; a base layer of a second conductivity type, the base layer being provided on a side of the drift layer facing the first main surface, a length of the base layer extending in a second direction and extending from an active region of the semiconductor device to a transition region of the semiconductor device, a side of the base layer adjacent to the first main surface constituting a part of the first main surface, a depth of the base layer extending in the first direction, the base layer and the well layer being arranged in the second direction, a depth of the well layer being greater than a depth of the base layer; the first groove is formed in the transition region, the depth of the first groove extends from the first main face towards the first direction, the length of the first groove extends in the third direction, the first groove is located between the well layer and the base layer in the second direction, two sides of the first groove in the second direction are respectively in contact with the well layer and the base layer, and the first direction, the second direction and the third direction are perpendicular to each other.
Therefore, the first groove is arranged between the well layer and the base layer, so that the first groove can prevent the second conductive type dopant of the well layer from diffusing towards the base layer, a curved surface can be prevented from being formed in the transition region, the electric field distribution of the transition region can be optimized, the electric field concentration is avoided, the reliability of the semiconductor device can be improved, and the safe working region of the semiconductor device can be increased.
In some examples of the present invention, the depth of the first trench is D1, the depth of the base layer is D2, and D1 and D2 satisfy the relationship: d1 And (3) not less than D2.
In some examples of the present invention, the depth of the well layer is D3, and D1 and D3 satisfy the relationship: d1 is less than or equal to D3.
In some examples of the invention, the semiconductor device further includes: a carrier storage layer of a first conductivity type, the carrier storage layer being provided on a side of the drift layer facing the first main surface, the carrier storage layer being located between the drift layer and the base layer, a length of the carrier storage layer extending in a second direction and extending from an active region of the semiconductor device to a transition region of the semiconductor device, the carrier storage layer being located on a side of the first trench in the second direction facing the base layer, a depth of the carrier storage layer extending in the first direction, the depths of the carrier storage layer being D4, D2 and D1 satisfying the relation: d4+d2 is not more than D1.
In some examples of the present invention, the semiconductor device further includes a second trench having a depth extending from the first main surface toward the first direction to the drift layer, a length of the second trench extending in a second direction and extending from the active region of the semiconductor device to a transition region of the semiconductor device, the second trench being a plurality of the second trenches, the plurality of the second trenches being spaced apart in the third direction, the second trench and the first trench having a same depth.
The manufacturing method of the semiconductor device according to the embodiment of the invention is used for manufacturing the semiconductor device described above, and includes: implanting second conductivity type dopants with first doping concentration into a part of one side of the drift layer facing the first main surface, which corresponds to the transition region, so as to form the well layer with first depth; implanting a second-conductivity-type dopant of a second doping concentration at a side of the drift layer facing the first main surface to form a base layer of a second depth arranged with the well layer in a second direction, wherein the second doping concentration is smaller than the first doping concentration, and the second depth is smaller than the first depth; the first trench extending from the first main face toward a first direction is etched between the well layer and the base layer.
In some examples of the present invention, the step of etching the first trench extending from the first main surface toward the first direction between the well layer and the base layer includes: the ion implantation regions of the first trench and the well layer are spaced apart from each other in the second direction toward a boundary of one side of the base layer.
In some examples of the present invention, the ion implantation regions of the first trench and the well layer are spaced apart from each other by a distance D5 in the second direction toward a boundary of one side of the base layer, and D5 satisfies the relationship: d5 is more than or equal to 0.5um and less than or equal to 2.0um.
In some examples of the present invention, after the step of forming the well layer at a first depth by implanting a second conductivity type dopant at a first doping concentration into a portion of the drift layer corresponding to the transition region on a side of the drift layer facing the first main surface, and before the step of forming the well layer at a second doping concentration by implanting a second conductivity type dopant at a second doping concentration into a side of the drift layer facing the first main surface, forming a base layer at a second depth aligned with the well layer in a second direction, wherein the second doping concentration is less than the first doping concentration, and the second depth is less than the first depth, the method further comprises: and injecting a first conductive type dopant into one side of the drift layer facing the first main surface to form a carrier storage layer.
In some examples of the present invention, after the step of forming the carrier storage layer by implanting the first conductivity-type dopant into the drift layer on a side facing the first main surface, the method further includes: and using the high-temperature gas with the first preset temperature to push the trap for the first preset time.
In some examples of the present invention, the step of implanting a second conductivity type dopant having a first doping concentration into a portion of the drift layer facing the first main surface corresponding to the transition region, after the step of forming the well layer having a first depth, further includes: and using the high-temperature gas with the second preset temperature to push the trap for the second preset time.
In some examples of the present invention, after the step of implanting a second conductivity-type dopant of a second doping concentration at a side of the drift layer toward the first main surface to form a base layer of a second depth arranged in a second direction with the well layer, the method further includes: and using the high-temperature gas with the third preset temperature to push the trap for the third preset time.
In some examples of the present invention, after the step of etching the first trench extending from the first main surface toward the first direction between the well layer and the base layer, the semiconductor device further includes: growing an oxidation insulating layer on the surfaces of the well layer, the first groove and the base layer; depositing polysilicon on the surface of the oxidation insulating layer, and etching the polysilicon; and depositing dielectric layers on the surfaces of the polysilicon, the well layer and the base layer.
In some examples of the present invention, the step of etching the first trench extending from the first main surface toward a first direction between the well layer and the base layer, the semiconductor device further includes: and etching a second groove extending from the first main surface to the drift layer towards the first direction, wherein the second groove extends in a second direction and extends from the active region of the semiconductor device to the transition region of the semiconductor device, the second grooves are multiple, the second grooves are arranged at intervals in the third direction, and the depths of the second groove and the first groove are the same.
Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.
Drawings
The foregoing and/or additional aspects and advantages of the invention will become apparent and may be better understood from the following description of embodiments taken in conjunction with the accompanying drawings in which:
fig. 1 is a schematic view of a semiconductor device according to an embodiment of the present invention;
FIG. 2 is a layout schematic of a transition region according to an embodiment of the present invention;
FIG. 3 is a cross-sectional view of a transition zone along the A-A direction in accordance with an embodiment of the present invention;
FIG. 4 is a cross-sectional view of a transition zone along the B-B direction in accordance with an embodiment of the present invention;
FIG. 5 is a cross-sectional view of a transition zone along the C-C direction in accordance with an embodiment of the present invention;
fig. 6 is a flowchart of a method of manufacturing a semiconductor device according to an embodiment of the present invention;
fig. 7 is a flowchart of a method of manufacturing a semiconductor device according to another embodiment of the present invention;
fig. 8 is a cross-sectional view of structure 1 according to an embodiment of the invention;
FIG. 9 is a cross-sectional view of structure 2 according to an embodiment of the invention;
FIG. 10 is a cross-sectional view of structure 3 according to an embodiment of the invention;
FIG. 11 is a cross-sectional view of structure 4 according to an embodiment of the present invention;
FIG. 12 is a cross-sectional view of structure 5 according to an embodiment of the invention;
FIG. 13 is a cross-sectional view of structure 6 according to an embodiment of the invention;
fig. 14 is a cross-sectional view of structure 7 according to an embodiment of the invention.
Reference numerals:
100. a semiconductor device; 101. an active region; 102. a transition zone; 103. a termination region; 104. a gate pad;
10. a drift layer; 11. a well layer; 12. a base layer; 13. a carrier storage layer; 14. a dielectric layer;
20. a first trench; 30. A second trench;
40. oxidizing the insulating layer; 50. Trench gate polysilicon; 60. Planar gate polysilicon;
70. a base; 71. a first major face; 72. a second major face.
Detailed Description
Embodiments of the present invention will be described in detail below, by way of example with reference to the accompanying drawings.
A semiconductor device 100 according to an embodiment of the present invention, the semiconductor device 100 may employ a manufacturing method of the semiconductor device 100, is described below with reference to fig. 1 to 14. The semiconductor device 100 may be an insulated gate bipolar transistor. In the following description, N and P denote conductivity types of semiconductors, and in the present invention, the first conductivity type is described as N type and the second conductivity type is described as P type.
As shown in connection with fig. 1 to 5, a semiconductor device 100 according to the present invention may mainly include: a body 70, a drift layer 10 of a first conductivity type, a well layer 11 of a second conductivity type, and a base layer 12 of a second conductivity type.
Specifically, the body 70 has a first main surface 71 and a second main surface 72, the first main surface 71 and the second main surface 72 are spaced apart from each other in the first direction, by disposing the drift layer 10 within the body 70 such that the drift layer 10 is located between the first main surface 71 and the second main surface 72, and disposing the well layer 11 at a portion of the drift layer 10 corresponding to the transition region 102 of the semiconductor device 100 on a side facing the first main surface 71, a side of the well layer 11 adjacent to the first main surface 71 constitutes a portion of the first main surface 71, a length of the well layer 11 extends in the second direction, a depth of the well layer 11 extends in the first direction, and a portion of the drift layer 10 corresponding to the transition region 102 of the semiconductor device 100 on a side facing the first main surface 71 is further disposed with the base layer 12, a side of the base layer 12 adjacent to the first main surface 71 constitutes a portion of the first main surface 71, a length of the base layer 12 extends in the second direction and extends from the active region 101 of the semiconductor device 100 to the transition region 102 of the semiconductor device 100, and a depth of the base layer 12 extends in the first direction, such that the base layer 12 and the base layer 11 and the second layer 11 are arranged in the first direction to form a semiconductor device 100 having a normal operation structure.
Considering that the transition region 102 of the semiconductor device 100 is located between the termination region 103 and the active region 101, the structure of the transition region 102 is relatively complex, and voltage breakdown is relatively easy to occur there, by providing the well layer 11 such that the depth of the well layer 11 is set to be greater than the depth of the base layer 12, the doping concentration of the second conductivity type dopant in the well layer 11 is greater than the doping concentration of the second conductivity type dopant in the base layer 12, the electric field distribution of the transition region 102 can be optimized, and the voltage withstand capability of the transition region 102 can be improved.
As shown in conjunction with fig. 2 and 3, the semiconductor device 100 may further include: the first trench 20 is disposed in the transition region 102, the depth of the first trench 20 extends from the first main surface 71 toward the first direction, the length of the first trench 20 extends in the third direction, the first trench 20 is located between the well layer 11 and the base layer 12 in the second direction, and two sides of the second direction of the first trench 20 are respectively in contact with the well layer 11 and the base layer 12, wherein the first direction, the second direction and the third direction are mutually perpendicular.
Specifically, considering that the base layer 12 is spaced apart from the well layer 11 in the second direction, and that there is a difference in doping concentration of the second conductivity type dopant in the base layer 12 and the well layer 11, the second conductivity type dopant in the well layer 11 may diffuse toward the base layer 12 in the second direction, and that the junction of the base layer 12 and the well layer 11 may form a curved surface due to the difference in depth of the base layer 12 and the well layer 11, the semiconductor device 100 may have electric field concentration at the position where the electric field concentration occurs at the time of reverse withstand voltage, the electric field intensity is large, and the safe operating region may become small, and the reliability of the semiconductor device 100 may be lowered.
Defining a direction perpendicular to the first direction and the second direction as a third direction, by providing the second trench 30, the oxide insulating layer 40 and the deposited polysilicon can be grown in the second trench 30, and the first trench 20 is located between the well layer 11 and the base layer 12 in the second direction, the first trench 20 has two sidewalls spaced apart in the second direction, the two sidewalls of the first trench 20 extend in the first direction, and by making the two sidewalls of the first trench 20 in the second direction contact with the well layer 11 and the base layer 12, respectively, so that the first trench 20 can be blocked between the well layer 11 and the base layer 12 in the second direction, thereby blocking the diffusion of the dopant of the second conductivity type in the well layer 11 toward the base layer 12, thereby avoiding the formation of a curved surface in the transition region 102, avoiding the occurrence of electric field concentration in the transition region 102 when the semiconductor device 100 is reverse voltage-withstanding, improving the reliability of the semiconductor device 100, and increasing the safe operating region of the semiconductor device 100.
Thus, by providing the first trench 20 such that the first trench 20 is located between the well layer 11 and the base layer 12, the first trench 20 can block the second conductivity type dopant of the well layer 11 from diffusing toward the base layer 12, can avoid forming a curved surface in the transition region 102, can optimize the electric field distribution of the transition region 102, and can avoid electric field concentration, thereby improving the reliability of the semiconductor device 100 and increasing the safe operating region of the semiconductor device 100.
As shown in fig. 3, the depth of the first trench 20 is D1, the depth of the base layer 12 is D2, and D1 and D2 satisfy the relationship: d1 And (3) not less than D2. Specifically, by setting the depth of the first trench 20 to be not smaller than the depth of the base layer 12, it is ensured that the first trench 20 completely blocks the base layer 12 in the first direction, so that the second conductivity type dopant in the well layer 11 can be more reliably blocked from diffusing into the base layer 12, the curved surface is prevented from being generated at the junction between the well layer 11 and the base layer 12, the reliability of the semiconductor device 100 can be further improved, and the safe operating area of the semiconductor device 100 can be increased.
Further, as shown in fig. 3, the depth of the well layer 11 is D3, and D1 and D3 satisfy the relation: d1 is less than or equal to D3. Specifically, the first trench 20 is further provided with a bottom wall connecting the two side walls toward the end of the second main surface 72, the curvature of the bottom wall is small, electric field concentration is liable to occur, and by setting the depth of the first trench 20 not larger than the depth of the well layer 11, it is ensured that the well layer 11 wraps at least part of the bottom wall of the first trench 20, so that the electric field near the bottom wall can be optimized, the electric field concentration is avoided, and the withstand voltage capability of the semiconductor device 100 can be ensured, and the reliability of the semiconductor device 100 can be ensured.
As shown in connection with fig. 2-5, the semiconductor device 100 may further include: a carrier storage layer 13 of the first conductivity type, the carrier storage layer 13 being provided on a side of the drift layer 10 facing the first main surface 71, the carrier storage layer 13 being located between the drift layer 10 and the base layer 12, a length of the carrier storage layer 13 extending in the second direction and from the active region 101 of the semiconductor device 100 to the transition region 102 of the semiconductor device 100, the carrier storage layer 13 being located on a side of the first trench 20 facing the base layer 12 in the second direction, a depth of the carrier storage layer 13 extending in the first direction, the depths of the carrier storage layer 13 being D4, D2 and D1 satisfying the relation: d4+d2 is not more than D1.
Specifically, by providing the carrier storage layer 13 of the first conductivity type, the carrier storage layer 13 is provided on the side of the drift layer 10 facing the first main surface 71, and the length of the carrier storage layer 13 is extended in the second direction and extends from the active region 101 of the semiconductor device 100 to the transition region 102 of the semiconductor device 100, so that the carrier storage layer 13 is at least partially located between the drift layer 10 and the base layer 12, and the depth of the carrier storage layer 13 is extended in the first direction, so that the carrier storage layer 13 plays a role of blocking holes, and electron injection into the drift layer 10 can be promoted, whereby the conductivity modulation effect can be enhanced, the forward conduction voltage drop of the semiconductor device 100 can be reduced, and the normal operation of the semiconductor device 100 can be promoted.
Further, the carrier storage layer 13 is located at a side of the first trench 20 facing the base layer 12 in the second direction, and by setting the sum of the depth of the carrier storage layer 13 and the depth of the base layer 12 to be smaller than the depth of the first trench 20, the carrier storage layer 13 can be completely blocked by the first trench 20 in the first direction, so that the diffusion of the first conductivity type dopant in the carrier storage layer 13 to the well layer 11 can be blocked, the generation of a PN junction with a small curvature in the second direction by the carrier storage layer 13 and the well layer 11 can be avoided, the electric field distribution of the transition region 102 can be optimized, the electric field concentration can be avoided, the reliability of the semiconductor device 100 can be further improved, and the safe operating region of the semiconductor device 100 can be increased.
As shown in fig. 2 and 5, the semiconductor device 100 may further include a second trench 30, the depth of the second trench 30 extending from the first main surface 71 toward the first direction to the drift layer 10, the length of the second trench 30 extending in the second direction, and the second trench 30 extending in the second direction from the active region 101 of the semiconductor device 100 to the transition region 102 of the semiconductor device 100, the second trench 30 being plural, the plural second trenches 30 being disposed at intervals in the third direction.
Specifically, by providing the second trench 30 such that the second trench 30 extends from the first main surface 71 toward the first direction to the drift layer 10, by providing the second trench 30 such that the second trench 30 extends in the second direction, by growing the oxide insulating layer 40 in the second trench 30 and depositing polysilicon, and providing the emitter layers of the first conductivity type on both sides of the second trench 30, it is possible for the second trench 30 to have a conductive channel with a current passing capability.
Further, the second trenches 30 may be provided in a plurality, the plurality of second trenches 30 are spaced apart in the third direction, and the second trenches 30 may extend from the active region 101 into the transition region 102 when extending in the second direction, so that the plurality of second trenches 30 may be connected to the gate pad 104 through the planar gate polysilicon 60 of the transition region 102, thereby allowing current to be drawn out and ensuring normal operation of the semiconductor device 100.
Further, the second trenches 30 and the first trenches 20 have the same depth. Specifically, the depth of the first trench 20 may be set to be the same as the depth of the first trench 20, so that the first trench 20 and the second trench 30 may be simultaneously etched, and thus the process flow of the semiconductor device 100 may be simplified.
The method of manufacturing the semiconductor device 100 according to the present invention can be used for manufacturing the semiconductor device 100 described above.
In some embodiments of the present invention, as shown in fig. 6, the method for manufacturing the semiconductor device 100 may mainly include the steps of: implanting a second conductivity type dopant of a first doping concentration into a portion of the drift layer 10 facing the first main surface 71 corresponding to the transition region 102 to form a well layer 11 of a first depth; a second conductivity type dopant of a second doping concentration is implanted at a side of the drift layer 10 facing the first main surface 71, forming a base layer 12 of a second depth arranged in a second direction with the well layer 11, wherein the second doping concentration is smaller than the first doping concentration, and the second depth is smaller than the first depth; a first trench 20 extending from the first main face 71 toward the first direction is etched between the well layer 11 and the base layer 12.
Specifically, in manufacturing the semiconductor device 100, a substrate material may be provided as the drift layer 10, a second conductivity type dopant having a first doping concentration may be implanted into a portion of the drift layer 10 facing the first main surface 71 corresponding to the transition region 102 to form the well layer 11 having a first depth, the voltage withstanding capability of the transition region 102 may be improved, and then a second conductivity type dopant having a second doping concentration may be implanted into a side of the drift layer 10 facing the first main surface 71 to form the base layer 12 having a second depth. Wherein, the second doping concentration is smaller than the first doping concentration, and the second depth is smaller than the first depth, namely: the doping concentration of the second conductivity type dopant in the well layer 11 is greater than the doping concentration of the second conductivity type dopant in the base layer 12, and the depth of the well layer 11 in the first direction is greater than the depth of the base layer 12 in the first direction, so that there is a depth difference and a concentration difference between the well layer 11 and the base layer 12 while ensuring the voltage withstand capability of the transition region 102.
Thereafter, the first trench 20 extending from the first main surface 71 toward the first direction is etched between the well layer 11 and the base layer 12, so that the first trench 20 can be blocked between the well layer 11 and the base layer 12, thereby blocking the diffusion of the second conductivity type dopant carrying the well layer 11 toward the base layer 12, and improving the reliability of the semiconductor device 100. Wherein the first conductive type dopant may be a phosphorus ion and the second conductive type dopant may be a boron ion, which is not particularly limited herein.
As shown in fig. 2, the step of etching the first trench 20 extending from the first main surface 71 toward the first direction between the well layer 11 and the base layer 12 may include: the ion implantation regions of the first trench 20 and the well layer 11 are spaced apart from each other in the second direction toward one side boundary of the base layer 12.
Specifically, after the second conductivity-type dopant is implanted into the portion of the drift layer 10 facing the first main surface 71 corresponding to the transition region 102, the second conductivity-type dopant diffuses in the second direction, that is: the well layer 11 finally formed will exceed the ion implantation region of the well layer 11 in the second direction, and in the step of etching the first trench 20 extending from the first main surface 71 towards the first direction between the well layer 11 and the base layer 12, the ion implantation regions of the first trench 20 and the well layer 11 are spaced apart from each other in the second direction towards a boundary of one side of the base layer 12, so that a distance can be reserved for the diffusion of the second conductivity type dopant in the well layer 11 in the second direction, and the first trench 20 can be ensured to be located between the well layer 11 and the subsequent base layer 12, so that electric field concentration is avoided, and the safe operating region of the semiconductor device 100 can be increased.
Further, the ion implantation regions of the first trench 20 and the well layer 11 are spaced apart from each other by a distance D4 in the second direction toward the boundary of one side of the base layer 12, and D5 satisfies the relationship: d5 is more than or equal to 0.5um and less than or equal to 2.0um. Specifically, by setting the spacing distance between the first trench 20 and the ion implantation region of the well layer 11 in the second direction toward the boundary of one side of the base layer 12 within a reasonable range, it is not only ensured that the first trench 20 is located between the well layer 11 and the subsequently formed base layer 12, avoiding the formation of a curved surface between the well layer 11 and the base layer 12, but also ensured that the base layer 12 formed after the diffusion of the second conductivity type dopant in the second direction at least partially encapsulates the bottom wall of the first trench 20, avoiding the occurrence of electric field concentration in the first trench 20, so that the electric field distribution of the transition region 102 can be optimized, the safe operating region of the semiconductor device 100 can be increased, and the reliability of the semiconductor device 100 can be improved.
In some embodiments of the present invention, as shown in fig. 7, after the step of forming the well layer 11 of the first depth by implanting the second conductive type dopant of the first doping concentration into the portion of the drift layer 10 facing the first main surface 71 corresponding to the transition region 102, and before the step of forming the base layer 12 of the second depth arranged with the well layer 11 in the second direction by implanting the second conductive type dopant of the second doping concentration into the drift layer 10 facing the first main surface 71, the method of manufacturing the semiconductor device 100 may further include: a first conductivity type dopant is injected into the drift layer 10 on the side facing the first main surface 71 to form a carrier storage layer 13.
Specifically, in the process of manufacturing the semiconductor device 100, after the well layer 11 is formed and before the base layer 12 is formed, the first conductivity type dopant may be further implanted at the side of the drift layer 10 toward the first main surface 71, so that the carrier storage layer 13 may be formed within the semiconductor device 100, and thus the operation performance of the semiconductor device 100 may be improved.
Further, the carrier storage layer 13 is at least partially located between the drift layer 10 and the base layer 12, and the carrier storage layer 13 is spaced apart from the well layer 11 in the second direction, so that the well layer 11 and the carrier storage layer 13 can also be separated by the first trench 20, and the first trench 20 can block the first conductivity type dopant in the carrier storage layer 13 from diffusing toward the well layer 11, whereby the formation of a PN junction of a small curvature can be prevented, and the electric field distribution can be optimized.
Further, as shown in fig. 7, after the step of forming the carrier storage layer 13 by injecting the first conductivity type dopant into the drift layer 10 on the side facing the first main surface 71, the method of manufacturing the semiconductor device 100 may further include: the high-temperature body high-temperature push-well using the first preset temperature for the first preset time, in this way, the rate and uniformity of the distribution and diffusion of the first conductivity type dopant in the substrate can be improved, so that the operation performance of the carrier storage layer 13 and thus the semiconductor device 100 can be optimized, and the reliability of the semiconductor device 100 can be improved. Wherein the high temperature gas can be N 2 The first preset temperature may be 1150 ℃, and the first preset time may be 120min, which is not particularly limited herein.
As shown in fig. 6 and 7, after the step of implanting the second conductivity-type dopant into the portion of the drift layer 10 facing the first main surface 71 corresponding to the transition region 102 to form the well layer 11, the method of manufacturing the semiconductor device 100 may further include: the high-temperature body of the second preset temperature is used for a second preset time, so that the rate and uniformity of the second conductivity type dopant distributed and diffused in the substrate can be improved, the well layer 11 and thus the working performance of the semiconductor device 100 can be optimized, and the reliability of the semiconductor device 100 can be improved. Wherein the high temperature gas can be N 2 The second preset temperature may be 1150 ℃ and the second preset time may be 80min, which is not particularly limited herein.
As shown in fig. 6 and 7, after the step of implanting a second conductivity-type dopant of a second doping concentration toward the side of the drift layer 10 facing the first main surface 71 to form the base layer 12 of a second depth arranged in the second direction with the well layer 11, the manufacturing method of the semiconductor device 100 may further include: the high temperature body high temperature push well using the third preset temperature for the third preset time, in this way, the rate and uniformity of the second conductivity type dopant distributed diffusion in the substrate can be improved, so that the operation performance of the base layer 12 and thus the semiconductor device 100 can be optimizedThe reliability of the semiconductor device 100 is improved. Wherein the high temperature gas can be N 2 The third preset temperature may be 1150 ℃, and the third preset time may be 80min, which is not particularly limited herein.
As shown in fig. 6 and 7, after the step of etching the first trench 20 extending from the first main surface 71 toward the first direction between the well layer 11 and the carrier storage layer 13, the manufacturing method of the semiconductor device 100 may further include: growing an oxide insulating layer 40 on the surfaces of the well layer 11, the first trench 20 and the base layer 12; depositing polysilicon on the surface of the oxidation insulating layer 40, and etching the polysilicon; a dielectric layer 14 is deposited on the surfaces of the polysilicon, the well layer 11 and the base layer 12.
Specifically, after etching the first trench 20 extending from the first main surface 71 toward the first direction between the well layer 11 and the base layer 12, an oxide insulating layer 40 may be further grown on the surfaces of the well layer 11, the first trench 20 and the carrier storage layer 13, and then polysilicon may be deposited on the surfaces of the oxide insulating layer 40, so that the polysilicon may be located on the surfaces of the well layer 11, the first trench 20 and the surface of the base layer 12, the polysilicon may be etched, the polysilicon located in the first trench 20 may be remained, the trench gate polysilicon 50 may be formed, and a portion of the polysilicon on the surface of the well layer 11 may be remained, the planar gate polysilicon 60 may be formed, and then the dielectric layer 14 may be deposited on the surfaces of the polysilicon, the well layer 11 and the base layer 12, so that the dielectric layer 14 may protect the surfaces of the polysilicon, the well layer 11 and the base layer 12, thereby improving the structural reliability of the semiconductor device 100.
As shown in fig. 6 and 7, the semiconductor device 100 may further include, while etching the first trench 20 extending from the first main surface 71 toward the first direction between the well layer 11 and the base layer: the second trenches 30 extending from the first main surface 71 toward the first direction to the drift layer 10 are etched, wherein the second trenches 30 extend in the second direction, the second trenches 30 are plural, the plural second trenches 30 are arranged at intervals in the third direction, the depths of the second trenches 30 and the first trenches 20 are the same, so that synchronous formation of the first trenches 20 and the second trenches 30 can be realized, and in the subsequent step, the oxide insulating layer 40 can be grown in the second trenches 30 and polysilicon can be deposited, so that the second trenches 30 are connected with the gate, thereby simplifying the manufacturing method of the semiconductor device 100 and ensuring normal operation of the semiconductor device 100.
The following describes, by way of example, a method of manufacturing the semiconductor device 100 with reference to fig. 3 and fig. 8 to 13:
as shown in fig. 8, a substrate material is provided, wherein the substrate material may be phosphorus doped with a silicon substrate having a resistivity of 25ohm. Forming structure 1.
As shown in FIG. 9, on the basis of the structure 1, boron ions as impurities are implanted with an energy of 60kev and a dose of 5E13cm -2 And performing high-temperature push trap, wherein the high-temperature push trap adopts gas N with high temperature of 1150 DEG C 2 The well layer 11 was formed for 80 min. Forming structure 2.
As shown in FIG. 10, on the basis of the structure 2, impurity phosphorus ions are implanted with an energy of 200kev and a dose of 5E12cm -2 And performing high-temperature push trap, wherein the high-temperature push trap adopts gas N with high temperature of 1150 DEG C 2 The time was 120min, and the carrier storage layer 13 was formed. Forming structure 3.
As shown in fig. 11, the first trenches 20 are etched on the basis of the structure 3. Forming structure 4.
As shown in FIG. 12, on the basis of the structure 4, a gas O of 1100℃was injected 2 A 0.12um thick silicon dioxide is grown as the insulating oxide insulating layer 40. Forming structure 5.
As shown in fig. 13, 0.8um thick polysilicon is deposited into the first trench 20 and onto the plane, and the excess polysilicon is etched away, based on the structure 5. Forming structure 6.
As shown in FIG. 14, on the basis of the structure 6, boron ions as impurities were implanted with an energy of 100kev and a dose of 2E13cm -2 And performing high-temperature push trap, wherein the high-temperature push trap adopts gas N with high temperature of 1150 DEG C 2 The base layer 12 was formed for 80 minutes. Forming structure 7.
As shown in fig. 3, 1um thick silicon dioxide is deposited as dielectric layer 14 on the basis of structure 7. The semiconductor device 100 is formed. Note that, here, taking the semiconductor device 100 provided with the carrier storage layer 13 as an example, the specific manufacturing process of the semiconductor device 100 not provided with the carrier storage layer 13 is the same, and the description thereof will be omitted.
Other configurations and operations of the semiconductor device 100 according to the embodiment of the present invention are known to those skilled in the art, and will not be described in detail herein.
In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings are merely for convenience in describing the present invention and simplifying the description, and do not indicate or imply that the device or element being referred to must have a specific orientation, be configured and operated in a specific orientation, and therefore should not be construed as limiting the present invention.
In the description of the present specification, reference to the terms "one embodiment," "some embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples.
While embodiments of the present invention have been shown and described, it will be understood by those of ordinary skill in the art that: many changes, modifications, substitutions and variations may be made to the embodiments without departing from the spirit and principles of the invention, the scope of which is defined by the claims and their equivalents.
Claims (14)
1. A semiconductor device, comprising:
-a substrate (70), the substrate (70) having a first main face (71) and a second main face (72), the first main face (71) and the second main face (72) being spaced apart from each other in a first direction;
a drift layer (10) of a first conductivity type, the drift layer (10) being provided between the first main surface (71) and the second main surface (72) and being provided on the substrate (70);
a well layer (11) of a second conductivity type, the well layer (11) being provided at a portion of the drift layer (10) corresponding to a transition region (102) of the semiconductor device (100) on a side of the first main surface (71), a side of the well layer (11) adjacent to the first main surface (71) constituting a portion of the first main surface (71), a length of the well layer (11) extending in a second direction and a depth extending in a first direction;
a base layer (12) of a second conductivity type, the base layer (12) being arranged on a side of the drift layer (10) facing the first main face (71), the base layer (12) having a length extending in a second direction and from an active region (101) of the semiconductor device (100) to a transition region (102) of the semiconductor device (100), a side of the base layer (12) adjacent to the first main face (71) constituting a part of the first main face (71), a depth of the base layer (12) extending in the first direction, the base layer (12) and the well layer (11) being arranged in the second direction, the well layer (11) having a depth greater than a depth of the base layer (12);
the first trench (20), first trench (20) set up in transition district (102), the degree of depth of first trench (20) is followed first principal plane (71) is towards first direction extension, the length of first trench (20) extends in the third direction, first trench (20) are located in the second direction well layer (11) with between base layer (12), the both sides of first trench (20) second direction respectively with well layer (11) and base layer (12) contact, wherein, first direction, second direction and third direction mutually perpendicular.
2. The semiconductor device according to claim 1, wherein the depth of the first trench (20) is D1, the depth of the base layer (12) is D2, and D1 and D2 satisfy the relation: d1 And (3) not less than D2.
3. The semiconductor device according to claim 2, wherein the depth of the well layer (11) is D3, and D1 and D3 satisfy the relation: d1 is less than or equal to D3.
4. The semiconductor device according to claim 2, further comprising: a carrier storage layer (13) of a first conductivity type, the carrier storage layer (13) being provided on a side of the drift layer (10) facing the first main surface (71), the carrier storage layer (13) being located between the drift layer (10) and the base layer (12), a length of the carrier storage layer (13) extending in a second direction and from an active region (101) of the semiconductor device (100) to a transition region (102) of the semiconductor device (100), the carrier storage layer (13) being located on a side of the first trench (20) facing the base layer (12) in the second direction, a depth of the carrier storage layer (13) extending in the first direction, the depths D4, D2 and D1 of the carrier storage layer (13) satisfying the relation: d4+d2 is not more than D1.
5. The semiconductor device according to claim 1, further comprising a second trench (30), a depth of the second trench (30) extending from the first main surface (71) toward the first direction to the drift layer (10), a length of the second trench (30) extending in a second direction and from an active region (101) of the semiconductor device (100) to a transition region (102) of the semiconductor device (100), the second trench (30) being plural, the second trenches (30) being disposed at intervals in the third direction, the depths of the second trench (30) and the first trench (20) being the same.
6. A manufacturing method of a semiconductor device for manufacturing the semiconductor device according to any one of claims 1 to 5, comprising:
implanting a second conductivity type dopant of a first doping concentration into a portion of the drift layer (10) facing the first main surface (71) corresponding to the transition region (102), thereby forming the well layer (11) of a first depth;
implanting a second conductivity type dopant of a second doping concentration at a side of the drift layer (10) facing the first main surface (71) to form a base layer (12) of a second depth arranged in a second direction with the well layer (11), wherein the second doping concentration is smaller than the first doping concentration, and the second depth is smaller than the first depth;
-etching the first trench (20) extending from the first main face (71) towards a first direction between the well layer (11) and the base layer (12).
7. The method according to claim 6, wherein the step of etching the first trench (20) extending from the first main surface (71) toward a first direction between the well layer (11) and the base layer (12) includes:
the ion implantation regions of the first trench (20) and the well layer (11) are spaced apart from each other in the second direction toward a boundary of one side of the base layer (12).
8. The method according to claim 7, wherein an ion implantation region of the first trench (20) and the well layer (11) is spaced apart from each other by a distance D5 in the second direction toward a boundary of one side of the base layer (12), the distance D5 satisfying a relationship: d5 is more than or equal to 0.5um and less than or equal to 2.0um.
9. The method of manufacturing a semiconductor device according to claim 6, wherein the step of implanting second conductivity type dopants of a first doping concentration into a portion of the drift layer (10) on a side facing the first main surface (71) corresponding to the transition region (102) is followed by the step of forming the well layer (11) of a first depth, and the step of implanting second conductivity type dopants of a second doping concentration into a side of the drift layer (10) on the first main surface (71) to form a base layer (12) of a second depth aligned with the well layer (11) in a second direction, wherein the second doping concentration is smaller than the first doping concentration, and the step of, prior to the second depth being smaller than the first depth, further comprises:
a first conductivity type dopant is injected into a side of the drift layer (10) facing the first main surface (71), thereby forming a carrier storage layer (13).
10. The method of manufacturing a semiconductor device according to claim 9, characterized in that after the step of forming the carrier storage layer (13) by injecting a first conductivity type dopant into a side of the drift layer (10) facing the first main surface (71), further comprising:
and using the high-temperature gas with the first preset temperature to push the trap for the first preset time.
11. The method of manufacturing a semiconductor device according to claim 6, wherein the step of implanting a second conductivity type dopant of a first doping concentration into a portion of the drift layer (10) facing the first main surface (71) corresponding to the transition region (102), after the step of forming the well layer (11) of a first depth, further comprises:
and using the high-temperature gas with the second preset temperature to push the trap for the second preset time.
12. The method of manufacturing a semiconductor device according to claim 6, wherein after the step of implanting a second conductivity-type dopant of a second doping concentration into a side of the drift layer (10) toward the first main surface (71) to form a base layer (12) of a second depth arranged in a second direction with the well layer (11), further comprising:
and using the high-temperature gas with the third preset temperature to push the trap for the third preset time.
13. The method of manufacturing a semiconductor device according to claim 6, characterized in that after the step of etching the first trench (20) extending from the first main surface (71) toward a first direction between the well layer (11) and the base layer (12), further comprising:
growing an oxide insulating layer (40) on the surfaces of the well layer (11), the first trench (20) and the base layer (12);
depositing polysilicon on the surface of the oxidation insulating layer (40), and etching the polysilicon;
a dielectric layer (14) is deposited on the surfaces of the polysilicon, the well layer (11) and the base layer (12).
14. The method of manufacturing a semiconductor device according to claim 6, characterized in that the step of etching the first trench (20) extending from the first main surface (71) toward a first direction between the well layer (11) and the base layer (12) further comprises:
-etching a second trench (30) extending from the first main surface (71) towards the first direction to the drift layer (10), wherein the second trench (30) extends in a second direction and extends from an active region (101) of the semiconductor device (100) to a transition region (102) of the semiconductor device (100), wherein the second trench (30) is a plurality, wherein a plurality of second trenches (30) are arranged at intervals in the third direction, and wherein the depths of the second trench (30) and the first trench (20) are the same.
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