CN109524473B - Low-power consumption power MOSFET device and preparation method - Google Patents
Low-power consumption power MOSFET device and preparation method Download PDFInfo
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- 238000002360 preparation method Methods 0.000 title claims abstract description 25
- 229910052751 metal Inorganic materials 0.000 claims abstract description 89
- 239000002184 metal Substances 0.000 claims abstract description 89
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 74
- 229920005591 polysilicon Polymers 0.000 claims abstract description 74
- 238000000034 method Methods 0.000 claims abstract description 51
- 239000004065 semiconductor Substances 0.000 claims abstract description 12
- 238000005530 etching Methods 0.000 claims description 29
- 230000008569 process Effects 0.000 claims description 22
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- 239000000758 substrate Substances 0.000 claims description 12
- 238000005468 ion implantation Methods 0.000 claims description 7
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- 238000004519 manufacturing process Methods 0.000 description 7
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- 230000005684 electric field Effects 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
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- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 239000010936 titanium Substances 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- 230000004075 alteration Effects 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 239000002360 explosive Substances 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
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- H—ELECTRICITY
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- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
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Abstract
The invention discloses a low-power consumption power MOSFET device and a preparation method thereof, and relates to the field of semiconductor power devices. The method is used for solving the problems of larger on-resistance and increased loss of the VDMOS device caused by larger drift region resistance of the conventional high-voltage device. The device includes: the shielding structure, the contact hole, the source electrode metal region layer epitaxial layer and the groove; the shielding structure consists of a second oxide layer and a second polysilicon layer, and is positioned at the bottom of the groove arranged in the epitaxial layer; the contact hole is positioned above the shielding structure, the bottom end of the contact hole is contacted with the upper end of the shielding structure, and the contact metal layer arranged in the contact hole extends out of the epitaxial layer to be contacted with the source metal region layer.
Description
Technical Field
The invention relates to the technical field of semiconductor power devices, in particular to a low-power consumption power MOSFET device and a preparation method thereof.
Background
As is well known, a common MOSFET (english: metal-Oxide-Semiconductor Field-Effect Transistor, chinese: metal Oxide semiconductor field effect transistor) is only suitable for the situation that the breakdown voltage of the drain and the source is low, and in practice, the common voltage is limited to 10V-30V, which is mainly limited by the structure of the common MOSFET, and the channel length required in the application of high drain-source voltage is firstly long, and the increase of the channel length brings unacceptable channel resistance, so that the device area is further increased. Secondly, the higher the drain-source voltage, the stronger the electric field strength at the gate oxide at the drain-source interface, which requires a thicker gate oxide, thus severely affecting the threshold voltage of the device.
The advent of double diffused MOS (double diffusion metal-oxide-semiconductor, DMOS) structure solves the problem of insufficient high voltage capability of conventional MOSFETs. First, LDMOS (english: lateral double-dif-fused MOSFET) was produced, and this structure is to add a low doped N-drift region between the channel and the high doped drain. Therefore, the blocking voltage of the LDMOS mainly depends on the width and the doping concentration of the drift region, and when the required withstand voltage is high, the width of the drift region must be increased and the doping concentration must be reduced, which will result in further increase of the device area and increase of the production cost. And the other VDMOS (vertical double-diffused MOSFET) structure has obviously more advantages than the LDMOS, and the effective utilization area of the chip is higher. The channel part is formed by two times of injection in the same window after diffusion, the length of the channel can be controlled by selecting the capability and angle of ion injection, a shorter channel can be formed, the process is completely compatible with the structure of a common MOSFET, a self-alignment process can be adopted, the production process is simple, and the cost is low. Therefore, the high-voltage power supply has the technical characteristics of high input impedance, low driving power, high switching speed, good temperature characteristic and the like.
The breakdown voltage of a VDMOS device is proportional to the on-resistance, which means that the larger the on-resistance is, the larger the on-loss of the device is, and JFET (Junction Field-Effect Transistor, abbreviated as Junction Field effect transistor) resistance and drift region resistance in the on-resistance of the VDMOS occupy a large portion. Along with the continuous development of economy and the continuous improvement of living standard of people, particularly the explosive growth and continuous updating of electronic products, the energy consumption is extremely increased, the energy saving consciousness of people is also gradually aroused, the semiconductor power electronic device which is an important component of the electronic products plays a very important role, and in order to reduce the conduction loss and the switching loss, the unit cell number is required to be continuously increased, the device area is correspondingly increased, and the production cost is increased in an intangible way. Therefore, the continuous optimization of the VDMOS structure reduces the conduction loss and the switching loss of the device, and meanwhile, reduces the production cost, so that the method is one of main research directions of the semiconductor power electronic device at present.
In order to improve the device withstand voltage in the conventional high-voltage device, the thickness of the drift region must be increased and the concentration of the drift region must be reduced, and the on-resistance mainly comes from the resistance of the drift region, which results in the on-resistance of the current VDMOS device being larger, thereby causing the increase of the on-loss.
In summary, the existing high-voltage device has the problems that the drift region resistance is larger, the on-resistance of the VDMOS device is larger, and the on-loss is increased.
Disclosure of Invention
The embodiment of the invention provides a low-power consumption power MOSFET device and a preparation method thereof, which are used for solving the problems that the on-resistance of a VDMOS device is larger and the on-loss is increased due to the fact that the resistance of a drift region is larger in the existing high-voltage device.
The embodiment of the invention provides a low-power consumption power MOSFET device, which comprises: the shielding structure, the contact hole, the source electrode metal region layer epitaxial layer and the groove;
the shielding structure consists of a second oxide layer and a second polysilicon layer, and is positioned at the bottom of the groove arranged in the epitaxial layer;
the contact hole is positioned above the shielding structure, the bottom end of the contact hole is contacted with the upper end of the shielding structure, and the contact metal layer arranged in the contact hole extends out of the epitaxial layer to be contacted with the source metal region layer.
Preferably, the semiconductor device further comprises a first P-type well region layer and N + A source region;
the first P-type well region layer is positioned above the epitaxial layer and extends into the epitaxial layer;
the N is + The source region is positioned above the first P-type well region layer and extends into the first P-type well region layer;
the contact metal layer is respectively connected with the first P-type well region layer and the N-type well region layer + The source regions are in contact.
Preferably, the semiconductor device further comprises a first oxide layer and a first polysilicon layer;
the bottom end of the first oxide layer is respectively contacted with the N+ source region layer, the P-type well region layer and the upper end of the epitaxial layer;
the upper end of the first oxide layer is contacted with the bottom end of the first polysilicon layer, and the second oxide layer arranged on the upper surface of the first polysilicon layer divides the first oxide layer and the first polysilicon layer arranged on the epitaxial layer into a plurality of sections;
the lower end part of the second oxide layer is contacted with the upper end of the first polysilicon layer, and is partially contacted with the N arranged on the epitaxial layer + The upper ends of the source regions are in contact.
The upper end of the second oxide layer is contacted with the lower end of the source electrode metal region layer.
Preferably, the trenches pass through the N in turn + The source region extends into the epitaxial layer; or the grooves sequentially penetrate through the N + The source region, the said first P type trap region layer, the said epitaxial layer, extend into the said substrate layer;
the inner wall of the groove is contacted with the second oxide layer, and the other side surface of the second oxide layer arranged in the groove is contacted with the second polysilicon.
Preferably, the semiconductor device further comprises a drain region metal layer; the drain region metal layer is located below the substrate layer.
The embodiment of the invention also provides a preparation method of the low-power consumption power MOSFET device, which comprises the following steps:
forming a groove in the epitaxial layer by an etching method, depositing a second oxide layer in the groove and above the epitaxial layer, and depositing a second polysilicon layer on the second oxide layer;
etching the second polysilicon layer positioned inside the groove and above the epitaxial layer through an etching process;
etching the second oxide layer on the side wall of the groove through an etching process, and determining the etched areas of the second oxide layer and the second polysilicon layer in the groove as contact holes;
and forming a metal contact layer in the contact hole by using a metal deposition method.
Preferably, before the forming the trench in the epitaxial layer by the etching method, the method further includes:
and sequentially forming a first oxide layer and a first polysilicon layer above the epitaxial layer, etching the first oxide layer and the first polysilicon layer above the epitaxial layer by an etching method, and forming a polysilicon gate region above the epitaxial layer.
Preferably, before the forming the trench in the epitaxial layer by the etching method, the method further includes:
performing first ion implantation on the epitaxial layer to form a first P-type well region layer, and activating doping elements of the first P-type well region layer through an annealing process;
performing first ion implantation on the epitaxial layer to form N + A source region, which is activated by an annealing process + The source region is doped with an element.
Preferably, after forming the metal contact layer in the contact hole by using a metal deposition method, the source metal region layer further includes:
and depositing a metal layer on the upper surfaces of the metal contact layer and the second oxide layer to form a source metal region layer.
Preferably, after forming the metal contact layer in the contact hole by using a metal deposition method, the method further comprises:
and depositing a metal layer below the substrate to form a drain metal region layer.
The embodiment of the invention provides a low-power consumption power MOSFET device and a preparation method thereof, wherein the device comprises the following components: the shielding structure, the contact hole, the source electrode metal region layer epitaxial layer and the groove; the shielding structure consists of a second oxide layer and a second polysilicon layer, and is positioned at the bottom of the groove arranged in the epitaxial layer; the contact hole is positioned above the shielding structure, the bottom end of the contact hole is contacted with the upper end of the shielding structure, and the contact metal layer arranged in the contact hole extends out of the epitaxial layer to be contacted with the source metal region layer. In the low-power consumption power MOSFET device, on the basis of a traditional VDMOS structure, a thick oxide layer and a polysilicon layer are deposited at the bottom of a groove to form a shielding structure, the bottom end of a contact hole is contacted with a second oxide layer and a second polysilicon layer in the shielding structure, a contact metal layer arranged in the contact hole extends out of an epitaxial layer to be contacted with a source metal area layer, and as the second oxide layer and the second polysilicon layer are deposited at the bottom of the groove, the shielding structure formed by the second oxide layer and the second polysilicon layer is in short circuit with the source metal area layer through the contact metal layer in the contact hole to form an electric field shielding structure, so that a RESURF effect is introduced in the vertical direction, and the device has lower on-resistance by utilizing a charge balance principle. Therefore, the problems that the on-resistance of the VDMOS device is large and the on-loss is increased due to the fact that the drift region resistance of the existing high-voltage device is large are solved.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic diagram of a low-power consumption power MOSFET device according to an embodiment of the present invention;
fig. 2 is a schematic flow chart of a method for manufacturing a low-power consumption power MOSFET device according to an embodiment of the present invention;
fig. 3 is a schematic illustration of epitaxial layer preparation according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a first oxide layer according to an embodiment of the present invention;
fig. 5 is a schematic diagram of a first polysilicon layer preparation according to an embodiment of the present invention;
FIG. 6 is a schematic diagram illustrating etching of a first polysilicon layer and a first oxide layer according to an embodiment of the present invention;
FIG. 7 is a schematic diagram of a first P-type well region layer and an N+ source region according to an embodiment of the present invention;
FIG. 8 is a schematic diagram of a trench preparation provided in an embodiment of the present invention;
FIG. 9 is a schematic diagram of a second oxide layer preparation according to an embodiment of the present invention;
fig. 10 is a schematic diagram of a second polysilicon layer preparation according to an embodiment of the present invention;
FIG. 11 is a schematic diagram of etching a second polysilicon layer according to an embodiment of the present invention;
FIG. 12 is a schematic diagram illustrating etching of a second oxide layer and formation of a contact hole according to an embodiment of the present invention;
FIG. 13 is a schematic illustration of a contact metal layer preparation according to an embodiment of the present invention;
fig. 14 is a schematic view of preparation of a source metal region layer and a drain metal region layer according to an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Fig. 1 schematically illustrates a structure of a low power consumption power MOSFET device according to an embodiment of the present invention, and as shown in fig. 1, the low power consumption power MOSFET device mainly includes a shielding structure, a contact hole 10, a source metal region layer 12, an epitaxial layer 2, and a trench 7.
In practical applications, in order to improve the withstand voltage of the conventional high-voltage device, it is generally necessary to increase the thickness of the drift region and reduce the concentration of the drift region, but this method may cause the on-resistance of the current VDMOS device to be larger, resulting in an increase in on-loss. In the embodiment of the present invention, in order to solve the above-mentioned problems, on the basis of the conventional VDMOS structure, a thick oxide layer and a polysilicon layer are deposited at the bottom of the trench 7, and the structure is shorted with the source region through the contact hole 10 to form an electric field shielding structure, so that RESURF effect is introduced in the vertical direction, and the device has a lower on-resistance by using the charge balance principle.
As shown in fig. 1, the low power consumption power MOSFET device provided by the embodiment of the invention is composed of a VDMOS structure and a shielding structure led out from a contact hole 10.
Specifically, the shielding structure is composed of a second oxide layer 8 and a second polysilicon layer 9, the shielding structure is located at the bottom of a groove 7 arranged in the epitaxial layer 2, a contact hole 10 is located above the shielding structure, the bottom end of the contact hole 10 is in contact with the second oxide layer 8 and the second polysilicon layer 9 in the shielding structure, a contact metal layer 11 arranged in the contact hole 10 extends out of the epitaxial layer 2 to be in contact with a source metal area layer, and as the second oxide layer 8 and the second polysilicon layer 9 are deposited at the bottom of the groove 7, the shielding structure composed of the second oxide layer 8 and the second polysilicon layer 9 is in short circuit with the source metal area layer through a contact metal layer 11 in the contact hole 10 to form an electric field shielding structure, so that a RESURF effect is introduced in the vertical direction, and the device has lower on-resistance by utilizing the charge balance principle.
Further, as shown in fig. 1, the low power consumption power MOSFET device further includes a first P-type well region layer 5 and N + A source region layer 6, wherein the first P-type well region layer 5 is located above the epitaxial layer 2 and extends into the epitaxial layer 2; n (N) + The source region layer 6 is located above the first P-type well region layer 5 and extends into the first P-type well region layer 5. Note that N + The source region layer 6 extends into the first P-type well region and does not extend into the epitaxial layer 2.
In the embodiment of the present invention, the contact metal layer 11 is in contact with the first P-type well region layer 5 and the n+ source region layer 6, respectively, and forms an ohmic contact layer.
Further, as shown in fig. 1, the low power MOSFET device further includes a first oxide layer 3 and a first polysilicon layer 4, where the first oxide layer 3 and the first polysilicon layer 4 are divided into a plurality of segments on the epitaxial layer 2 by a second oxide layer 8 disposed on an upper surface of the first polysilicon layer 4, so as to form a polycrystalline gate region. Specifically, the upper end of the first polysilicon layer 4 contacts the second oxide layer 8, and the second oxide layer 8 divides the first oxide layer 3 and the first polysilicon layer 4 into multiple segments, the sidewall of the first polysilicon layer 4 also contacts the second oxide layer 8, the sidewall of the first oxide layer 3 also contacts the second oxide layer 8, and further, the lower end of the second oxide layer 8Part is also connected with N arranged on the epitaxial layer 2 + The upper ends of the source region layers 6 are in contact.
Further, as shown in fig. 1, the upper end of the second oxide layer 8 is in contact with the lower end of the source metal region layer 12, and the lower end of the epitaxial layer 2 sequentially includes the substrate layer 1 and the drain region metal layer 13.
Since the first P-type well region layer 5 and the N-type well region layer are formed on the epitaxial layer 2 by ion implantation + A source region layer 6, a polycrystalline gate region divided into a plurality of segments by a second oxide layer 8 is formed on the epitaxial layer 2, and a substrate layer 1 is further provided at the lower end of the epitaxial layer 2. Thus, in the embodiment of the present invention, it is possible for the trenches 7 provided in the epitaxial layer 2 to pass through N in sequence + A source region layer 6, a first P-type well region layer 5, extending into the epitaxial layer 2; it is also possible to pass through N in sequence + A source region layer 6, a first P-type well region layer 5, an epitaxial layer 2 and a layer extending into the substrate layer 1. In the embodiment of the present invention, the specific position of the trench 7 in the epitaxial layer 2 is not limited.
Further, the inner wall of the trench 7 is in contact with one side face of the second oxide layer 8, and the other side face of the second oxide layer 8 provided in the trench 7 is in contact with the second polysilicon layer 9.
In order to more clearly describe the low-power consumption power MOSFET device provided by the embodiment of the invention, the preparation method of the low-power consumption power MOSFET device is described below.
Fig. 2 is a schematic flow chart of a method for manufacturing a low-power consumption power MOSFET device according to an embodiment of the present invention, and fig. 3 is a schematic flow chart of an epitaxial layer manufacturing method according to an embodiment of the present invention; FIG. 4 is a schematic diagram of a first oxide layer according to an embodiment of the present invention; fig. 5 is a schematic diagram of a first polysilicon layer preparation according to an embodiment of the present invention; FIG. 6 is a schematic diagram illustrating etching of a first polysilicon layer and a first oxide layer according to an embodiment of the present invention; FIG. 7 is a schematic diagram of a first P-type well region layer and an N+ source region according to an embodiment of the present invention; FIG. 8 is a schematic diagram of a trench preparation provided in an embodiment of the present invention; FIG. 9 is a schematic diagram of a second oxide layer preparation according to an embodiment of the present invention; FIG. 10 is a schematic diagram of a second polysilicon layer preparation according to an embodiment of the present invention; FIG. 11 is a schematic diagram of a second polysilicon layer etching process according to an embodiment of the present invention; FIG. 12 is a schematic diagram illustrating etching of a second oxide layer and formation of a contact hole according to an embodiment of the present invention; FIG. 13 is a schematic illustration of a contact metal layer preparation according to an embodiment of the present invention; fig. 14 is a schematic view illustrating the preparation of the source metal region layer 12 and the drain metal region layer 13 according to an embodiment of the present invention.
The following is a schematic flow chart of a preparation method provided in fig. 2, and the preparation method provided in fig. 3 to 14 is combined to describe in detail a preparation method of a low-power consumption power MOSFET device, specifically, as shown in fig. 2, the method mainly includes the following steps:
step 101, forming a groove 7 in the epitaxial layer 2 by an etching method, depositing a second oxide layer 8 in the groove 7 and above the epitaxial layer 2, and depositing a second polysilicon layer 9 on the second oxide layer 8;
step 102, etching the side wall of the groove 7 and the second polysilicon layer 9 above the epitaxial layer 2 through an etching process;
step 103, etching the second oxide layer 8 on the side wall of the trench 7 through an etching process, and determining the second oxide layer 8 and the second polysilicon layer 9 remained at the bottom of the trench 7 as a contact hole 10;
and 104, forming a metal contact layer in the contact hole 10 by a metal deposition method.
Specifically, as shown in FIG. 3, N with high doping concentration in the N-type of the first conductivity type + On the monocrystalline silicon substrate layer 1, an epitaxial layer 2 of a first conductivity type of N-type low doping concentration is grown.
As shown in fig. 4 and 5, a first oxide layer 3 is grown on the surface of the epitaxial layer 2 by an oxidation process, and a first polysilicon layer 4 is deposited on the first oxide layer 3 by an LPCVD process, and the first oxide layer 3 may also be referred to as a gate oxide layer.
As shown in fig. 6, the first polysilicon layer 4 is exposed through a photolithography process to define a gate polysilicon region, then the first polysilicon layer 4 and the first oxide layer 3 on top of the epitaxial layer 2 are removed through dry etching, the first polysilicon not protected by the photoresist is removed, the epitaxial layer 2 corresponding to the source region is exposed, and after the photoresist is removed, the gate polysilicon region is formed.
As shown in fig. 7, a first P-type well region implantation region is defined by a photolithography process, a first ion implantation doping element is performed on the epitaxial layer 2 to form a first P-type well region layer 5, and the doping element is activated by an annealing process; defining N by photoetching process + A source region implantation region for forming a second conductivity type N by performing a second ion implantation into the epitaxial layer 2 + The source region layer 6 activates the doping element by an annealing process.
As shown in fig. 8, the trench 7 region is defined by a photolithography process, and N is penetrated by dry etching + The source region layer 6 and the first P-type well region layer 5 extend into the epitaxial layer 2 to form a trench 7. The trench 7 may also be formed by penetrating the bottom of the epitaxial layer 2 and extending directly into the n+ monocrystalline silicon substrate layer 1.
As shown in fig. 9, at said N + A second oxide layer 8 is deposited over the source region layer 6 and the second polysilicon layer 9 and inside the trench 7 to form an insulating dielectric layer.
As shown in fig. 10, a second polysilicon layer 9 is deposited over the insulating dielectric layer.
As shown in fig. 11, dry etching is performed on the second polysilicon layer 9, leaving the second polysilicon layer 9 at the bottom of the trench 7.
As shown in fig. 12, the second oxide layer 8 inside the trench 7 is etched by a dry etching process, the second oxide layer 8 at the bottom of the trench 7 remains, and the second oxide layer 8 and the second polysilicon layer 9 at the bottom of the trench 7 have the same height, thereby forming the contact hole 10.
As shown in fig. 13, the contact hole 10 is filled with metal, a metal titanium bonding layer is deposited, a titanium nitride barrier layer is deposited on the metal titanium bonding layer, then a tungsten metal layer is deposited to form a contact metal layer 11, and the metal titanium bonding layer and the titanium nitride barrier layer and the N at the side end of the contact hole 10 + Source region layer 6 and P-type well region to form N + The source ohmic contact and the ohmic contact layer of the P-type well are contacted with the second oxide layer 8 and the second polysilicon layer 9 at the bottom of the side surface end of the contact hole 10.
If 14, forming a source metal region layer 12 by depositing metal on the upper surface of the second oxide layer 8, wherein the contact hole 10 is connected with the source metal region layer 12 through the contact metal layer 11 to form a source metal electrode;
and photoetching the metal area layer, and protecting a source metal electrode area of the MOS tube unit cell array area and a grid metal electrode area at the periphery of the MOS tube unit cell array area by using photoresist, namely defining a source metal electrode area and a grid metal electrode area pattern.
And selectively removing the metal region layer which is not protected by the photoresist by adopting a dry etching method, exposing the second oxide layer 8 serving as an insulating dielectric layer, removing the photoresist, forming a metal electrode of the MOS transistor source electrode by the metal region layer which is left in the unit cell array region, and forming a metal electrode of the MOS transistor gate electrode by the metal region layer which is left in the periphery of the unit cell array region.
And depositing a metal layer and a drain metal region layer 13 on the bottom surface of the N+ monocrystalline silicon substrate layer 1, wherein the metal layer forms the drain metal region layer 13 of the MOS tube.
It should be noted that, in the embodiment of the present invention, the doping types of the first polysilicon layer 4 and the second polysilicon layer 9 are N-type doping or P-type doping.
In summary, the embodiment of the present invention provides a low power consumption power MOSFET device, which includes: the shielding structure, the contact hole, the source electrode metal region layer epitaxial layer and the groove; the shielding structure consists of a second oxide layer and a second polysilicon layer, and is positioned at the bottom of the groove arranged in the epitaxial layer; the contact hole is positioned above the shielding structure, the bottom end of the contact hole is contacted with the upper end of the shielding structure, and the contact metal layer arranged in the contact hole extends out of the epitaxial layer to be contacted with the source metal region layer. In the low-power consumption power MOSFET device, on the basis of a traditional VDMOS structure, a thick oxide layer and a polysilicon layer are deposited at the bottom of a groove to form a shielding structure, the bottom end of a contact hole is contacted with a second oxide layer and a second polysilicon layer in the shielding structure, a contact metal layer arranged in the contact hole extends out of an epitaxial layer to be contacted with a source metal area layer, and as the second oxide layer and the second polysilicon layer are deposited at the bottom of the groove, the shielding structure formed by the second oxide layer and the second polysilicon layer is in short circuit with the source metal area layer through the contact metal layer in the contact hole to form an electric field shielding structure, so that a RESURF effect is introduced in the vertical direction, and the device has lower on-resistance by utilizing a charge balance principle. Therefore, the problems that the on-resistance of the VDMOS device is large and the on-loss is increased due to the fact that the drift region resistance of the existing high-voltage device is large are solved.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the invention.
It will be apparent to those skilled in the art that various modifications and variations can be made to the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.
Claims (7)
1. A low power MOSFET device, comprising: the semiconductor device comprises a shielding structure, a contact hole, a source electrode metal area layer, an epitaxial layer and a groove;
the shielding structure consists of a second oxide layer and a second polysilicon layer, and is positioned at the bottom of the groove arranged in the epitaxial layer;
the contact hole is positioned above the shielding structure, the bottom end of the contact hole is contacted with the upper end of the shielding structure, and the contact metal layer arranged in the contact hole extends out of the epitaxial layer to be contacted with the source metal region layer;
also comprises a first P-type well region layer and N + A source region;
the first P-type well region layer is positioned above the epitaxial layer and extends into the epitaxial layer;
the N is + The source region is positioned above the first P-type well region layer and extends into the first P-type well region layer;
the contact metal layer is respectively connected with the first P-type well region layer and the N-type well region layer + The source electrode area contacts;
the semiconductor device further comprises a first oxide layer and a first polysilicon layer;
the bottom ends of the first oxide layer are respectively connected with the N + The source electrode region layer is contacted with the upper end of the epitaxial layer;
the upper end of the first oxide layer is contacted with the bottom end of the first polysilicon layer, and the second oxide layer arranged on the upper surface of the first polysilicon layer divides the first oxide layer and the first polysilicon layer arranged on the epitaxial layer into a plurality of sections;
the lower end part of the second oxide layer is contacted with the upper end of the first polysilicon layer, and is partially contacted with the N arranged on the epitaxial layer + The upper end of the source electrode area contacts;
the upper end of the second oxide layer is contacted with the lower end of the source electrode metal region layer.
2. The device of claim 1, wherein the trenches sequentially pass through the N + The source region extends into the epitaxial layer; or the grooves sequentially penetrate through the N + The source region, the said first P type trap region layer, the said epitaxial layer, extend into the said substrate layer;
the inner wall of the groove is contacted with the second oxide layer, and the other side surface of the second oxide layer arranged in the groove is contacted with the second polysilicon.
3. The device of claim 2, further comprising a drain region metal layer; the drain region metal layer is located below the substrate layer.
4. The preparation method of the low-power consumption power MOSFET device is characterized by comprising the following steps of:
forming a groove in the epitaxial layer by an etching method, depositing a second oxide layer in the groove and above the epitaxial layer, and depositing a second polysilicon layer on the second oxide layer;
etching the second polysilicon layer positioned inside the groove and above the epitaxial layer through an etching process;
etching the second oxide layer on the side wall of the groove through an etching process, and determining the etched areas of the second oxide layer and the second polysilicon layer in the groove as contact holes;
forming a metal contact layer in the contact hole by a metal deposition method;
before the trench is formed in the epitaxial layer by the etching method, the method further comprises:
and sequentially forming a first oxide layer and a first polysilicon layer above the epitaxial layer, etching the first oxide layer and the first polysilicon layer above the epitaxial layer by an etching method, and forming a polysilicon gate region above the epitaxial layer.
5. The method of claim 4, wherein prior to forming the trench in the epitaxial layer by etching, further comprising:
performing first ion implantation on the epitaxial layer to form a first P-type well region layer, and activating doping elements of the first P-type well region layer through an annealing process;
performing first ion implantation on the epitaxial layer to form N + A source region, which is activated by an annealing process + The source region is doped with an element.
6. The method of claim 4, wherein after forming a metal contact layer in the contact hole by a metal deposition method, the source metal region layer further comprises:
and depositing a metal layer on the upper surfaces of the metal contact layer and the second oxide layer to form a source metal region layer.
7. The method of claim 4, wherein after forming a metal contact layer in the contact hole by a metal deposition method, further comprising:
and depositing a metal layer below the substrate to form a drain metal region layer.
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| CN102263133A (en) * | 2011-08-22 | 2011-11-30 | 无锡新洁能功率半导体有限公司 | Low-gate charge low-on resistance deep trench power metal oxide semiconductor field effect transistor (MOSFET) device and manufacturing method |
| US9761695B1 (en) * | 2016-05-31 | 2017-09-12 | Shanghai Huahong Grace Semiconductor Manufacturing Corporation | Method for fabricating a shield gate trench MOSFET |
| CN209216982U (en) * | 2018-12-29 | 2019-08-06 | 华羿微电子股份有限公司 | A kind of low-consumption power MOSFET element |
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| US20120037983A1 (en) * | 2010-08-10 | 2012-02-16 | Force Mos Technology Co., Ltd. | Trench mosfet with integrated schottky rectifier in same cell |
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| CN102263133A (en) * | 2011-08-22 | 2011-11-30 | 无锡新洁能功率半导体有限公司 | Low-gate charge low-on resistance deep trench power metal oxide semiconductor field effect transistor (MOSFET) device and manufacturing method |
| US9761695B1 (en) * | 2016-05-31 | 2017-09-12 | Shanghai Huahong Grace Semiconductor Manufacturing Corporation | Method for fabricating a shield gate trench MOSFET |
| CN209216982U (en) * | 2018-12-29 | 2019-08-06 | 华羿微电子股份有限公司 | A kind of low-consumption power MOSFET element |
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