CN205595339U - Integrated schottky diode's siC ditch cell type MOSFET device - Google Patents
Integrated schottky diode's siC ditch cell type MOSFET device Download PDFInfo
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- CN205595339U CN205595339U CN201521141019.4U CN201521141019U CN205595339U CN 205595339 U CN205595339 U CN 205595339U CN 201521141019 U CN201521141019 U CN 201521141019U CN 205595339 U CN205595339 U CN 205595339U
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- schottky diode
- drift layer
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- mosfet device
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- 229910052751 metal Inorganic materials 0.000 claims abstract description 21
- 239000002184 metal Substances 0.000 claims abstract description 21
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 238000007789 sealing Methods 0.000 claims description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 9
- 229920005591 polysilicon Polymers 0.000 claims description 9
- 238000004519 manufacturing process Methods 0.000 abstract description 5
- 230000000694 effects Effects 0.000 abstract description 4
- 238000002955 isolation Methods 0.000 abstract 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 23
- 238000001459 lithography Methods 0.000 description 15
- 238000001020 plasma etching Methods 0.000 description 15
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 12
- 238000005516 engineering process Methods 0.000 description 11
- 238000005468 ion implantation Methods 0.000 description 10
- 239000000463 material Substances 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 6
- 239000000377 silicon dioxide Substances 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 238000001259 photo etching Methods 0.000 description 5
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 238000000926 separation method Methods 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 229920006395 saturated elastomer Polymers 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- 229910003978 SiClx Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
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- Electrodes Of Semiconductors (AREA)
Abstract
The utility model provides an integrated schottky diode's siC ditch cell type MOSFET device, the device includes: 1 )Ditch cell type MOSFET: the N of N+ substrate on and the drift layer, N the drift layer contains the P trap that has a N+ source region of keeping apart each other, the U type channel in the P trap outside, there is the oxide layer on U type channel surface, has the grid in it, be the isolation layer on grid and the some N+ source regions, openly be the source electrode and the back for draining, 2 ) schottky diode: N in the drift layer N between the P trap the drift layer with the schottky contact that the source electrode metal formed. The utility model discloses an introduce schottky diode in ditch cell type siCMOSFET, at the device during operation, play freewheeling diode's effect, improved the efficiency and the reliability of circuit work, reduced the circuit cost of manufacture.
Description
Technical field
This utility model relates to a kind of semiconductor device, and the SiC being specifically related to a kind of integrated schottky diode is groove-shaped
MOSFET element.
Background technology
Carborundum (SiC) is to develop after first generation Semiconducting Silicon Materials, germanium and the second carrying semiconductor material GaAs, indium phosphide
The third generation semi-conducting material got up, the broad stopband of carbofrax material is 2～3 times of silicon and GaAs so that semiconductor device energy
(more than 500 DEG C) work and have the ability launching blue light at relatively high temperatures；Its high breakdown electric field is more equal than silicon and GaAs
Want high an order of magnitude, determine the high pressure of semiconductor device, high-power performance；Its high saturated electron drift velocity and low Jie
Electric constant determines the high frequency of device, high speed operation performance；The thermal conductivity of carborundum is 3.3 times of silicon, 10 times of GaAs,
Mean its good heat conductivity, the integrated level of circuit can be greatly improved, reduce cooling heat radiation system, thus reduce the body of complete machine
Long-pending.Therefore the most perfect along with carbofrax material and device technology, part Si field is carbonized silicon and is substituted within sight.Carbon
SiClx has the features such as broad-band gap, high critical breakdown strength, high thermal conductivity, the high saturated elegant speed of electronics, is particularly suitable for
High-power, high-voltage power electronic device, therefore becomes the study hotspot of current power electronic applications.
The theoretical maximum operating voltage scope of SiC base power device is more than 10kV, higher than silica-based insulated gate bipolar transistor (IGBT)
The running voltage of device；As unipolar device, its switching speed is faster than ambipolar silica-based IGBT, required epitaxial layer especially by
Decuple silica-based critical breakdown electric field in SiC and reduce, be accordingly regarded as substituting the ideal chose of silica-based IGBT device.
For gate-controlled switch type power electronic devices such as: IGBT, metal oxide layer semiconductor field-effect transistor (MOSFET)
Deng, in use, it is often with diode inverse parallel to play afterflow effect in circuit, power IGBT as shown in Figure 1
Circuit diagram antiparallel with diode.Silica-based IGBT is usually antiparallel diode is encapsulated into power model simultaneously,
Silica-based MOSFET then naturally form anti-paralleled diode due to p-well and drift region, is therefore not required to additionally increase diode
Encapsulation in parallel.
Although SiC base MOSFET also has the anti-paralleled diode of self-assembling formation, but owing to the energy gap of SiC is high, its
The cut-in voltage of PN junction diode is high, reaches about 3V, when using the anti-paralleled diode within SiC MOSFET, and meeting
Greatly increase the power consumption in circuit；Simultaneously as the basic vector face dislocation in SiC material can induce due to the work of PN junction
Fault, therefore, using its internal PN junction diode to make anti-paralleled diode can affect the reliability of device.Use SiC MOSFET
During device, it is generally required in its outer counter parallel connection SiC Schottky diode, but so can increase the cost of manufacture of device.
Summary of the invention
The purpose of this utility model is to provide the carborundum trench MOSFET of a kind of integrated schottky device, overcomes prior art
The drawbacks described above existed, by introducing Schottky diode in groove-shaped SiC MOSFET, when device works, plays afterflow
The effect of diode, improves efficiency and the reliability of circuit work, reduces circuit production cost.
In order to achieve the above object, this utility model is by the following technical solutions:
A kind of SiC trench MOSFET device of integrated schottky diode, described device includes:
1) trench MOSFET:
N+ substrate and N-drift layer thereon, described N-drift layer comprises the p-well having N+ source region being isolated from each other；
U-shaped raceway groove outside described p-well, described U-shaped channel surface has oxide layer, has grid in it；
It is sealing coat on described grid and part described N+ source region；
Front be source electrode and the back side be drain electrode；
2) Schottky diode: Xiao that the N-drift layer between described p-well in described N-drift layer is formed with described source metal
Te Ji contacts.
First optimal technical scheme of described device, described Schottky diode is fly-wheel diode.
Second optimal technical scheme of described device, the resistivity of described N+ substrate is 0.015～0.02 ohmcm.
3rd optimal technical scheme of described device, the thickness of described N-drift layer is 10～500 μm, and its doping content is
1×1014～5 × 1015cm-3。
4th optimal technical scheme of described device, the distance between described p-well is 1～3 μm, and its well depth is 1～3 μm.
5th optimal technical scheme of described device, width and the degree of depth of described N+ source region are respectively less than described p-well.
6th optimal technical scheme of described device, the degree of depth of described U-shaped raceway groove is 4～10 μm.
7th optimal technical scheme of described device, the thickness of described oxide layer is 50～150 μm.
8th optimal technical scheme of described device, the thickness of described sealing coat is 15～50 μm.
9th optimal technical scheme of described device, described grid is N-shaped or the polysilicon of p-type degeneracy doping.
A kind of manufacture method of the SiC trench MOSFET device of described integrated schottky diode, described method include as
Lower step:
1) making mask on N+ substrate epitaxial N-drift layer surface the most graphical, implanted dopant forms p-well；
2) making mask on described p-well surface the most graphical, doping forms N+ source region；
3) making mask on described N-drift layer the most graphical, etching SiC forms U-shaped raceway groove；
4) in described raceway groove inner surface deposited oxide layer；
5) in the described raceway groove with oxide layer, fill polysilicon poly, form grid；
6) in described grid and part described N+ source region, sealing coat is deposited；
7) deposit metal in described drift layer front and described substrate back, form source electrode and drain electrode respectively.
With immediate prior art ratio, this utility model has the advantages that
1) source electrode of this utility model carborundum trench MOSFET forms Schottky contacts, shape with epitaxial layer between p-well
The Schottky diode become, when device works, plays the effect of fly-wheel diode, improves efficiency and the reliability of circuit work；
2) when the PN junction during integrated device of the present utility model avoids SiC MOSFET is as fly-wheel diode, SiC PN
The problem that the knot circuit conversion efficiency that causes of cut-in voltage height is low；
3) SiC Schottky diode of the present utility model is unipolar device, it is to avoid the BPD dislocation caused during PN junction work
Increase, the problem that device reliability reduces；
4) SiC Schottky diode of the present utility model and the integrated preparation of SiC MOSFET, reduce the material of element manufacturing
Material and process costs.
Accompanying drawing explanation
Fig. 1: IGBT with the antiparallel circuit diagram of diode；
The profile of N-drift layer is formed on Fig. 2: N+ substrate；
Fig. 3: N-drift layer ion implanting forms the profile of p-well；
Fig. 4: in p-well, ion implanting forms the profile of N+ source region；
Fig. 5: outside p-well, etching forms the profile of U-shaped raceway groove；
Fig. 6: trench bottom and sidewall form the profile of oxide-film；
The profile of polysilicon poly is filled in Fig. 7: raceway groove；
The profile of layer deposited isolating on Fig. 8: N-drift layer；
Fig. 9: the profile after lithographic section sealing coat；
Figure 10: front deposition metal forms the profile of source electrode；
Figure 11: backside deposition metal forms the profile of drain electrode.
Detailed description of the invention
Being described in detail this utility model below in conjunction with example, this utility model is not limited to this specific embodiment, this
General replacement known to skilled person is also covered by protection domain of the present utility model.
Embodiment 1
First on N+ substrate, extension generates N-drift layer, and the thickness of this drift layer is 12 μm, and doping content is 2 × 1015cm-3。
The resistivity of N+ substrate is 0.015-0.02 ohmcm.
Then the mask plate on N-drift layer makes the figure needing doping by lithography, carries out the ion implantation technology of p-well, each p-well
Between distance be 1 μm, p-well is 1 μm deeply.This part is used for forming Schottky contacts with metal.
Then, utilizing mask plate to make N+ source region figure by lithography, carry out the ion implantation technology of N+ source region, the degree of depth of N+ source region is little
In p-well, being 0.5 μm, width is again smaller than p-well.
Then, utilize mask plate to make grid groove (U-shaped raceway groove) figure by lithography, use reactive ion etching (RIE) or inductively
Plasma etching (ICP) forms groove, channel depth 5 μm.
Then, forming oxide-film at channel bottom and sidewall, thickness is 100nm.
Then, in groove, polysilicon poly is filled.
Then, one layer of Si is grown by plasma reinforced chemical vapour deposition (PECVD)3N4As sealing coat, isolate thickness
Degree is 20nm.
Then, by photoetching, other positions except grid and part N+ source region are exposed, as shown in Figure 9.
Then, deposit metal in front, form Schottky contacts, as source electrode.
Finally, deposit metal overleaf, form Ohmic contact, as drain electrode.
Embodiment 2
First on N+ substrate, extension generates N-drift layer, and the thickness of this drift layer is 15 μm. and doping content is 1 × 1015cm-3。
The resistivity of N+ substrate is 0.015-0.02 ohmcm.
Then the mask plate on N-drift layer makes the figure needing doping by lithography, carries out the ion implantation technology of p-well, each p-well
Between distance be 1.5 μm, p-well is 1 μm deeply.This part is used for forming Schottky contacts with metal.
Then, utilizing mask plate to make N+ source region figure by lithography, carry out the ion implantation technology of N+ source region, the degree of depth of N+ source region is little
In p-well, being 0.5 μm, width is again smaller than p-well.
Then, utilize mask plate to make grid groove (U-shaped raceway groove) figure by lithography, use reactive ion etching (RIE) or inductively
Plasma etching (ICP) forms groove, channel depth 7 μm.
Then, forming oxide-film at channel bottom and sidewall, thickness is 100nm.
Then, in groove, polysilicon poly is filled.
Then, plasma reinforced chemical vapour deposition (PECVD) grows one layer of Si3N4As sealing coat, separation layer thickness is
30nm。
Then, by photoetching, other positions except grid and part N+ source region are exposed, as shown in Figure 9.
Then, deposit metal in front, form Schottky contacts, as source electrode.
Finally, deposit metal overleaf, form Ohmic contact, as drain electrode.
Embodiment 3
First on N+ substrate, extension generates N-drift layer, and the thickness of this drift layer is 50 μm, and doping content is 8 × 1014cm-3。
The resistivity of N+ substrate is 0.015-0.02 ohmcm.
Then the mask plate on N-drift layer makes the figure needing doping by lithography, carries out the ion implantation technology of p-well, each p-well
Between distance be 1.5 μm, p-well is 1.5 μm deeply.This part is used for forming Schottky contacts with metal.
Then, utilizing mask plate to make N+ source region figure by lithography, carry out the ion implantation technology of N+ source region, the degree of depth of N+ source region is little
In p-well, being 0.5 μm, width is again smaller than p-well.
Then, utilize mask plate to make grid groove (U-shaped raceway groove) figure by lithography, use reactive ion etching (RIE) or inductively
Plasma etching (ICP) forms groove, channel depth 10 μm.
Then, forming oxide-film at channel bottom and sidewall, thickness is 100nm.
Then, in groove, polysilicon poly is filled.
Then, plasma reinforced chemical vapour deposition (PECVD) grows one layer of Si3N4As sealing coat, separation layer thickness is
20nm。
Then, by photoetching, other positions except grid and part N+ source region are exposed, as shown in Figure 9.
Then, deposit metal in front, form Schottky contacts, as source electrode.
Finally, deposit metal overleaf, form Ohmic contact, as drain electrode.
Embodiment 4
First on N+ substrate, extension generates N-drift layer, and the thickness of this drift layer is 100 μm, and doping content is 5 × 1014cm-3。
The resistivity of N+ substrate is 0.015-0.02 ohmcm.
Then the mask plate on N-drift layer makes the figure needing doping by lithography, carries out the ion implantation technology of p-well, each p-well
Between distance be 2 μm, p-well is 2 μm deeply.This part is used for forming Schottky contacts with metal.
Then, utilizing mask plate to make N+ source region figure by lithography, carry out the ion implantation technology of N+ source region, the degree of depth of N+ source region is little
In p-well, being 0.5 μm, width is again smaller than p-well.
Then, utilize mask plate to make grid groove (U-shaped raceway groove) figure by lithography, use reactive ion etching (RIE) or inductively
Plasma etching (ICP) forms groove, channel depth 10 μm.
Then, forming oxide-film at channel bottom and sidewall, thickness is 100nm.
Then, in groove, polysilicon poly is filled.
Then, plasma reinforced chemical vapour deposition (PECVD) grows one layer of Si3N4As sealing coat, separation layer thickness is
20nm。
Then, by photoetching, other positions except grid and part N+ source region are exposed, as shown in Figure 9.
Then, deposit metal in front, form Schottky contacts, as source electrode.
Finally, deposit metal overleaf, form Ohmic contact, as drain electrode.
Embodiment 5
First on N+ substrate, extension generates N-drift layer, and the thickness of this drift layer is 112 μm, and doping content is 7 × 10-14cm-3。
The resistivity of N+ substrate is 0.015-0.02 ohmcm.
Then the mask plate on N-drift layer makes the figure needing doping by lithography, carries out the ion implantation technology of p-well, each p-well
Between distance be 1.5 μm, p-well is 2 μm deeply.This part is used for forming Schottky contacts with metal.
Then, utilizing mask plate to make N+ source region figure by lithography, carry out the ion implantation technology of N+ source region, the degree of depth of N+ source region is little
In p-well, being 0.5 μm, width is again smaller than p-well.
Then, utilize mask plate to make grid groove (U-shaped raceway groove) figure by lithography, use reactive ion etching (RIE) or inductively
Plasma etching (ICP) forms groove, channel depth 10 μm.
Then, forming oxide-film at channel bottom and sidewall, thickness is 100nm.
Then, in groove, polysilicon poly is filled.
Then, plasma reinforced chemical vapour deposition (PECVD) grows one layer of Si3N4As sealing coat, separation layer thickness is
20nm。
Then, by photoetching, other positions except grid and part N+ source region are exposed, as shown in Figure 9.
Then, deposit metal in front, form Schottky contacts, as source electrode.
Finally, deposit metal overleaf, form Ohmic contact, as drain electrode.
Finally should be noted that: above example only in order to illustrate that the technical solution of the utility model is not intended to limit, although
Being described in detail this utility model with reference to above-described embodiment, those of ordinary skill in the field are it is understood that still
Detailed description of the invention of the present utility model can be modified or equivalent, and without departing from this utility model spirit and scope
Any amendment or equivalent, it all should be contained in the middle of right of the present utility model.
Claims (10)
1. the SiC trench MOSFET device of an integrated schottky diode, it is characterised in that described device includes:
Trench MOSFET:
N+ substrate and N-drift layer thereon, described N-drift layer comprises the p-well having N+ source region being isolated from each other；
U-shaped raceway groove outside described p-well, described U-shaped channel surface has oxide layer, has grid in it；
It is sealing coat on described grid and part described N+ source region；
Front be source electrode and the back side be drain electrode；
Schottky diode: the Schottky contacts that the N-drift layer between described p-well in described N-drift layer is formed with described source metal.
The SiC trench MOSFET device of a kind of integrated schottky diode the most according to claim 1, it is characterised in that described Schottky diode is fly-wheel diode.
The SiC trench MOSFET device of a kind of integrated schottky diode the most according to claim 1, it is characterised in that the resistivity of described N+ substrate is 0.015～0.02 ohmcm.
The SiC trench MOSFET device of a kind of integrated schottky diode the most according to claim 1, it is characterised in that the thickness of described N-drift layer is 10～500 μm, its doping content is 1 × 1014～5 × 1015cm-3。
The SiC trench MOSFET device of a kind of integrated schottky diode the most according to claim 1, it is characterised in that the distance between described p-well is 1～3 μm, its well depth is 1～3 μm.
The SiC trench MOSFET device of a kind of integrated schottky diode the most according to claim 1, it is characterised in that width and the degree of depth of described N+ source region are respectively less than described p-well.
The SiC trench MOSFET device of a kind of integrated schottky diode the most according to claim 1, it is characterised in that the degree of depth of described U-shaped raceway groove is 4～10 μm.
The SiC trench MOSFET device of a kind of integrated schottky diode the most according to claim 1, it is characterised in that the thickness of described oxide layer is 50～150 μm.
The SiC trench MOSFET device of a kind of integrated schottky diode the most according to claim 1, it is characterised in that the thickness of described sealing coat is 15～50 μm.
The SiC trench MOSFET device of a kind of integrated schottky diode the most according to claim 1, it is characterised in that described grid is N-shaped or the polysilicon of p-type degeneracy doping.
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| CN201521141019.4U CN205595339U (en) | 2015-12-31 | 2015-12-31 | Integrated schottky diode's siC ditch cell type MOSFET device |
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| CN201521141019.4U CN205595339U (en) | 2015-12-31 | 2015-12-31 | Integrated schottky diode's siC ditch cell type MOSFET device |
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| CN205595339U true CN205595339U (en) | 2016-09-21 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2017114113A1 (en) * | 2015-12-31 | 2017-07-06 | 全球能源互联网研究院 | Sic trench mosfet device for integrating schottky diode, and manufacturing method thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2017114113A1 (en) * | 2015-12-31 | 2017-07-06 | 全球能源互联网研究院 | Sic trench mosfet device for integrating schottky diode, and manufacturing method thereof |
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