CN111129132B - A kind of IGBT device - Google Patents

Abstract

The invention provides an IGBT device, which comprises: the collector electrode metal layer, the P+ region, the N' region and the N-region are sequentially arranged from bottom to top, step-type grooves are formed in the top of the N-region, and groove gates and plane gates are formed on different steps of the grooves. Compared with a groove type IGBT device with a single structure, the groove type IGBT device has the advantages that two grid structures of a groove grid and a plane grid are combined, so that two working mechanisms of the plane grid IGBT and the groove grid IGBT are provided. The gate oxidation process of the planar gate IGBT section and the trench gate IGBT section may be completed simultaneously, and may have the same gate oxide thickness.

Description

A kind of IGBT device

Technical field

The present invention relates to semiconductor devices, in particular to an IGBT device.

Background technique

Insulated gate bipolar transistor (IGBT) is the most eye-catching and rapidly developing new power electronic device in recent years. IGBT devices have the characteristics of high gate input impedance and wide safe operating area when turning on and off. Therefore, IGBT devices are widely used in motor drives, welding machines, induction cookers, UPS power supplies, etc.

Currently, planar IGBT devices and trench IGBT devices are widely used. Planar gate IGBT has good gate oxide layer quality and simpler manufacturing process; while trench gate IGBT has lower on-resistance, which optimizes the conflicting relationship between IGBT's on-resistance and turn-off speed. Trench gate trench etching The rear surface is rough and damaged, which will affect the mobility of carriers. In addition, the trench gate has a large gate capacitance, which weakens its short-circuit capability. At this stage, there is no structure to combine the two.

Contents of the invention

In view of the above technical problems existing in the prior art, the present invention proposes an IGBT device, which includes: a collector metal layer, a P+ region, an N' region and an N- region arranged sequentially from bottom to top. A step-shaped trench is formed on the top, and trench gates and planar gates are formed on different steps of the trench.

In one embodiment, the trench gate includes: a first gate oxide layer formed in the trench, a first P base region disposed outside the first gate oxide layer, side surfaces of the first P base region and the first Gate oxide layer contact, a first N+ source region disposed on the top of the first P base region and in contact with the first gate oxide layer, a first P+ ohmic contact region disposed on one side of the first N+ source region, The first P+ ohmic contact region is not in contact with the gate oxide layer.

In one embodiment, the planar gate includes: a second gate oxide layer formed in the trench, a second P base region disposed under the second gate oxide layer, the top of the second P base region and the second gate The anode oxide layer contacts, the second N+ source region is disposed on the top of the second P base region and is flush with the top edge of the second gate oxide layer, and the second P+ ohm is disposed on one side of the second N+ source region. The contact area, the second P+ ohmic contact area is not in contact with the second gate oxide layer.

In one embodiment, the bottom surface of the first N+ source region is no higher than the top surface of the first gate oxide layer.

In one embodiment, the top surface of the first P+ ohmic contact region is flush with the top surface of the first N+ source region, or the top surface of the first P+ ohmic contact region is lower than the top surface of the first N+ source region.

In one embodiment, the top surface of the second P+ ohmic contact region is flush with the top surface of the second N+ source region, or the top surface of the second P+ ohmic contact region is lower than the top surface of the second N+ source region, The first gate oxide layer and the second gate oxide layer have an integrated structure.

In one embodiment, the IGBT device further includes an N hole blocking region disposed between the N-region and the first P base region or an N hole blocking region disposed between the N- region and the second P base region. any one or combination thereof.

In one embodiment, the IGBT device further includes a polysilicon layer formed over the second gate oxide layer, the top surface of the polysilicon layer being no lower than the top surface of the first N+ source region.

In one embodiment, a first isolation oxide layer is formed above the polysilicon layer, and a second isolation oxide layer is formed on the side of the polysilicon layer. The first isolation oxide layer covers a portion of the top surface of the first N+ source region, and the second isolation oxide layer covers a portion of the top surface of the first N+ source region. An isolation oxide layer covers a portion of the top surface of the second N+ source region.

In one embodiment, the IGBT device further includes an emissive metal layer, the emissive metal layer is connected to the top surface of the first P+ ohmic contact region, the top surface of the first N+ source region, the top surface of the second P+ ohmic contact region and the second The top surfaces of the N+ source regions are in contact with each other, and the first isolation oxide layer and the second isolation oxide layer have an integrated structure.

Compared with the existing technology, the advantage of the present invention is that compared with a single-structure trench IGBT device or a single-structure planar IGBT device, this device combines two gate structures: a trench gate and a planar gate. Therefore, It has two working mechanisms: planar gate IGBT and trench gate IGBT. The gate oxidation process of the planar gate IGBT part and the trench gate IGBT part can be completed at the same time, and they can have the same gate oxide layer thickness.

Description of the drawings

The preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings, in which:

Figure 1 shows a cross-sectional view of a trench gate IGBT structure in the prior art.

Figure 2 shows a cross-sectional view of a planar gate IGBT structure in the prior art.

Figure 3 shows a cross-sectional view of the IGBT structure according to Embodiment 1 of the present invention.

Figure 4 shows a cross-sectional view of the IGBT structure of Embodiment 2 of the present invention.

Figure 5 shows a cross-sectional view of the IGBT structure of Embodiment 3 of the present invention.

In the drawings, like parts are provided with the same reference numerals, and the drawings are not drawn to actual scale.

Detailed ways

The present invention will be further described below in conjunction with the accompanying drawings.

As shown in Figure 1, the existing trench type IGBT structure includes a collector metal layer 114, a P+ region 112, an N' region 111, an N- region 101 and a stepped trench arranged in sequence from bottom to top. A polysilicon layer is provided in the trench. A P base region 104 is provided on the side of the trench. A gate oxide layer 102 is provided at the bottom of the trench and on the side surface close to the P base region 104 . An N+ source region 105 is provided on the top side of the P base region 104 close to the trench. A P+ ohmic contact region 106 is provided on the top side of the P base region 104 away from the trench. An isolation oxide layer 110 is provided on top of the polysilicon. An emitter metal layer 113 is provided on top of the isolation oxide layer 110 , N+ source region 105 and P+ ohmic contact region 106 . When a voltage exceeding the threshold is applied to the gate electrode, a large number of electrons are gathered in the area of the P base region 104 close to the gate oxide layer 102 to form an electron channel. This channel, the N+ source region 105 and the N- region 101 are both N type, thereby forming an open current path. When the voltage applied to the gate electrode is lower than the threshold, the electron channel there disappears, and the P base region 104 forms a barrier to prevent the communication of electrons in the N+ source region 105 and N- region 101, and the IGBT enters the shutdown process until it is turned off. Finish. In the trench gate IGBT structure, electrons flow from the emitter to the collector, and the current direction is opposite. The flow is vertical in the channel near the gate oxide. Figure 1 is the smallest functional unit of the existing trench IGBT. By mirroring the structure along the right edge of Figure 1 to the right, the complete cell structure of the trench IGBT can be obtained.

As shown in Figure 2, the overall structure of the planar IGBT structure in the prior art is similar to that of the trench type. The biggest difference lies in the placement of the P base region 107, P+ ohmic contact region 109, and N+ source region 108. Different from groove type. The P base region, P+ ohmic contact region 109, and N+ source region 108 of the trench gate are all located on the side of the polysilicon gate, while the P base region 107, P+ ohmic contact region 109, and N+ source region 108 of the planar gate are all located on the polysilicon gate. bottom of. Their current switching principles are the same. When a voltage higher than the threshold is applied to the gate, the current passes through the electron channel between the P base region 107 and the gate oxide layer 102 and the N+ source region to the emitter metal, forming an open current path, otherwise its path is closed. At this time, the direction of the current is horizontally through the planar gate and flows out from the emitter. Figure 2 is the smallest functional unit of the existing planar IGBT. By mirroring along the left edge of the structure in Figure 2 to the left, the complete cell structure of the planar IGBT can be obtained.

Embodiment 1

The composite IGBT structure in the present invention combines two structures: planar gate and trench gate. Specifically, as shown in Figure 3, the IGBT device of this embodiment includes: a collector metal layer 114, a P+ region 112, an N' region 111, and an N- region 101 arranged in sequence from bottom to top. Among them, a step-shaped trench is formed on the top of the N-region 101. The step sides and bottom of the trench form a trench gate and a planar gate respectively.

Specifically, the trench gate includes a first gate oxide layer 102a. A first P base region 104 and a first N+ source region 105 are also provided outside the first gate oxide layer 102a. The side surface of the first P base region 104 is in contact with the first gate oxide layer 102a. The side surface of the first N+ source region 105 is in contact with the first gate oxide layer 102a. And the first N+ source regions 105 are located on the top surface of the first P base region 104 . A first P+ ohmic contact region 106 is also provided outside the first N+ source region 105 . In this embodiment, the top surfaces of the first P+ ohmic contact region 106 and the first N+ source region 105 are flush with the top surface of the first gate oxide layer 102a. At the same time, the first P+ ohmic contact region 106 is on top of the first P base region 104 and is tightly surrounded by the first P base region 104 . And the first P+ ohmic contact region 106 is not in contact with the first gate oxide layer 102a.

Preferably, the bottom surface of the first N+ source region 105 is not higher than the top surface of the first gate oxide layer 102a. As a result, the side surface of the first N+ source region 105 is in contact with the first gate oxide layer 102a. Furthermore, the first P+ ohmic contact region 106 is not in contact with the first gate oxide layer 102a. The first P base region 104 is located at the junction of the first gate oxide layer 102a and the N- drift region 101 and extends below the first P+ ohmic contact region 106, and connects the first N+ source region 105 with the first P+ ohmic contact region 106. The contact area 106 is tightly surrounded. When the gate electrode applies a voltage exceeding the threshold to the emitter E, an electron channel is formed. The side surface of the first P base region 104 is in contact with the first gate oxide layer 102a, and the electron channel formed at this time is N-type. Only when the top surfaces of the first N+ source region 105 and the first P base region 104 are lower than the top surface of the first gate oxide layer 102a can electrons be gathered near the first gate oxide layer 102a to ensure that electrons A channel is formed and the current flows smoothly.

The planar gate includes a second gate oxide layer 102b, and a second P base region 107 and a second N+ source region 108 are also provided at the bottom of the second gate oxide layer 102b. The top surface of the second P base region 107 is in contact with the bottom surface of the second gate oxide layer 102b. The top surface of the second N+ source region 108 is also in contact with the bottom surface of the second gate oxide layer 102b. And the second N+ source region 108 is provided on the top surface of the second P base region 107 . A second P+ ohmic contact region 109 is also provided outside the second N+ source region 108 . In this embodiment, the top surfaces of the second P+ ohmic contact region 109 and the second N+ source region 108 are flush with the top surface of the second gate oxide layer 102b. At the same time, the second P+ ohmic contact region 109 is on top of the second P base region 107 and is tightly surrounded by the second P base region 107 . And the second P+ ohmic contact region 109 is not in contact with the second gate oxide layer 102b. Furthermore, the second P+ ohmic contact region 109 is not in contact with the second gate oxide layer 102b.

The second P base region 107 is located at the junction of the second gate oxide layer 102b and the N region 101 and extends below the second P+ ohmic contact region 109, and connects the second N+ source region 108 with the second P+ ohmic contact region. 109 tightly surrounded. When the gate electrode applies a voltage exceeding the threshold to the emitter E, an electron channel is formed. The top surface of the second P base region 107 is in contact with the second gate oxide layer 102b, and the electron channel formed at this time is N-type. Only when the top surfaces of the second N+ source region 108 and the second P base region 107 are in contact with the bottom surface of the second gate oxide layer 102b can electrons be gathered near the second gate oxide layer 102b to ensure that the electrons A channel is formed and the current flows smoothly.

An emitter metal layer 113 is disposed over the first N+ source region 105 , the first P+ ohmic contact region 106 , the second N+ source region 108 , the second P=ohmic contact region 109 and the polysilicon layer 103 . A first isolation oxide layer 110a and a second isolation oxide layer 110b are also provided between the polysilicon layer 103 and the emission metal layer 113. The first isolation oxide layer 110a and the second isolation oxide layer 110b have an integrated structure. Among them, the first isolation oxide layer 110a is provided on the top surface of the polysilicon layer 103. The second isolation oxide layer 110b is provided on the side of the polysilicon 103. The first isolation oxide layer 110a covers a portion of the top surface of the first N+ source region 105, and the second isolation oxide layer 110b covers a portion of the top surface of the second N+ source region 108. In this embodiment, the emission metal layer 113 is connected to the top surface of the first P+ ohmic contact region 106, the top surface 105 of the first N+ source region, the top surface of the second P+ ohmic contact region 109 and the second N+ source region 108. The top surfaces are in contact.

When making a step-shaped trench on the top of the N-region, first dig a trench on the top of the N-region 101, etch the corresponding groove shape, and oxidize to form the gate oxide layer 102. Then, a gate polysilicon layer 103 is disposed on the gate oxide layer 102, and an isolation oxide layer 110 is formed on the polysilicon layer 103. The isolation oxide layer 110 is used to electrically isolate the polysilicon layer 103 from outer layers. Among them, the polysilicon layer 103 is generally filled with polysilicon material. The gate oxide layer 102 includes a second gate oxide layer 102a and a first gate oxide layer 102b. The isolation oxide layer 110 includes a first isolation oxide layer 110a and a second isolation oxide layer 110b.

The IGBT device in this embodiment combines two gate structures, a trench gate and a planar gate, and therefore has two working mechanisms: a planar gate IGBT and a trench gate IGBT. Moreover, the gate oxidation process of the planar gate IGBT part and the trench gate IGBT part can be completed at the same time, and they can have the same gate oxide layer thickness, which simplifies the manufacturing process and improves the yield.

Embodiment 2

In a preferred embodiment, as shown in FIG. 4 , based on Embodiment 1, an N hole blocking region 122 can be provided between the N-region 101 and the P base region 107 and P base region 104 . Arranging the N hole blocking region 122 at the bottom of the P base region can effectively improve the carrier injection level when the IGBT current is turned on, reduce the on-resistance, and reduce the conduction loss. In specific applications, the N hole blocking region can be set at the bottom of any P base region according to the actual situation, or the N hole blocking region 122 can be set at the bottom of two P base regions at the same time.

Embodiment 3

In one embodiment, the top of the P+ ohmic contact area is set downward. As shown in FIG. 5 , the top of the first P+ ohmic contact region 106 is lower than the first N+ source region 105 , and the top of the second P+ ohmic contact region 109 is lower than the second N+ source region 108 . Similarly, in such a structure, when the gate electrode applies a voltage exceeding the threshold to the emitter E, the electron channel can also be successfully formed in the thin layer on the side of the P base region close to the gate oxide layer.

In particular, such an arrangement can facilitate etching operations. The etching and doping of the P+ ohmic contact area is the last processing process in the silicon body on the emitter side. Its doping depth is mainly controlled by ion implantation. In order to prevent the P-type impurities injected into the P+ ohmic contact area from interfering with the N+ source area. To compensate for the N-type doping and reduce the effective P-type concentration, you can achieve better implantation effects by etching away the N+ source region, simultaneously reducing the position of the P+ ohmic contact region, and then injecting P+ ions.

Embodiment 4

In a new embodiment, the original N-type doping region in the trench gate IGBT device of the above-mentioned Embodiment 1, 2, and 3 is replaced with a P-type doping region. The area is replaced by an N-type doped area. This will convert the channel type of the original trench gate IGBT device from N channel to P channel. This replacement only involves changes in doping type, and the relative size of the doping concentration remains unchanged. For example, P is replaced by N, P+ is replaced by N+, N- is replaced by P-, N is replaced by P, N′ is replaced by P′, N+ Replace with P+. Such conversion can also achieve the technical effects of the present invention.

In the above-mentioned embodiments and corresponding drawings, only the minimum functional unit of the present invention is shown. By mirroring the rightmost boundary of the structure of each drawing to the right, a new minimum functional unit that conforms to the content of the present invention can be obtained. By mirroring the leftmost boundary of the structure of each drawing to the left, a new minimum functional unit that conforms to the content of the present invention can be obtained with the same mirroring operation on the right as described above. Therefore, the terms "left" and "right" in this specification are only for the structure of the drawings. If a mirror image is used, the expressions "left" and "right" are interchangeable and do not limit the content of the present invention.

The above are only preferred embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily make changes or changes within the technical scope disclosed in the present invention, and such changes or changes All are covered by the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.

Claims (8)

1. An IGBT device, comprising: the collector comprises a collector metal layer, a P+ region, an N' region and an N-region which are sequentially arranged from bottom to top, wherein a step-type groove is formed at the top of the N-region, and groove gates and plane gates are formed on different steps of the groove;

the trench gate includes:

a first gate oxide layer formed within the trench,

the first P base region is arranged outside the first gate oxide layer, the side surface of the first P base region is contacted with the first gate oxide layer,

a first N+ source region disposed on top of the first P base region and in contact with the first gate oxide layer,

the first P+ ohmic contact region is arranged on one side of the first N+ source electrode region, and the first P+ ohmic contact region is not contacted with the gate oxide layer;

the planar gate includes:

a second gate oxide layer formed within the trench,

a second P base region arranged below the second gate oxide layer, the top of the second P base region is contacted with the gate oxide layer,

a second N+ source region disposed on top of the second P base region and flush with a top edge of the second gate oxide layer,

and the second P+ ohmic contact region is arranged at one side of the second N+ source electrode region, and the second P+ ohmic contact region is not contacted with the gate oxide layer.

2. The IGBT device of claim 1 wherein: the bottom surface of the first N+ source region is not higher than the top surface of the first gate oxide layer.

3. The IGBT device of claim 1 wherein: the top surface of the first P+ ohmic contact region is flush with the top surface of the first N+ source region, or the top surface of the first P+ ohmic contact region is lower than the top surface of the first N+ source region.

4. The IGBT device of claim 1 wherein the top surface of the second p+ ohmic contact region is level with the top surface of the second n+ source region or the top surface of the second p+ ohmic contact region is lower than the top surface of the second n+ source region.

5. The IGBT device of claim 1 further comprising any one or a combination of an N hole blocking region disposed between the trench and the first P base region or an N hole blocking region disposed between the trench and the second P base region.

6. The IGBT device of claim 1, wherein,

the IGBT device further comprises a polysilicon layer formed above the second gate oxide layer, wherein the top surface of the polysilicon layer is not lower than the top surface of the first N+ source region.

7. The IGBT device of claim 6 wherein the polysilicon layer is formed with a first isolation oxide layer over the polysilicon layer, the polysilicon layer is formed with a second isolation oxide layer on a side surface, the first isolation oxide layer covers a portion of the top surface of the first n+ source region, the second isolation oxide layer covers a portion of the top surface of the second n+ source region, and the first isolation oxide layer and the second isolation oxide layer are of unitary construction.

8. The IGBT device of claim 7 further comprising a metal emitter layer in contact with the top surface of the first p+ ohmic contact region, the top surface of the first n+ source region, the top surface of the second p+ ohmic contact region, and the top surface of the second n+ source region.