CN111129132B - IGBT device - Google Patents
IGBT device Download PDFInfo
- Publication number
- CN111129132B CN111129132B CN201811277607.9A CN201811277607A CN111129132B CN 111129132 B CN111129132 B CN 111129132B CN 201811277607 A CN201811277607 A CN 201811277607A CN 111129132 B CN111129132 B CN 111129132B
- Authority
- CN
- China
- Prior art keywords
- region
- oxide layer
- top surface
- ohmic contact
- gate oxide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000002184 metal Substances 0.000 claims abstract description 12
- 238000002955 isolation Methods 0.000 claims description 27
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 22
- 229920005591 polysilicon Polymers 0.000 claims description 22
- 230000000903 blocking effect Effects 0.000 claims description 8
- 238000010276 construction Methods 0.000 claims 1
- 230000003647 oxidation Effects 0.000 abstract description 13
- 238000007254 oxidation reaction Methods 0.000 abstract description 13
- 238000000034 method Methods 0.000 abstract description 4
- 230000008569 process Effects 0.000 abstract description 4
- 230000007246 mechanism Effects 0.000 abstract description 3
- 238000005530 etching Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Classifications
-
- H01L29/7397—
-
- H01L29/42356—
-
- H01L29/4236—
-
- H01L29/66348—
Landscapes
- Electrodes Of Semiconductors (AREA)
Abstract
The invention provides an IGBT device, which comprises: the collector electrode metal layer, the P+ region, the N' region and the N-region are sequentially arranged from bottom to top, step-type grooves are formed in the top of the N-region, and groove gates and plane gates are formed on different steps of the grooves. Compared with a groove type IGBT device with a single structure, the groove type IGBT device has the advantages that two grid structures of a groove grid and a plane grid are combined, so that two working mechanisms of the plane grid IGBT and the groove grid IGBT are provided. The gate oxidation process of the planar gate IGBT section and the trench gate IGBT section may be completed simultaneously, and may have the same gate oxide thickness.
Description
Technical Field
The present invention relates to semiconductor devices, and more particularly to an IGBT device.
Background
Insulated Gate Bipolar Transistors (IGBTs) are the most attractive and fast developing new power electronics in recent years. The IGBT device has the characteristics of high input impedance of a grid electrode, wider safe working area when being switched on and off, and the like, so that the IGBT device has wide application in the aspects of motor drive, electric welding machines, induction cookers, UPS power supplies and the like.
The planar IGBT device and the trench IGBT device are widely used at present. The planar gate type IGBT gate oxide layer has good quality and simpler manufacturing process; the trench gate IGBT has lower on-resistance, so that the contradiction relation between the on-resistance and the off-speed of the IGBT is optimized, the etched surface of the trench gate is rough, the damage is large, and the mobility of carriers can be influenced. In addition, the gate capacitance of the trench gate is large, and the short circuit capability of the trench gate is weakened. There is no structure for combining the two at this stage.
Disclosure of Invention
In order to solve the above technical problems in the prior art, the present invention provides an IGBT device, which includes: the collector electrode metal layer, the P+ region, the N' region and the N-region are sequentially arranged from bottom to top, step-type grooves are formed in the top of the N-region, and groove gates and plane gates are formed on different steps of the grooves.
In one embodiment, a trench gate includes: the first grid electrode oxidation layer is formed in the groove, the first P base region is arranged on the outer side of the first grid electrode oxidation layer, the side face of the first P base region is in contact with the first grid electrode oxidation layer, the first N+ source region is arranged on the top of the first P base region and in contact with the first grid electrode oxidation layer, the first P+ ohmic contact region is arranged on one side of the first N+ source region, and the first P+ ohmic contact region is not in contact with the grid electrode oxidation layer.
In one embodiment, a planar gate includes: the second grid electrode oxidation layer is formed in the groove, the second P base region is arranged below the second grid electrode oxidation layer, the top of the second P base region is in contact with the second grid electrode oxidation layer, the second N+ source region is arranged on the top of the second P base region and is flush with the top edge of the second grid electrode oxidation layer, the second P+ ohmic contact region is arranged on one side of the second N+ source region, and the second P+ ohmic contact region is not in contact with the second grid electrode oxidation layer.
In one embodiment, a bottom surface of the first n+ source region is not higher than a top surface of the first gate oxide layer.
In one embodiment, the top surface of the first p+ ohmic contact region is flush with the top surface of the first n+ source region or the top surface of the first p+ ohmic contact region is lower than the top surface of the first n+ source region.
In one embodiment, the top surface of the second p+ ohmic contact region is flush with the top surface of the second n+ source region, or the top surface of the second p+ ohmic contact region is lower than the top surface of the second n+ source region, and the first gate oxide layer and the second gate oxide layer are in an integral structure.
In one embodiment, the IGBT device further includes any one of or a combination of an N hole blocking region disposed between the N-region and the first P base region, or an N hole blocking region disposed between the N-region and the second P base region.
In one embodiment, the IGBT device further includes a polysilicon layer formed over the second gate oxide layer, a top surface of the polysilicon layer not lower than a top surface of the first n+ source region.
In one embodiment, a first isolation oxide layer is formed over the polysilicon layer, a second isolation oxide layer is formed on a side of the polysilicon layer, the first isolation oxide layer covers a portion of the top surface of the first n+ source region, and the second isolation oxide layer covers a portion of the top surface of the second n+ source region.
In one embodiment, the IGBT device further includes an emitter metal layer in contact with the top surface of the first p+ ohmic contact region, the top surface of the first n+ source region, the top surface of the second p+ ohmic contact region, and the top surface of the second n+ source region, the first isolation oxide layer and the second isolation oxide layer being of unitary structure.
Compared with the prior art, the device has the advantages that compared with a groove type IGBT device with a single structure or a plane type IGBT device with a single structure, the device combines two grid structures of a groove grid and a plane grid, so that the device has two working mechanisms of the plane grid IGBT and the groove grid IGBT. The gate oxidation process of the planar gate IGBT section and the trench gate IGBT section may be completed simultaneously, and may have the same gate oxide thickness.
Drawings
Preferred embodiments of the present invention will be described in detail below with reference to the attached drawing figures, wherein:
fig. 1 shows a cross-sectional view of a trench gate IGBT structure in the prior art.
Fig. 2 shows a cross-sectional view of a prior art planar gate IGBT structure.
Fig. 3 shows a cross-sectional view of an IGBT structure according to a first embodiment of the invention.
Fig. 4 shows a cross-sectional view of an IGBT structure according to a second embodiment of the invention.
Fig. 5 shows a cross-sectional view of an IGBT structure according to a third embodiment of the invention.
In the drawings, like parts are given like reference numerals, and the drawings are not drawn to scale.
Detailed Description
The invention will be further described with reference to the accompanying drawings.
As shown in fig. 1, the conventional trench IGBT structure includes, from bottom to top, a collector metal layer 114, a p+ region 112, an N' region 111, an N-region 101, and a step trench. A polysilicon layer is disposed in the trench. A P base region 104 is provided at the side of the trench. The bottom of the trench and the side near the P base region 104 are provided with a gate oxide layer 102. An n+ source region 105 is disposed on a side of the top of the P base region 104 close to the trench. A P + ohmic contact region 106 is provided on the top of the P base region 104 on the side remote from the trench. An isolation oxide layer 110 is provided on top of the polysilicon. An emitter metal layer 113 is disposed on top of the isolation oxide layer 110, the n+ source region 105, and the p+ ohmic contact region 106. When a voltage exceeding a threshold value is applied to the gate electrode, a region of the P base region 104 close to the gate oxide layer 102 gathers a large number of electrons to form an electron channel, which is N-type with the n+ source region 105 and the N-region 101, thereby forming an open current path. When the voltage applied to the gate electrode is lower than the threshold value, the electron channel disappears, the P base region 104 forms a barrier, the communication of electrons between the N+ source region 105 and the N-region 101 is prevented, and the IGBT enters the turn-off process until the turn-off is completed. In a trench gate IGBT structure, electrons flow from the emitter to the collector, with the current direction being opposite. Flow is in a vertical direction in the channel near the gate oxide. Fig. 1 is a diagram showing the minimum functional unit of the conventional trench IGBT, and the trench IGBT is mirrored along the right edge of the structure of fig. 1 to obtain a complete cell structure of the trench IGBT.
As shown in fig. 2, the planar IGBT structure in the prior art has a general structure similar to the trench type, and the biggest difference is that the P base region 107, the p+ ohmic contact region 109, and the n+ source region 108 are disposed at different positions from the trench type. The P base region, the p+ ohmic contact region 109, and the n+ source region 108 of the trench gate are all located at the side of the polysilicon gate, and the P base region 107, the p+ ohmic contact region 109, and the n+ source region 108 of the planar gate are all located at the bottom of the polysilicon gate. The on-off principle of the currents is the same, when the voltage higher than the threshold value is applied to the grid electrode, the current reaches the emitter metal through the electron channel between the P base region 107 and the grid electrode oxide layer 102 and the N+ source region, an open current path is formed, and conversely, the path is closed. At this time, the direction of the current is horizontal through the planar gate and out of the emitter. Fig. 2 is a diagram showing the minimum functional unit of a conventional planar IGBT, and the minimum functional unit is mirrored along the left side edge of the structure of fig. 2, so that a complete cell structure of the planar IGBT can be obtained.
Example 1
The composite IGBT structure combines two structures of a planar gate and a trench gate. Specifically, as shown in fig. 3, the IGBT device of the present embodiment includes: collector metal layer 114, p+ region 112, N' region 111, N-region 101 are disposed in this order from bottom to top. Wherein a stepped trench is formed on top of N-region 101. The step sides and bottom of the trench form a trench gate and a planar gate, respectively.
Specifically, the trench gate includes a first gate oxide layer 102a. A first P base region 104 and a first n+ source region 105 are further provided outside the first gate oxide layer 102a. The side of the first P base region 104 is in contact with the first gate oxide layer 102a. The side of the first n+ source region 105 is in contact with the first gate oxide layer 102a. And the first n+ source regions 105 are all disposed on the top surface of the first P base region 104. A first p+ ohmic contact region 106 is further provided outside the first n+ source region 105. In the present embodiment, the top surfaces of the first p+ ohmic contact region 106 and the first n+ source region 105 are flush with the top surface of the first gate oxide layer 102a. Meanwhile, the first p+ ohmic contact region 106 is on top of the first P base region 104 and is tightly surrounded by the first P base region 104. And the first p+ ohmic contact region 106 is not in contact with the first gate oxide layer 102a.
Preferably, the bottom surface of the first n+ source region 105 is not higher than the top surface of the first gate oxide layer 102a. Thereby, the side surface of the first n+ source region 105 is in contact with the first gate oxide layer 102a. And, the first p+ ohmic contact region 106 is not in contact with the first gate oxide layer 102a. The first P base region 104 is located at the interface between the first gate oxide layer 102a and the N-drift region 101 and extends to below the first p+ ohmic contact region 106, and tightly surrounds the first n+ source region 105 and the first p+ ohmic contact region 106. When a voltage exceeding a threshold is applied to the emitter E by the gate electrode, an electron channel is formed. The side surface of the first P base region 104 contacts the first gate oxide layer 102a, and the electron channel formed at this time is N-type. Only when the top surfaces of the first n+ source region 105 and the first P base region 104 are lower than the top surface of the first gate oxide layer 102a, electrons can be collected near the first gate oxide layer 102a, so that the formation of an electron channel is ensured, and the current is smooth.
The planar gate includes a second gate oxide layer 102b, and a second P base region 107 and a second n+ source region 108 are further disposed at the bottom of the second gate oxide layer 102b. The top surface of the second P base region 107 contacts the bottom surface of the second gate oxide layer 102b. The top surface of the second n+ source region 108 is also in contact with the bottom surface of the second gate oxide 102b. And a second n+ source region 108 is provided on the top surface of the second P base region 107. A second p+ ohmic contact region 109 is also provided outside the second n+ source region 108. In the present embodiment, the top surfaces of the second p+ ohmic contact region 109 and the second n+ source region 108 are flush with the top surface of the second gate oxide layer 102b. Meanwhile, the second p+ ohmic contact region 109 is on top of the second P base region 107 and is tightly surrounded by the second P base region 107. And the second p+ ohmic contact region 109 is not in contact with the second gate oxide layer 102b. And, the second p+ ohmic contact region 109 is not in contact with the second gate oxide layer 102b.
The second P base region 107 is located at the interface between the second gate oxide layer 102b and the N region 101 and extends to below the second p+ ohmic contact region 109, and tightly surrounds the second n+ source region 108 and the second p+ ohmic contact region 109. When a voltage exceeding a threshold is applied to the emitter E by the gate electrode, an electron channel is formed. The top surface of the second P-base region 107 contacts the second gate oxide layer 102b, and the electron channel formed at this time is N-type. Only when the top surfaces of the second n+ source region 108 and the second P base region 107 are both in contact with the bottom surface of the second gate oxide layer 102b, electrons can be collected near the second gate oxide layer 102b, so that the formation of an electron channel is ensured, and the current is smooth.
An emitter metal layer 113 is disposed over the first n+ source region 105, the first p+ ohmic contact region 106, the second n+ source region 108, the second p=ohmic contact region 109, and the polysilicon layer 103. A first isolation oxide layer 110a and a second isolation oxide layer 110b are also provided between the polysilicon layer 103 and the emission metal layer 113. The first isolation oxide layer 110a and the second isolation oxide layer 110b are of an integral structure. Wherein, the first isolation oxide layer 110a is disposed on the top surface of the polysilicon layer 103. The second isolation oxide layer 110b is disposed on the side of the polysilicon 103. Wherein the first isolation oxide layer 110a covers a portion of the top surface of the first n+ source region 105 and the second isolation oxide layer 110b covers a portion of the top surface of the second n+ source region 108. In this embodiment, the emission metal layer 113 is in contact with the top surface of the first p+ ohmic contact region 106, the top surface 105 of the first n+ source region, the top surface of the second p+ ohmic contact region 109, and the top surface of the second n+ source region 108.
When a step-type trench is formed on the top of the N-region, a trench is first dug in the top of the N-region 101, a corresponding trench is etched, and the trench is oxidized to form a gate oxide layer 102. Then, a gate polysilicon layer 103 is disposed on the gate oxide layer 102, and an isolation oxide layer 110 is formed on the polysilicon layer 103. The isolation oxide layer 110 serves to electrically isolate the polysilicon layer 103 from the outer layer. Wherein the polysilicon layer 103 is generally filled with polysilicon material. The gate oxide layer 102 includes a second gate oxide layer 102a and a first gate oxide layer 102b. The isolation oxide layer 110 includes a first isolation oxide layer 110a and a second isolation oxide layer 110b.
The IGBT device in this embodiment combines two gate structures of a trench gate and a trench gate, and thus has two operating mechanisms of a planar gate IGBT and a trench gate IGBT. And the gate oxidation process of the planar gate IGBT part and the trench gate IGBT part can be completed simultaneously, and the planar gate IGBT part and the trench gate IGBT part can have the same gate oxide thickness, so that the manufacturing process is simplified, and the yield is improved.
Example two
In a preferred embodiment, as shown in fig. 4, an N hole blocking region 122 may be further disposed between the N-region 101 and the P base region 107, the P base region 104 on the basis of the first embodiment. The N hole blocking region 122 is arranged at the bottom of the P base region, so that the carrier injection level of the IGBT when the current is conducted can be effectively improved, the on-resistance is reduced, and the on-loss is reduced. In specific application, an N hole blocking region may be disposed at the bottom of any P base region according to actual situations, or an N hole blocking region 122 may be disposed at the bottoms of two P base regions at the same time.
Example III
In one embodiment, the top of the p+ ohmic contact region is set down. As shown in fig. 5, the top of the first p+ ohmic contact region 106 is lower than the first n+ source region 105, and the top of the second p+ ohmic contact region 109 is lower than the second n+ source region 108. Similarly, when the gate electrode applies a voltage exceeding a threshold to the emitter E, the electron channel can be smoothly formed in a thin layer on the side of the P base region close to the gate oxide layer.
In particular, such an arrangement can facilitate the etching operation. The etching and doping of the P+ ohmic contact region belongs to the last processing technology in the silicon body at one side of the emitter, and the doping depth is mainly controlled by ion implantation, so that the effective P type concentration is reduced by etching the N+ source region without compensating the N type doping of the N+ source region by the P type impurity implanted into the P+ ohmic contact region, and the position of the P+ ohmic contact region is reduced at the same time, and then P+ ions are implanted, thereby achieving better implantation effect.
Example IV
In a new embodiment, the original N-type doped region in the trench gate IGBT device of the first, second and third embodiments is replaced with a P-type doped region, and the original P-type doped region is replaced with an N-type doped region. This will cause the channel type of the original trench gate IGBT device to be converted from N-channel to P-channel. The substitution involves only a change in the doping type, the doping concentration being constant with respect to the size, e.g., P for N, p+ for n+, N-for P-, N for P, N 'for P', n+ for p+. Such conversion can also achieve the technical effects of the present invention.
In the above embodiments and the corresponding drawings, only the minimum functional units of the present disclosure are shown. The right side boundary of the structure of each drawing is mirrored to the right, so that a new minimum functional unit conforming to the content of the invention can be obtained. The leftmost boundary of the structure of each drawing is mirrored left to obtain a new minimum functional unit which accords with the content of the invention and has the same right side mirror image operation. Thus, the terms "left" and "right" in this specification are interchangeable only with respect to the structure of the drawings, and are not intended to limit the scope of the invention.
The above is only a preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily make modifications or variations within the technical scope of the present invention disclosed herein, and such modifications or variations are intended to be included in the scope of the present invention. Therefore, the protection scope of the invention is subject to the protection scope of the claims.
Claims (8)
1. An IGBT device, comprising: the collector comprises a collector metal layer, a P+ region, an N' region and an N-region which are sequentially arranged from bottom to top, wherein a step-type groove is formed at the top of the N-region, and groove gates and plane gates are formed on different steps of the groove;
the trench gate includes:
a first gate oxide layer formed within the trench,
the first P base region is arranged outside the first gate oxide layer, the side surface of the first P base region is contacted with the first gate oxide layer,
a first N+ source region disposed on top of the first P base region and in contact with the first gate oxide layer,
the first P+ ohmic contact region is arranged on one side of the first N+ source electrode region, and the first P+ ohmic contact region is not contacted with the gate oxide layer;
the planar gate includes:
a second gate oxide layer formed within the trench,
a second P base region arranged below the second gate oxide layer, the top of the second P base region is contacted with the gate oxide layer,
a second N+ source region disposed on top of the second P base region and flush with a top edge of the second gate oxide layer,
and the second P+ ohmic contact region is arranged at one side of the second N+ source electrode region, and the second P+ ohmic contact region is not contacted with the gate oxide layer.
2. The IGBT device of claim 1 wherein: the bottom surface of the first N+ source region is not higher than the top surface of the first gate oxide layer.
3. The IGBT device of claim 1 wherein: the top surface of the first P+ ohmic contact region is flush with the top surface of the first N+ source region, or the top surface of the first P+ ohmic contact region is lower than the top surface of the first N+ source region.
4. The IGBT device of claim 1 wherein the top surface of the second p+ ohmic contact region is level with the top surface of the second n+ source region or the top surface of the second p+ ohmic contact region is lower than the top surface of the second n+ source region.
5. The IGBT device of claim 1 further comprising any one or a combination of an N hole blocking region disposed between the trench and the first P base region or an N hole blocking region disposed between the trench and the second P base region.
6. The IGBT device of claim 1, wherein,
the IGBT device further comprises a polysilicon layer formed above the second gate oxide layer, wherein the top surface of the polysilicon layer is not lower than the top surface of the first N+ source region.
7. The IGBT device of claim 6 wherein the polysilicon layer is formed with a first isolation oxide layer over the polysilicon layer, the polysilicon layer is formed with a second isolation oxide layer on a side surface, the first isolation oxide layer covers a portion of the top surface of the first n+ source region, the second isolation oxide layer covers a portion of the top surface of the second n+ source region, and the first isolation oxide layer and the second isolation oxide layer are of unitary construction.
8. The IGBT device of claim 7 further comprising a metal emitter layer in contact with the top surface of the first p+ ohmic contact region, the top surface of the first n+ source region, the top surface of the second p+ ohmic contact region, and the top surface of the second n+ source region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811277607.9A CN111129132B (en) | 2018-10-30 | 2018-10-30 | IGBT device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811277607.9A CN111129132B (en) | 2018-10-30 | 2018-10-30 | IGBT device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111129132A CN111129132A (en) | 2020-05-08 |
| CN111129132B true CN111129132B (en) | 2023-09-08 |
Family
ID=70484440
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811277607.9A Active CN111129132B (en) | 2018-10-30 | 2018-10-30 | IGBT device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111129132B (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001358338A (en) * | 2000-06-14 | 2001-12-26 | Fuji Electric Co Ltd | Trench gate type semiconductor device |
| KR20050083340A (en) * | 2004-02-23 | 2005-08-26 | 재단법인서울대학교산학협력재단 | Dual gate transistor |
| CN107785415A (en) * | 2017-10-27 | 2018-03-09 | 电子科技大学 | A kind of SOI RC LIGBT devices and preparation method thereof |
| CN108321196A (en) * | 2018-02-05 | 2018-07-24 | 电子科技大学 | A kind of trench gate charge storage type IGBT and preparation method thereof |
| CN108615707A (en) * | 2018-02-13 | 2018-10-02 | 株洲中车时代电气股份有限公司 | A kind of production method of the igbt chip with the compound grid structure of folded form |
| CN108682624A (en) * | 2018-02-13 | 2018-10-19 | 株洲中车时代电气股份有限公司 | A kind of igbt chip production method with composite grid |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008305998A (en) * | 2007-06-07 | 2008-12-18 | Fuji Electric Device Technology Co Ltd | Semiconductor device |
| WO2015127673A1 (en) * | 2014-02-28 | 2015-09-03 | 电子科技大学 | Bi-directional igbt component |
-
2018
- 2018-10-30 CN CN201811277607.9A patent/CN111129132B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001358338A (en) * | 2000-06-14 | 2001-12-26 | Fuji Electric Co Ltd | Trench gate type semiconductor device |
| KR20050083340A (en) * | 2004-02-23 | 2005-08-26 | 재단법인서울대학교산학협력재단 | Dual gate transistor |
| CN107785415A (en) * | 2017-10-27 | 2018-03-09 | 电子科技大学 | A kind of SOI RC LIGBT devices and preparation method thereof |
| CN108321196A (en) * | 2018-02-05 | 2018-07-24 | 电子科技大学 | A kind of trench gate charge storage type IGBT and preparation method thereof |
| CN108615707A (en) * | 2018-02-13 | 2018-10-02 | 株洲中车时代电气股份有限公司 | A kind of production method of the igbt chip with the compound grid structure of folded form |
| CN108682624A (en) * | 2018-02-13 | 2018-10-19 | 株洲中车时代电气股份有限公司 | A kind of igbt chip production method with composite grid |
Also Published As
| Publication number | Publication date |
|---|---|
| CN111129132A (en) | 2020-05-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10608106B2 (en) | Power semiconductor devices | |
| JP6266166B2 (en) | Silicon carbide semiconductor device and manufacturing method thereof | |
| US8575685B2 (en) | Buried field ring field effect transistor (BUF-FET) integrated with cells implanted with hole supply path | |
| TWI383497B (en) | Double gate insulated gate bipolar transistor | |
| CN215377412U (en) | Power semiconductor device | |
| US10529839B2 (en) | Semiconductor device | |
| CN108847423B (en) | Semiconductor device and method for manufacturing the same | |
| US20200020798A1 (en) | Power mosfet with an integrated pseudo-schottky diode in source contact trench | |
| JPH01253966A (en) | Vertical field effect transistor | |
| JPH06188438A (en) | Dielectric isolation semiconductor device and manufacture thereof | |
| JPWO2002097888A1 (en) | Power semiconductor devices | |
| JP2983110B2 (en) | Semiconductor device and manufacturing method thereof | |
| JPH08227999A (en) | Integrated gate bipolar transistor and its manufacture and semiconductor integrated circuit and its manufacture | |
| US11664434B2 (en) | Semiconductor power devices having multiple gate trenches and methods of forming such devices | |
| JP2011204808A (en) | Semiconductor device and method of manufacturing the same | |
| JP2003338624A (en) | Semiconductor device | |
| CN113437142A (en) | Trench type IGBT structure and manufacturing method thereof | |
| CN114497201A (en) | Field effect transistor of integrated body relay diode, preparation method thereof and power device | |
| JP2020004876A (en) | Silicon carbide semiconductor device | |
| CN111129132B (en) | IGBT device | |
| US12107160B2 (en) | Power device and manufacturing method thereof | |
| CN116741837A (en) | Stepped grid silicon carbide MOSFET, preparation method thereof and chip | |
| CN116364763A (en) | MOSFET device and manufacturing method thereof | |
| KR20190124894A (en) | Semiconductor device and method manufacturing the same | |
| CN113451296A (en) | Power element with lateral insulated gate bipolar transistor and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| TA01 | Transfer of patent application right | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20200928 Address after: 412001 Room 309, floor 3, semiconductor third line office building, Tianxin hi tech park, Shifeng District, Zhuzhou City, Hunan Province Applicant after: Zhuzhou CRRC times Semiconductor Co.,Ltd. Address before: The age of 412001 in Hunan Province, Zhuzhou Shifeng District Road No. 169 Applicant before: ZHUZHOU CRRC TIMES ELECTRIC Co.,Ltd. |
|
| GR01 | Patent grant | ||
| GR01 | Patent grant |