CN115050824A - Middle-high voltage shielding grid power MOSFET - Google Patents

Middle-high voltage shielding grid power MOSFET Download PDF

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CN115050824A
CN115050824A CN202210542949.9A CN202210542949A CN115050824A CN 115050824 A CN115050824 A CN 115050824A CN 202210542949 A CN202210542949 A CN 202210542949A CN 115050824 A CN115050824 A CN 115050824A
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semiconductor
threshold
epitaxial layer
conductivity type
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张振宇
刘挺
顾书帆
赵群
张博
王毅
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Yangjie Technology Wuxi Co ltd
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Yangjie Technology Wuxi Co ltd
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Abstract

The application discloses well high voltage shielding grid power MOSFET, this structure mainly includes: a semiconductor drain region; a semiconductor drift region; a first trench located at a sidewall of the semiconductor drift region; a semiconductor pillar of the second conductivity type and having a depth not less than a third threshold; a second trench; shielding the gate oxide layer; a shield gate electrode; an inter-electrode dielectric; a gate oxide layer; a gate electrode; a second conductivity type semiconductor well region; a first conductivity type semiconductor source region; a second conductive type semiconductor body contact region. The power line aggregation phenomenon at the corner of the grid oxide layer and the corner of the shielding grid oxide layer when the device is in the resistance state is optimized, and meanwhile, the drift region with high doping can be realized to reduce the on-state resistance of the device and improve the performance of the device.

Description

Middle-high voltage shielding grid power MOSFET
Technical Field
The application belongs to the technical field of semiconductor power devices, and particularly relates to a middle-high voltage shielded gate power MOSFET.
Background
The vertical double-diffused power device is widely applied to a power integrated circuit because of the advantages of high voltage resistance, large current, high switching speed and the like. However, the high breakdown voltage of a power device generally requires a longer drift region, which, however, increases the specific on-resistance of the device exponentially, resulting in greater static power consumption of the device.
In the prior art, the shielding gate technology can effectively relieve the contradiction between the breakdown voltage and the specific on-resistance of the device. The shielding grid technology is to introduce a shielding grid electrode into a conventional groove grid longitudinal double-diffusion power device, the introduced shielding grid can not only assist in depleting a drift region to reduce the on-resistance of the device, but also reduce the overlapping area of a grid electrode and a drain region to reduce the Miller capacitance, so that the shielding grid power device is a mainstream device in the field of medium and low voltage power devices at present. However, when the shielded gate power device is in a blocking state, a phenomenon of relatively concentrated power line aggregation occurs at the corners of the gate oxide layer or the shielded gate oxide layer, which may cause the device to fail in advance.
Disclosure of Invention
The application provides a middle and high voltage shielding gate power MOSFET, which aims at the problem that the corners of a gate oxide layer or a shielding gate oxide layer of a shielding gate power device in a blocking state are gathered together by concentrated power lines and further optimizes the static power consumption of the device.
In order to achieve the above object, one technical solution adopted by the present application is to provide a medium-high voltage shielded gate power MOSFET, including: a semiconductor drain region of heavily doped semiconductor material of a first conductivity type; the semiconductor drift region is made of a semiconductor material which is lightly doped with a first conductive type and comprises a first epitaxial layer, and the first epitaxial layer is positioned above the semiconductor drain region; the second epitaxial layer is positioned above the first epitaxial layer; the third epitaxial layer is positioned above the second epitaxial layer, the sum of the thicknesses of the first epitaxial layer and the second epitaxial layer is not less than the first threshold value, and the total thickness of the semiconductor drift region is not less than the second threshold value; the first trench is positioned on the side wall of the semiconductor drift region, and the depth of the first trench is not less than the third threshold value; a semiconductor pillar of a second conductivity type formed by depositing a semiconductor material of the second conductivity type within the first trench; the second groove is positioned in the middle area of the semiconductor drift area, and the depth of the second groove is not less than a fourth threshold value; the shielding gate oxide layer is positioned on the inner wall of the second groove; the shielding gate electrode is positioned on the shielding gate oxide layer of the second groove, and the depth of the shielding gate electrode is not less than a fifth threshold value; an interpolar dielectric located above the shield gate electrode and having a thickness not less than a sixth threshold; a gate oxide layer formed on the sidewalls of the second trench and over the inter-electrode dielectric by thermal oxidation; a gate electrode deposited on the gate oxide layer; the second conduction type semiconductor well region is prepared on the third epitaxial layer and forms a thick region and a thin region, wherein the thick region is a part close to the second groove, the thin region is a part far away from the second groove, and the thickness of the thick region is greater than that of the thin region; a first conductivity type semiconductor source region located over the thick region of the second conductivity type semiconductor well region; a second conductivity type semiconductor body contact region located over the thin region of the second conductivity type semiconductor well region; the first threshold is smaller than the second threshold, the third threshold is between the first threshold and the second threshold, the fourth threshold is larger than the first threshold but smaller than the third threshold, the fifth threshold is smaller than the fourth threshold, and the sixth threshold is smaller than the fifth threshold.
Optionally, the interlayer dielectric is located above the gate electrode, and the interlayer dielectric is composed of undoped silicon oxide and borophosphosilicate glass;
optionally, the source metal electrode is located above the interlayer dielectric and contacts the semiconductor source region and the semiconductor body contact region through the contact hole; and the drain end metal electrode is positioned below the semiconductor drain region.
Optionally, the conductivity corresponding to the third epitaxial layer is greater than the conductivity corresponding to the second epitaxial layer, and the conductivity corresponding to the second epitaxial layer is greater than the conductivity corresponding to the first epitaxial layer.
Optionally, the bottom of the first trench extends into the first epitaxial layer.
Optionally, the thickness of the shielding gate oxide layer ranges from 0.25 μm to 0.95 μm.
Optionally, a lower bottom surface of the gate electrode is lower than a lower bottom surface of the second conductivity type semiconductor well region.
Optionally, for the high-voltage shielded gate power MOSFET in the N channel, the first conductivity type refers to an N type, and the second conductivity type is a P type; for a P-channel medium-high voltage shielded gate power MOSFET, the first conductivity type refers to P-type, and the second conductivity type is N-type.
The technical scheme of the application can reach the beneficial effect that: when the device is in a blocking state, the phenomenon of power line aggregation at the corners of the gate oxide layer and the shielding gate oxide layer can be relieved, the device is effectively prevented from failing in advance at one of the gate oxide layer and the shielding gate oxide layer, and the drift region can be assisted in the blocking state, so that the new structure can obtain high drift region concentration, the specific on-resistance of the new structure is reduced, and the static power consumption of the device during working is reduced.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to these drawings without inventive exercise.
Fig. 1 is a schematic diagram of the overall structure of a medium-high voltage shielded gate power MOSFET according to the present application;
fig. 2 is a schematic diagram of a first trench structure with a depth a of a medium-high voltage shielded gate power MOSFET according to the present application;
FIG. 3 is a schematic diagram of a second conductivity type semiconductor pillar structure of a medium to high voltage shielded gate power MOSFET of the present application;
fig. 4 is a schematic diagram of a second trench structure with a depth b of a medium-high voltage shielded gate power MOSFET according to the present application;
FIG. 5 is a schematic diagram of a shielded gate oxide structure of a medium-high voltage shielded gate power MOSFET of the present application;
FIG. 6 is a schematic diagram of a shield gate electrode structure of a medium-high voltage shield gate power MOSFET of the present application;
fig. 7 is a schematic structural diagram of an interpolar dielectric of a medium-high voltage shielded gate power MOSFET according to the present application;
FIG. 8 is a schematic diagram of a gate oxide structure of a medium-high voltage shielded gate power MOSFET according to the present application;
fig. 9 is a schematic structural diagram of a gate electrode of a medium-high voltage shielded gate power MOSFET according to the present application;
FIG. 10 is a schematic diagram of the semiconductor well, source and body regions of a middle and high voltage shielded gate power MOSFET of the present application;
FIG. 11 is a schematic diagram of the structure of the interlayer dielectric of a medium-high voltage shielded gate power MOSFET of the present application;
fig. 12 is a schematic structural diagram of a source metal electrode of a medium-high voltage shielded gate power MOSFET according to the present application;
the regions in fig. 1 to 12 are labeled as follows: 1-a semiconductor drain region, 2-a first epitaxial layer, 3-a second epitaxial layer, 4-a third epitaxial layer, 5-a second conductivity type semiconductor column, 6-a shielding gate oxide layer, 7-a shielding gate electrode, 8-an inter-electrode medium, 9-a gate oxide layer, 10-a gate electrode, 11-a second conductivity type semiconductor well region, 12-a first conductivity type semiconductor source region, 13-a second conductivity type semiconductor body contact region, 14-undoped silicon oxide, 15-boron phosphorus silicon glass, 16-a source end metal electrode, 17-a drain end metal electrode, 18-a first trench, and 19-a second trench.
With the above figures, there have been shown specific embodiments of the present application, which will be described in more detail below. The drawings and written description are not intended to limit the scope of the inventive concepts in any manner, but rather to illustrate the concepts of the application by those skilled in the art with reference to specific embodiments.
Detailed Description
The following detailed description of the preferred embodiments of the present application, taken in conjunction with the accompanying drawings, will provide those skilled in the art with a better understanding of the advantages and features of the present application, and will make the scope of the present application more clear and definite.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of additional identical elements in the process, method, article, or apparatus that comprises the element.
The following describes the technical solutions of the present application and how to solve the above technical problems with specific examples. The specific embodiments described below can be combined with each other to form new embodiments. The same or similar ideas or processes described in one embodiment may not be repeated in other embodiments. Embodiments of the present application will be described below with reference to the accompanying drawings.
Fig. 1 illustrates one embodiment of a medium-high voltage shielded gate power MOSFET of the present application.
A medium to high voltage shielded gate power MOSFET as shown in fig. 1, comprising: a semiconductor drain region (1) heavily doped with a semiconductor material of a first conductivity type;
a semiconductor drift region lightly doped with a semiconductor material of a first conductivity type comprising a first epitaxial layer (2), a second epitaxial layer (3) and a third epitaxial layer (4),
the first epitaxial layer is positioned above the semiconductor drain region,
the second epitaxial layer is located above the first epitaxial layer,
the third epitaxial layer is positioned above the second epitaxial layer,
the sum of the thicknesses of the first epitaxial layer and the second epitaxial layer is not smaller than a first threshold value, and the total thickness of the semiconductor drift region is not smaller than a second threshold value;
a first trench (18) located on a sidewall of the semiconductor drift region and having a depth not less than a third threshold;
a semiconductor pillar (5) of a second conductivity type formed by depositing a semiconductor material of the second conductivity type within the first trench;
a second trench (19) located in the middle region of the semiconductor drift region and having a depth not less than a fourth threshold;
a shielding gate oxide layer (6) which is positioned on the inner wall of the second groove;
a shielding gate electrode (7) which is positioned on the shielding gate oxide layer of the second trench and has the depth not less than a fifth threshold value;
an interpolar dielectric (8) located above the shield gate electrode and having a thickness not less than a sixth threshold;
a gate oxide layer (9) formed on the sidewalls of the second trench and over the inter-electrode dielectric;
a gate electrode (10) deposited on the gate oxide layer;
a second conductive type semiconductor well region (11) prepared above the third epitaxial layer and forming a thick region and a thin region, wherein the thick region is a part close to the second groove, the thin region is a part far away from the second groove, and the thickness of the thick region is greater than that of the thin region;
a first conductivity type semiconductor source region (12) located over a thick region of the second conductivity type semiconductor well region;
a second conductivity type semiconductor body contact region (13) located over the thin region of the second conductivity type semiconductor well region;
and the interlayer dielectric is positioned above the grid electrode and consists of undoped silicon oxide and boron-phosphorus-silicon glass.
Wherein the first threshold is smaller than the second threshold, the third threshold is between the first threshold and the second threshold, the fourth threshold is larger than the first threshold but smaller than the third threshold, the fifth threshold is smaller than the fourth threshold, and the sixth threshold is smaller than the fifth threshold.
Compared with a shielding gate power device with a conventional upper and lower structure, the shielding gate power device with the upper and lower structure has the advantages that the second conductive type semiconductor column is prepared in the first conductive type semiconductor drift region, so that the power line aggregation phenomenon of the corner of the gate oxide layer and the corner of the shielding gate oxide layer in the resistance state is optimized, the early failure of the device is avoided, and meanwhile, compared with the shielding gate power device with the conventional upper and lower structure, the shielding gate electrode and the second conductive type semiconductor column are used for assisting in depleting the first conductive type semiconductor drift region, so that the semiconductor drift region achieves higher doping concentration, and the static power consumption of the device in working is further reduced.
In the embodiment shown in fig. 1, the medium-high voltage shielded gate power MOSFET includes a semiconductor drain region (1) which is heavily doped with a semiconductor material of a first conductivity type. The structure is a basic structure for realizing a medium-high voltage shielding gate power MOSFET, and the conductivity of a semiconductor drain region can be improved by doping high-concentration impurity ions, so that the performance of a device is ensured.
In a specific embodiment of the present application, the semiconductor drain region is heavily doped with a semiconductor material of the first conductivity type. The first conductive type includes an N-type semiconductor material and a P-type semiconductor material, and the specific material type is determined by the type of the MOSFET. The heavy doping here means that the concentration of impurity atoms in the crystal is within a predetermined range. For example, the concentration of impurity atoms in the crystal is 4.5X 10 19 Per cm 3 -9×10 19 Per cm 3 In the meantime. The thickness of the semiconductor drain region may be 150 μm, and the specific thickness is not limited in this application.
In the embodiment shown in fig. 1, the medium-high voltage shielded gate power MOSFET includes a semiconductor drift region including a first epitaxial layer (2), a second epitaxial layer (3) and a third epitaxial layer (4), wherein the third epitaxial layer is located above the second epitaxial layer, the second epitaxial layer is located above the first epitaxial layer, the first epitaxial layer is located above the semiconductor drain region, wherein the sum of the thicknesses of the first epitaxial layer and the second epitaxial layer is not less than a first threshold value, and the total thickness of the semiconductor drift region is not less than a second threshold value. The electric field distribution of the drift region can be more uniform by arranging the three epitaxial layers, and because an electric field peak can be formed between the layers of the epitaxial layers, higher breakdown voltage can be realized, and the withstand voltage of the device is improved.
Specifically, silicon is deposited on the highly doped semiconductor drain region (1) and a first conductivity type semiconductor material is doped at a first concentration to form a first epitaxial layer (2). Silicon is deposited on the first epitaxial layer (2) and doped with a second concentration of semiconductor material of the first conductivity type to form a second epitaxial layer (3). Silicon is deposited on the second epitaxial layer (3) and doped with a third concentration of semiconductor material of the first conductivity type to form a third epitaxial layer (4).
The sum of the thicknesses of the first epitaxial layer and the second epitaxial layer is not less than a first threshold value, the total thickness of the semiconductor drift region is not less than a second threshold value, wherein the total thickness of the semiconductor drift region is the sum of the thickness of the first epitaxial layer, the thickness of the second epitaxial layer and the thickness of the third epitaxial layer, and the thickness of each epitaxial layer can be calculated according to the required withstand voltage energy and the specific on-resistance value, for example, the thicknesses of the first epitaxial layer, the second epitaxial layer and the third epitaxial layer can be 5 μm, 8 μm and 6 μm.
For example, taking a high-reliability medium-high voltage shielded gate power MOSFET of an N-type drift region as an example, a low-doped semiconductor drift region is formed on a high-doped semiconductor drain region (1), and the semiconductor drift region is composed of a low-doped first epitaxial layer (2), a medium-doped second epitaxial layer (3) and a high-doped third epitaxial layer (4). Wherein the doping concentration of the semiconductor drift region is 1.5 × 10 15 Per cm 3 -8.5×10 16 Per cm 3 。
In a specific embodiment of the present application, the conductivity corresponding to the third epitaxial layer is greater than the conductivity corresponding to the second epitaxial layer, and the conductivity corresponding to the second epitaxial layer is greater than the conductivity corresponding to the first epitaxial layer. The specific embodiment can better improve the performance of the device by reducing the specific on-resistance.
For example, when the resistivity of the first epitaxial layer is R1, the resistivity of the second epitaxial layer is R2, and the resistivity of the third epitaxial layer is R3, the conductivity relationship between the epitaxial layers of the semiconductor drift region is R3 < R2 < R1.
In the embodiment shown in fig. 1, the medium-high voltage shielded gate power MOSFET includes a first trench (18) located on a sidewall of the semiconductor drift region and having a depth not less than the third threshold. In this embodiment, the first trench is etched in the sidewall of the semiconductor drift region, which lays a foundation for introducing the semiconductor pillar of the second conductivity type in the semiconductor drift region.
Specifically, as shown in fig. 2, a first trench with a depth a is prepared on the sidewall of the semiconductor drift region by applying an etching method, wherein a value range of the depth of the first trench is determined according to the performance of the device. Preferably, the depth of the first trench of the medium-voltage device ranges from 2.5 μm to 15 μm, and the depth of the first trench of the high-voltage device ranges from about 30 μm.
In a specific embodiment of the present application, the trench bottom of the first trench extends into the first epitaxial layer. The bottom of the groove of the first groove extends into the first epitaxial layer, so that the doping concentration of the first epitaxial layer of the device can be improved, and the on-resistance of the device is reduced.
In the embodiment shown in fig. 1, the medium-high voltage shielded gate power MOSFET includes a semiconductor pillar (5) of the second conductivity type formed by depositing a semiconductor material of the second conductivity type within the first trench. The second conductive type semiconductor column is prepared in the first conductive type semiconductor drift region, so that the power line aggregation phenomenon at the corner of the gate oxide layer and the corner of the shielding gate oxide layer can be reduced when the second conductive type semiconductor column is in a resistance state, the advanced failure of the device at any position of the corner of the gate oxide layer and the corner of the shielding gate oxide layer is avoided, and the performance of the device is improved.
Specifically, as shown in fig. 3, a semiconductor material of the second conductivity type is deposited in the first trench by an epitaxial technique, and the semiconductor material of the second conductivity type is polished so that the upper surface of the deposited semiconductor material of the second conductivity type is flush with the surface of the third epitaxial layer, thereby forming a semiconductor pillar of the second conductivity type on the sidewall of the drift region.
In the embodiment shown in fig. 1, the medium-high voltage shielded gate power MOSFET includes a second trench (19) located in the middle region of the semiconductor drift region and having a depth not less than the fourth threshold. By etching the second trench, a foundation is laid for forming a shield gate electrode in the second trench.
Specifically, as shown in fig. 4, a second trench with a depth b is formed in the middle region of the drift region by an etching method. Wherein the depth of the second trench has a value range larger than the first threshold and smaller than the third threshold.
In a specific embodiment of the present application, the depth of the first trench is greater than the depth of the second trench.
Specifically, the first trench is filled with the second conductive type semiconductor material, and the fully depleted second conductive type semiconductor pillar is beneficial to relieving the phenomenon of electric line aggregation at the corner of the shielding gate oxide layer in the second trench, and the second conductive type semiconductor pillar is also beneficial to enhancing the reliability of the corner of the gate oxide layer.
In the embodiment shown in fig. 1, the medium-high voltage shielded gate power MOSFET includes a shielded gate oxide layer (6) located on the inner wall of the second trench. The shielding gate oxide layer can ensure the electric isolation between the shielding gate electrode and the first conductive material, and the performance of the device is ensured.
In one embodiment of the present application, the thickness of the shield gate oxide layer ranges from 0.25 μm to 0.95 μm. The performance of the device is ensured by setting the thickness of the shielding gate oxide layer.
Specifically, when the shield gate oxide layer is thin, the device cannot achieve medium-high withstand voltage. When the shielding gate oxide layer is thicker, the auxiliary depletion effect of the shielding gate electrode on the semiconductor drift region is obviously weakened, so that the specific on-resistance of the device is obviously increased, and the value range of the thickness of the shielding gate oxide layer is set to be 0.25-0.95 mu m to ensure the performance of the device.
For example, as shown in fig. 5, an oxide layer with a first predetermined oxidation thickness is formed in the second trench by a thermal oxidation process, and then an oxide layer with a second predetermined oxidation thickness is prepared by sub-pressure chemical vapor deposition, so as to form a shield gate oxide layer. Wherein the first predetermined oxidation thickness may be 0.05-0.1 μm and the second predetermined oxidation thickness may be 0.2-0.85 μm.
In the embodiment shown in fig. 1, the medium-high voltage shielded gate power MOSFET includes a shielded gate electrode (7) on the shielded gate oxide layer of the second trench and having a depth not less than a fifth threshold. The depletion effect of the semiconductor drift region is assisted by the shield gate electrode.
Specifically, as shown in fig. 6, a gate polysilicon of the shield gate is deposited on the shield gate oxide of the second trench by a chemical vapor deposition process to form a shield gate electrode of the structure 7 shown in fig. 6, and the deposited gate polysilicon of the shield gate is polished to make the upper surface of the deposited polysilicon flush with the upper surface of the third epitaxial layer, thereby forming a shield gate electrode.
In a specific embodiment of the present application, a lower bottom surface of the gate electrode is lower than a lower bottom surface of the second conductivity type semiconductor well region.
Specifically, the depth of the gate electrode cannot exceed the junction of the third epitaxial layer and the second epitaxial layer, because the third epitaxial layer plays a role in current sharing, which is helpful for increasing the conductive area when the device is turned on, so as to further reduce the specific on-resistance of the new structure.
In the embodiment shown in fig. 1, the medium-high voltage shielded gate power MOSFET includes an interpolar dielectric (8) that overlies the shield gate electrode and has a thickness that is no less than a sixth threshold. The performance of the device is improved by arranging the inter-electrode medium to reduce the Miller capacitance of the device.
Specifically, as shown in fig. 7, the shield gate electrode (7) and the shield gate oxide layer (6) are etched. As shown in fig. 8, after the etching is completed, undoped silicon oxide is deposited over the shield gate electrode (7) by chemical vapor deposition, and the deposited undoped silicon oxide is etched back to form an interpolar dielectric (8) having a thickness c. Wherein the thickness of the inter-electrode dielectric may be in the range of 0.2 μm to 1 μm.
In the embodiment shown in fig. 1, the medium-high voltage shielded gate power MOSFET includes a gate oxide layer (9) deposited on the sidewalls of the second trench and over the inter-electrode dielectric.
Specifically, as shown in fig. 8, a gate oxide layer (9) of a third predetermined oxide thickness is prepared on the sidewalls of the second trench by a thermal oxidation process, wherein the third predetermined oxide thickness may be 0.05-0.1 μm.
In the embodiment shown in fig. 1, the medium-high voltage shielded gate power MOSFET includes a gate electrode (10) deposited on a gate oxide.
Specifically, gate polysilicon is deposited on the inter-electrode medium in the second trench by a chemical vapor deposition method, and the deposited gate polysilicon is polished to make the upper surface of the gate polysilicon flush with the upper surface of the third epitaxial layer, thereby forming a gate electrode.
In the embodiment shown in fig. 1, the medium-high voltage shielded gate power MOSFET includes a second conductivity type semiconductor well region (11) formed on the third epitaxial layer, and forming a thick region and a thin region, wherein the thick region is a portion close to the second trench, the thin region is a portion far away from the second trench, and the thickness of the thick region is greater than that of the thin region.
Specifically, a second conductivity type well region is prepared by ion implantation over the third epitaxial layer, and finally, a second conductivity type semiconductor well region (11) as in fig. 10 is obtained. Wherein, annealing is carried out after ion implantation is finished so as to eliminate defects and repair crystal lattice damage as much as possible, and the thin region of the second conductive type semiconductor well region is formed by a subsequent etching process.
In the embodiment shown in fig. 1, the medium-high voltage shielded gate power MOSFET includes a first conductivity type semiconductor source region (12) located over a thick region of a second conductivity type semiconductor well region.
Specifically, a semiconductor source region of the first conductivity type is prepared by ion implantation over a higher thickness portion of the second conductivity type semiconductor well region.
In the embodiment shown in fig. 1, the medium-high voltage shielded gate power MOSFET includes a second conductivity type semiconductor body contact region (13) located over a thin region of the second conductivity type semiconductor well region.
Specifically, the second conductive type semiconductor body contact region is prepared at the lower part of the second conductive type semiconductor well region through ion implantation.
In one embodiment of the present application, the medium-high voltage shielded gate power MOSFET further comprises an interlayer dielectric over the gate electrode, wherein the interlayer dielectric is composed of undoped silicon oxide and borophosphosilicate glass.
Specifically, as shown in fig. 11, undoped silicon oxide (14) and borophosphosilicate glass (15) are deposited on the first semiconductor source region and the gate electrode, which constitute an interlayer dielectric, and then contact holes are etched in the interlayer dielectric.
In one embodiment of the present application, the medium-high voltage shielded gate power MOSFET further comprises a source metal electrode located above the interlayer dielectric and contacting the semiconductor source region and the semiconductor body contact region through the contact hole; and the drain end metal electrode is positioned below the semiconductor drain region.
Specifically, as shown in fig. 12, a source terminal metal electrode (16) is formed by depositing a conductive metal over the interlayer dielectric and over the second-type semiconductor contact region and etching the conductive metal. And depositing conductive metal below the semiconductor drain region to form a drain end metal electrode (17), thereby forming the middle-high voltage shielding grid power MOSFET with a complete structure.
In a specific embodiment of the present application, where the medium-high voltage shielded gate power MOSFET is a first type channel device, the first conductivity type is a first type semiconductor material, the second conductivity type is a second type semiconductor material, the first and second types are N-type or P-type, and the first and second types are different types.
Specifically, for an N-channel medium-high voltage shielded gate power MOSFET, the first conductivity type is N-type, and the second conductivity type is P-type. For a P-channel medium-high voltage shielded gate power MOSFET, the first conductivity type is P-type, and the second conductivity type is N-type.
In the several embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
The above description is only an example of the present application and is not intended to limit the scope of the present application, and all equivalent structural changes made by using the contents of the specification and the drawings, which are directly or indirectly applied to other related technical fields, are included in the scope of the present application.

Claims (8)

1. A medium-high voltage shielded gate power MOSFET comprising:
a semiconductor drain region heavily doped with a semiconductor material of a first conductivity type;
a semiconductor drift region lightly doped with a semiconductor material of a first conductivity type, comprising a first epitaxial layer, the first epitaxial layer being located above the semiconductor drain region;
a second epitaxial layer located above the first epitaxial layer, an
A third epitaxial layer located above the second epitaxial layer;
the sum of the thicknesses of the first epitaxial layer and the second epitaxial layer is not less than a first threshold value, and the total thickness of the semiconductor drift region is not less than a second threshold value;
a first trench located on a sidewall of the semiconductor drift region and having a depth not less than a third threshold;
a semiconductor pillar of a second conductivity type formed by depositing a semiconductor material of the second conductivity type within the first trench;
a second trench located in a middle region of the semiconductor drift region and having a depth not less than a fourth threshold;
the shielding gate oxide layer is positioned on the inner wall of the second groove;
the shielding gate electrode is positioned on the shielding gate oxide layer, and the depth of the shielding gate electrode is not less than a fifth threshold value;
an inter-electrode dielectric over the shield gate electrode and having a thickness not less than a sixth threshold;
a gate oxide layer formed on sidewalls of the second trench and over the inter-electrode dielectric by thermal oxidation;
a gate electrode deposited on the gate oxide layer;
a second conductive type semiconductor well region prepared on the third epitaxial layer and forming a thick region and a thin region, wherein the thick region is a part close to the second trench, the thin region is a part far away from the second trench, and the thickness of the thick region is greater than that of the thin region;
a first conductivity type semiconductor source region located over the thick region of the second conductivity type semiconductor well region;
a second conductivity type semiconductor body contact region located over the thin region of the second conductivity type semiconductor well region;
an interlayer dielectric over the gate electrode, the interlayer dielectric being comprised of undoped silicon oxide and borophosphosilicate glass.
Wherein the first threshold is less than the second threshold, the third threshold is between the first threshold and the second threshold, the fourth threshold is greater than the first threshold but less than the third threshold, the fifth threshold is less than the fourth threshold, and the sixth threshold is less than the fifth threshold.
2. The medium-high voltage shielded gate power MOSFET of claim 1 further comprising:
a source end metal electrode which is positioned above the interlayer medium and is contacted with the semiconductor source region and the semiconductor body contact region through a contact hole;
and the drain end metal electrode is positioned below the semiconductor drain region.
3. The medium-high voltage shielded gate power MOSFET of claim 1 wherein the conductivity corresponding to the third epitaxial layer is greater than the conductivity corresponding to the second epitaxial layer, and the conductivity corresponding to the second epitaxial layer is greater than the conductivity corresponding to the first epitaxial layer.
4. The medium-high voltage shielded gate power MOSFET of claim 1 wherein the first trench depth is greater than the second trench depth.
5. The medium-high voltage shielded gate power MOSFET of claim 1 wherein the second trench bottom extends into the interior of the first epitaxial layer.
6. The medium-high voltage shielded gate power MOSFET of claim 1 wherein the thickness of the shielded gate oxide layer ranges from 0.25 μm to 0.95 μm.
7. The medium-high voltage shielded gate power MOSFET of claim 1 wherein a lower bottom surface of the gate electrode is lower than a lower bottom surface of the second conductivity type semiconductor well region.
8. The medium-high voltage shielded gate power MOSFET of claim 1 wherein for an N-channel medium-high voltage shielded gate power MOSFET, the first conductivity type is N-type and the second conductivity type is P-type; for a P-channel medium-high voltage shielded gate power MOSFET, the first conductivity type refers to P-type, and the second conductivity type is N-type.
CN202210542949.9A 2022-05-18 2022-05-18 Middle-high voltage shielding grid power MOSFET Pending CN115050824A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN118335778A (en) * 2024-06-11 2024-07-12 深圳市港祥辉电子有限公司 Diamond SGT device and preparation method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN118335778A (en) * 2024-06-11 2024-07-12 深圳市港祥辉电子有限公司 Diamond SGT device and preparation method thereof

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