CN111129132A - IGBT device - Google Patents

IGBT device Download PDF

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Publication number
CN111129132A
CN111129132A CN201811277607.9A CN201811277607A CN111129132A CN 111129132 A CN111129132 A CN 111129132A CN 201811277607 A CN201811277607 A CN 201811277607A CN 111129132 A CN111129132 A CN 111129132A
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region
oxide layer
top surface
gate
source region
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CN111129132B (en
Inventor
唐龙谷
吴煜东
戴小平
罗海辉
刘国友
张泉
覃荣震
彭勇殿
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Zhuzhou CRRC Times Semiconductor Co Ltd
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Zhuzhou CRRC Times Electric Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333—Vertical insulated gate bipolar transistors
    • H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

The invention provides an IGBT device, which comprises: the collector metal layer, the P + region, the N' region and the N-region are sequentially arranged from bottom to top, a step-type groove is formed at the top of the N-region, and a groove gate and a plane gate are formed on different steps of the groove. Compared with a trench type IGBT device with a single structure, the trench type IGBT device has the advantages that two grid structures of a trench grid and a planar grid are combined, and therefore two working mechanisms of the planar grid IGBT and the trench grid IGBT are achieved. The gate oxidation process for the planar gate IGBT part and the trench gate IGBT part can be done simultaneously and can have the same gate oxide thickness.

Description

IGBT device
Technical Field
The invention relates to a semiconductor device, in particular to an IGBT device.
Background
Insulated Gate Bipolar Transistors (IGBTs) are a new type of power electronic device that has attracted the most attention and developed rapidly in recent years. The IGBT device has the characteristics of high grid input impedance, wider safe working area when being switched on and switched off and the like, so the IGBT device has wide application in the aspects of motor drive, electric welding machines, induction cookers, UPS power supplies and the like.
The prior art has the advantages of wide application of planar IGBT devices and trench IGBT devices. The planar gate type IGBT gate oxide layer has good quality and simple manufacturing process; the trench gate IGBT has lower on-resistance, the contradiction relation between the on-resistance and the turn-off speed of the IGBT is optimized, and the trench gate groove is rough in surface and large in damage after being etched, so that the mobility of current carriers is influenced. In addition, the gate capacitance of the trench gate is large, which reduces its short-circuit capability. At present, there is no structure for combining the two.
Disclosure of Invention
In view of the above technical problems in the prior art, the present invention provides an IGBT device, including: the collector metal layer, the P + region, the N' region and the N-region are sequentially arranged from bottom to top, a step-type groove is formed at the top of the N-region, and a groove gate and a plane gate are formed on different steps of the groove.
In one embodiment, the trench gate includes: the first P + source electrode region is arranged at the top of the first P base region and is in contact with the first grid oxide layer, the first P + ohmic contact region is arranged on one side of the first N + source electrode region, and the first P + ohmic contact region is not in contact with the grid oxide layer.
In one embodiment, a planar gate includes: the second P + source region is arranged at the top of the second P base region and is flush with the edge of the top of the second grid oxide layer, and the second P + ohmic contact region is arranged on one side of the second N + source region and is not contacted with the second grid oxide layer.
In one embodiment, a bottom surface of the first N + source region is not higher than a top surface of the first gate oxide layer.
In one embodiment, a top surface of the first P + ohmic contact region is flush with a top surface of the first N + source region, or the top surface of the first P + ohmic contact region is lower than the top surface of the first N + source region.
In one embodiment, the top surface of the second P + ohmic contact region is flush with the top surface of the second N + source region, or the top surface of the second P + ohmic contact region is lower than the top surface of the second N + source region, and the first gate oxide layer and the second gate oxide layer are of an integral structure.
In one embodiment, the IGBT device further includes any one or a combination of an N-hole blocking region disposed between the N-region and the first P-base region or an N-hole blocking region disposed between the N-region and the second P-base region.
In one embodiment, the IGBT device further includes a polysilicon layer formed over the second gate oxide layer, a top surface of the polysilicon layer being not lower than a top surface of the first N + source region.
In one embodiment, a first isolation oxide layer is formed over the polysilicon layer, a second isolation oxide layer is formed on a side surface of the polysilicon layer, the first isolation oxide layer covers a portion of a top surface of the first N + source region, and the second isolation oxide layer covers a portion of a top surface of the second N + source region.
In one embodiment, the IGBT device further includes an emission metal layer contacting a top surface of the first P + ohmic contact region, a top surface of the first N + source region, a top surface of the second P + ohmic contact region, and a top surface of the second N + source region, the first isolation oxide layer and the second isolation oxide layer being a unitary structure.
Compared with the prior art, the invention has the advantages that compared with a groove type IGBT device with a single structure or a plane type IGBT device with a single structure, the device combines two grid structures of a groove grid and a plane grid, thereby having two working mechanisms of the plane grid IGBT and the groove grid IGBT. The gate oxidation process for the planar gate IGBT part and the trench gate IGBT part can be done simultaneously and can have the same gate oxide thickness.
Drawings
Preferred embodiments of the present invention will be described in detail below with reference to the attached drawing figures, wherein:
fig. 1 shows a cross-sectional view of a prior art trench gate IGBT structure.
Fig. 2 shows a cross-sectional view of a prior art planar gate IGBT structure.
Fig. 3 shows a cross-sectional view of an IGBT structure according to a first embodiment of the invention.
Fig. 4 shows a cross-sectional view of an IGBT structure according to a second embodiment of the invention.
Fig. 5 shows a cross-sectional view of an IGBT structure according to a third embodiment of the invention.
In the drawings, like parts are designated with like reference numerals, and the drawings are not drawn to scale.
Detailed Description
The invention will be further explained with reference to the drawings.
As shown in fig. 1, the conventional trench IGBT structure includes a collector metal layer 114, a P + region 112, an N' region 111, an N-region 101, and a step trench, which are sequentially disposed from bottom to top. A polysilicon layer is disposed in the trench. A P base region 104 is provided on a side surface of the trench. The bottom of the trench and the side surface close to one side of the P-base region 104 are provided with a gate oxide layer 102. An N + source region 105 is arranged on one side of the top of the P base region 104 close to the groove. A P + ohmic contact region 106 is provided on the top of the P base region 104 remote from the trench. An isolation oxide layer 110 is provided on top of the polysilicon. An emitter metal layer 113 is disposed on top of the isolation oxide layer 110, the N + source region 105, and the P + ohmic contact region 106. When a voltage exceeding a threshold value is applied to the gate electrode, a large number of electrons are gathered in the region of the P-base region 104 close to the gate oxide layer 102 to form an electron channel, and the electron channel, the N + source region 105 and the N-region 101 are of the same N type, so that an open current path is formed. When the voltage applied to the gate electrode is lower than the threshold value, the electron channel disappears, the P-base region 104 forms a barrier to prevent the N + source region 105 and the N-region 101 from electronically communicating, and the IGBT enters a turn-off process until the turn-off is completed. In the trench gate IGBT structure, electrons flow from the emitter into the collector, and the direction of current flow is reversed. There is a vertical flow in the channel near the gate oxide. Fig. 1 shows a minimum functional unit of the conventional trench IGBT, and a complete cell structure of the trench IGBT can be obtained by mirroring from the right edge of the structure of fig. 1 to the right.
As shown in fig. 2, the overall structure of the planar IGBT structure in the prior art is similar to that of the trench type, and the greatest difference is that the P base region 107, the P + ohmic contact region 109, and the N + source region 108 are disposed at different positions from those of the trench type. The P base region, the P + ohmic contact region 109 and the N + source region 108 of the trench gate are all located on the side face of the polysilicon gate, and the P base region 107, the P + ohmic contact region 109 and the N + source region 108 of the planar gate are all located at the bottom of the polysilicon gate. The current on-off principle is the same, when the grid applies a voltage higher than the threshold, the current reaches the emitter metal through the electron channel between the P base region 107 and the grid oxide layer 102 and the N + source region, so that an open current path is formed, and the path is closed. At this time, the current flows horizontally through the planar grid and flows out of the emitter. Fig. 2 shows a minimum functional unit of the conventional planar IGBT, which is mirrored along the left edge of the structure of fig. 2 to the left, so that a complete cell structure of the planar IGBT can be obtained.
Example one
The composite IGBT structure combines two structures of a planar gate and a trench gate. Specifically, as shown in fig. 3, the IGBT device of the present embodiment includes: a collector metal layer 114, a P + region 112, an N' region 111, and an N-region 101, which are sequentially disposed from bottom to top. Wherein a step-shaped trench is formed on top of N-region 101. The side and bottom of the step of the groove form a groove gate and a plane gate respectively.
Specifically, the trench gate includes a first gate oxide layer 102 a. A first P base region 104 and a first N + source region 105 are further disposed outside the first gate oxide layer 102 a. The side surface of the first P base region 104 is in contact with the first gate oxide layer 102 a. The side of the first N + source region 105 contacts the first gate oxide layer 102 a. And the first N + source regions 105 are all disposed on the top surface of the first P base region 104. A first P + ohmic contact region 106 is further disposed outside the first N + source region 105. In the present embodiment, the top surfaces of the first P + ohmic contact region 106 and the first N + source region 105 are flush with the top surface of the first gate oxide layer 102 a. Meanwhile, the first P + ohmic contact region 106 is on top of the first P base region 104 and is tightly surrounded by the first P base region 104. And the first P + ohmic contact region 106 is not in contact with the first gate oxide layer 102 a.
Preferably, the bottom surface of the first N + source region 105 is not higher than the top surface of the first gate oxide layer 102 a. Thus, the side of the first N + source region 105 contacts the first gate oxide layer 102 a. Also, the first P + ohmic contact region 106 is not in contact with the first gate oxide layer 102 a. The first P base region 104 is located at the interface between the first gate oxide layer 102a and the N-drift region 101 and extends to below the first P + ohmic contact region 106, and tightly surrounds the first N + source region 105 and the first P + ohmic contact region 106. When the gate electrode applies a voltage exceeding a threshold to the emitter E, an electron channel is formed. The side surface of the first P-base region 104 is in contact with the first gate oxide layer 102a, and the electron channel formed at this time is N-type. Only when the top surfaces of the first N + source region 105 and the first P base region 104 are lower than the top surface of the first gate oxide layer 102a, electrons can be gathered near the first gate oxide layer 102a, thereby ensuring that an electron channel is formed and the current is smooth.
The planar gate includes a second gate oxide layer 102b, and a second P base region 107 and a second N + source region 108 are further disposed at the bottom of the second gate oxide layer 102 b. The top surface of the second P base region 107 is in contact with the bottom surface of the second gate oxide layer 102 b. The top surface of the second N + source region 108 also contacts the bottom surface of the second gate oxide layer 102 b. And a second N + source region 108 is provided on the top surface of the second P base region 107. A second P + ohmic contact region 109 is further provided outside the second N + source region 108. In the present embodiment, the top surfaces of the second P + ohmic contact region 109 and the second N + source region 108 are flush with the top surface of the second gate oxide layer 102 b. Meanwhile, the second P + ohmic contact region 109 is on top of the second P base region 107 and is tightly surrounded by the second P base region 107. And the second P + ohmic contact region 109 is not in contact with the second gate oxide layer 102 b. And, the second P + ohmic contact region 109 is not in contact with the second gate oxide layer 102 b.
The second P base region 107 is located at the interface between the second gate oxide layer 102b and the N region 101 and extends to the lower side of the second P + ohmic contact region 109, and tightly surrounds the second N + source region 108 and the second P + ohmic contact region 109. When the gate electrode applies a voltage exceeding a threshold to the emitter E, an electron channel is formed. The top surface of the second P-base region 107 is in contact with the second gate oxide layer 102b, and the electron channel formed at this time is N-type. Only when the top surfaces of the second N + source region 108 and the second P base region 107 are both in contact with the bottom surface of the second gate oxide layer 102b, electrons can be gathered near the second gate oxide layer 102b, thereby ensuring that an electron channel is formed and the current is smooth.
An emitter metal layer 113 is disposed over the first N + source region 105, the first P + ohmic contact region 106, the second N + source region 108, the second P ═ ohmic contact region 109, and the polysilicon layer 103. A first isolation oxide layer 110a and a second isolation oxide layer 110b are also provided between the polysilicon layer 103 and the emitter metal layer 113. The first isolation oxide layer 110a and the second isolation oxide layer 110b are an integral structure. Wherein the first isolation oxide layer 110a is disposed on the top surface of the polysilicon layer 103. A second isolation oxide layer 110b is provided on the side of the polysilicon 103. The first isolation oxide layer 110a covers a portion of the top surface of the first N + source region 105, and the second isolation oxide layer 110b covers a portion of the top surface of the second N + source region 108. In this embodiment, the emission metal layer 113 contacts the top surface of the first P + ohmic contact region 106, the top surface 105 of the first N + source region, the top surface of the second P + ohmic contact region 109, and the top surface of the second N + source region 108.
When a step-type trench is formed at the top of the N-region, a trench is first dug at the top of the N-region 101, a corresponding trench is etched, and the trench is oxidized to form a gate oxide layer 102. Then, a gate polysilicon layer 103 is disposed on the gate oxide layer 102, and an isolation oxide layer 110 is formed on the polysilicon layer 103. The isolation oxide layer 110 serves to electrically isolate the polysilicon layer 103 from the outer layer. The polysilicon layer 103 is typically filled with a polysilicon material. The gate oxide layer 102 includes a second gate oxide layer 102a and a first gate oxide layer 102 b. The isolation oxide layer 110 includes a first isolation oxide layer 110a and a second isolation oxide layer 110 b.
The IGBT device in the embodiment combines two grid structures of a trench grid and a planar grid, so that the IGBT device has two working mechanisms of the planar grid IGBT and the trench grid IGBT. And the gate oxidation process of the planar gate IGBT part and the trench gate IGBT part can be completed simultaneously, the gate oxidation layer can have the same thickness, the manufacturing process is simplified, and the yield is improved.
Example two
In a preferred embodiment, as shown in fig. 4, on the basis of the first embodiment, an N-hole blocking region 122 may be further disposed between the N-region 101 and the P- base regions 107 and 104. The N hole blocking region 122 is arranged at the bottom of the P base region, so that the carrier injection level of the IGBT can be effectively improved when the current is conducted, the conduction resistance is reduced, and the conduction loss is reduced. In a specific application, an N hole blocking region may be disposed at the bottom of any one P base region according to an actual situation, or the N hole blocking regions 122 may be disposed at the bottoms of two P base regions at the same time.
EXAMPLE III
In one embodiment, the top of the P + ohmic contact region is provided downshifting. As shown in fig. 5, the top of the first P + ohmic contact region 106 is lower than the first N + source region 105, and the top of the second P + ohmic contact region 109 is lower than the second N + source region 108. Similarly, in such a structure, when a voltage exceeding a threshold value is applied to the emitter E by the gate electrode, an electron channel can be smoothly formed in the thin layer on the side of the P base region close to the gate oxide layer.
In particular, such an arrangement can facilitate the etching operation. The etching and doping of the P + ohm contact area belong to the last processing technology in the silicon body on one side of the emitter, the doping depth is mainly controlled by ion implantation, in order to prevent the P-type impurities injected into the P + ohm contact area from compensating with the N-type doping of an N + source area and reduce the effective P-type concentration, the N + source area can be etched away, meanwhile, the position of the P + ohm contact area is reduced, and then P + ions are injected, so that a better injection effect can be achieved.
Example four
In a new embodiment, the original N-type doped region in the trench gate IGBT device according to the first, second, and third embodiments is replaced with a P-type doped region, and the original P-type doped region is replaced with an N-type doped region. This will cause the channel type of the original trench gate IGBT device to switch from N-channel to P-channel. The replacement involves only a change in the doping type, with the relative magnitude of the doping concentration unchanged, e.g., P is replaced by N, P + is replaced by N +, N-is replaced by P-, N is replaced by P, N 'is replaced by P', N + is replaced by P +. The technical effect of the invention can be achieved by the conversion.
In the above embodiments and the corresponding drawings, only the minimum functional units of the present disclosure are shown. The structure rightmost boundary of each figure is mirrored to the right, so that a new minimum functional unit which accords with the content of the invention can be obtained. By mirroring the leftmost boundary of the structure of each figure to the left, a new minimum functional unit consistent with the content of the present invention can be obtained, which is the same as the right-side mirroring operation. Therefore, "left" and "right" in the present specification are only for the structure of the drawings, and if the structure is a mirror image, the expressions of "left" and "right" are interchangeable, and do not limit the content of the present invention.
The above is only a preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily make changes or variations within the technical scope of the present invention disclosed, and such changes or variations should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims (10)

1. An IGBT device, characterized by comprising: the collector electrode structure comprises a collector electrode metal layer, a P + region, an N 'region and an N-region, wherein the collector electrode metal layer, the P + region, the N' region and the N-region are sequentially arranged from bottom to top, a step-shaped groove is formed at the top of the N-region, and a groove gate and a plane gate are formed on different steps of the groove.
2. The IGBT device of claim 1, wherein the trench gate comprises:
a first gate oxide layer formed in the trench,
a first P base region arranged at the outer side of the first grid oxide layer, wherein the side surface of the first P base region is contacted with the first grid oxide layer,
a first N + source region disposed on top of the first P base region and in contact with the first gate oxide layer,
and the first P + ohmic contact region is arranged on one side of the first N + source region and is not in contact with the grid oxide layer.
3. The IGBT device of claim 2, wherein the planar gate comprises:
a second gate oxide layer formed in the trench,
a second P base region arranged below the second grid oxide layer, wherein the top of the second P base region is contacted with the grid oxide layer,
a second N + source region arranged on the top of the second P base region and flush with the top edge of the second gate oxide layer,
and the second P + ohmic contact region is arranged on one side of the second N + source region and is not in contact with the grid oxide layer.
4. The IGBT device of claim 2, wherein: the bottom surface of the first N + source region is not higher than the top surface of the first gate oxide layer.
5. The IGBT device according to claim 2 or 3, characterized in that: the top surface of the first P + ohmic contact region is flush with the top surface of the first N + source region, or the top surface of the first P + ohmic contact region is lower than the top surface of the first N + source region.
6. The IGBT device of claim 3, wherein a top surface of the second P + ohmic contact region is flush with a top surface of the second N + source region, or wherein a top surface of the second P + ohmic contact region is lower than a top surface of the second N + source region.
7. The IGBT device of claim 3, further comprising any one or a combination of an N hole blocking region disposed between the trench and the first P base region or an N hole blocking region disposed between the trench and the second P base region.
8. The IGBT device of claim 3,
the IGBT device further comprises a polysilicon layer formed above the second gate oxide layer, wherein the top surface of the polysilicon layer is not lower than the top surface of the first N + source region.
9. The IGBT device of claim 8, wherein a first isolation oxide layer is formed over the polysilicon layer, wherein a second isolation oxide layer is formed on a side surface of the polysilicon layer, wherein the first isolation oxide layer covers a portion of a top surface of the first N + source region, and wherein the second isolation oxide layer covers a portion of a top surface of the second N + source region. The first isolation oxide layer and the second isolation oxide layer are of an integral structure.
10. The IGBT device of claim 9, further comprising a metal emitter layer, the emitter metal layer contacting a top surface of the first P + ohmic contact region, a top surface of the first N + source region, a top surface of a second P + ohmic contact region, and a top surface of the second N + source region.
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Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001358338A (en) * 2000-06-14 2001-12-26 Fuji Electric Co Ltd Trench gate type semiconductor device
KR20050083340A (en) * 2004-02-23 2005-08-26 재단법인서울대학교산학협력재단 Dual gate transistor
US20080303057A1 (en) * 2007-06-07 2008-12-11 Fuji Electric Device Technology Co., Ltd. Semiconductor device and method of manufacturing thereof
US20160322483A1 (en) * 2014-02-28 2016-11-03 University Of Electronic Science And Technology Of China Bidirectional insulated gate bipolar transistor
CN107785415A (en) * 2017-10-27 2018-03-09 电子科技大学 A kind of SOI RC LIGBT devices and preparation method thereof
CN108321196A (en) * 2018-02-05 2018-07-24 电子科技大学 A kind of trench gate charge storage type IGBT and preparation method thereof
CN108615707A (en) * 2018-02-13 2018-10-02 株洲中车时代电气股份有限公司 A kind of production method of the igbt chip with the compound grid structure of folded form
CN108682624A (en) * 2018-02-13 2018-10-19 株洲中车时代电气股份有限公司 A kind of igbt chip production method with composite grid

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001358338A (en) * 2000-06-14 2001-12-26 Fuji Electric Co Ltd Trench gate type semiconductor device
KR20050083340A (en) * 2004-02-23 2005-08-26 재단법인서울대학교산학협력재단 Dual gate transistor
US20080303057A1 (en) * 2007-06-07 2008-12-11 Fuji Electric Device Technology Co., Ltd. Semiconductor device and method of manufacturing thereof
US20160322483A1 (en) * 2014-02-28 2016-11-03 University Of Electronic Science And Technology Of China Bidirectional insulated gate bipolar transistor
CN107785415A (en) * 2017-10-27 2018-03-09 电子科技大学 A kind of SOI RC LIGBT devices and preparation method thereof
CN108321196A (en) * 2018-02-05 2018-07-24 电子科技大学 A kind of trench gate charge storage type IGBT and preparation method thereof
CN108615707A (en) * 2018-02-13 2018-10-02 株洲中车时代电气股份有限公司 A kind of production method of the igbt chip with the compound grid structure of folded form
CN108682624A (en) * 2018-02-13 2018-10-19 株洲中车时代电气股份有限公司 A kind of igbt chip production method with composite grid

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